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cache's core response queue size control

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This commit is contained in:
Blaise Tine
2021-07-16 13:09:29 -07:00
parent a8248b334c
commit 53b3d42908
7 changed files with 51 additions and 12 deletions
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7
hw/rtl/cache/VX_bank.v vendored
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@@ -20,6 +20,8 @@ module VX_bank #(
// Core Request Queue Size
parameter CREQ_SIZE = 1,
// Core Response Queue Size
parameter CRSQ_SIZE = 1,
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 1,
// Memory Request Queue Size
@@ -474,8 +476,9 @@ module VX_bank #(
assign crsq_data = rdata_st1;
end
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS)
VX_elastic_buffer #(
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
.SIZE (CRSQ_SIZE)
) core_rsp_req (
.clk (clk),
.reset (reset),

9
hw/rtl/cache/VX_cache.v vendored
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@@ -18,13 +18,15 @@ module VX_cache #(
parameter WORD_SIZE = 4,
// Core Request Queue Size
parameter CREQ_SIZE = 4,
parameter CREQ_SIZE = 2,
// Core Response Queue Size
parameter CRSQ_SIZE = 2,
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 8,
// Memory Response Queue Size
parameter MRSQ_SIZE = 4,
// Memory Request Queue Size
parameter MREQ_SIZE = 4,
parameter MREQ_SIZE = 2,
// Enable cache writeable
parameter WRITE_ENABLE = 1,
@@ -250,7 +252,7 @@ module VX_cache #(
VX_elastic_buffer #(
.DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE),
.BUFFERED (1)
.BUFFERED (MRSQ_SIZE > 2)
) mem_rsp_queue (
.clk (clk),
.reset (reset),
@@ -436,6 +438,7 @@ module VX_cache #(
.WORD_SIZE (WORD_SIZE),
.NUM_REQS (NUM_REQS),
.CREQ_SIZE (CREQ_SIZE),
.CRSQ_SIZE (CRSQ_SIZE),
.MSHR_SIZE (MSHR_SIZE),
.MREQ_SIZE (MREQ_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),

9
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -13,7 +13,9 @@ module VX_shared_mem #(
parameter NUM_REQS = 4,
// Core Request Queue Size
parameter CREQ_SIZE = 8,
parameter CREQ_SIZE = 2,
// Core Response Queue Size
parameter CRSQ_SIZE = 2,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 8,
@@ -240,8 +242,9 @@ module VX_shared_mem #(
assign crsq_in_valid = creq_out_valid && per_bank_req_has_reads;
VX_skid_buffer #(
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH)
VX_elastic_buffer #(
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH),
.SIZE (CRSQ_SIZE)
) core_rsp_req (
.clk (clk),
.reset (reset),