adding floating extension to SimX

This commit is contained in:
Blaise Tine
2021-02-24 14:25:04 -08:00
parent 34ce0b8e89
commit 4fe345f269
11 changed files with 939 additions and 286 deletions

View File

@@ -25,6 +25,14 @@ enum Opcode {
VSET_ARITH= 0x57,
VL = 0x7,
VS = 0x27,
// F-Extension
FL = 0x7,
FS = 0x27,
FCI = 0x53,
FMADD = 0x43,
FMSUB = 0x47,
FMNMSUB = 0x4b,
FMNMADD = 0x4f,
};
enum InstType {
@@ -35,25 +43,28 @@ enum InstType {
B_TYPE,
U_TYPE,
J_TYPE,
V_TYPE
V_TYPE,
R4_TYPE
};
class Instr {
public:
Instr()
: predicated_(false)
: opcode_(Opcode::NOP)
, nRsrc_(0)
, nPsrc_(0)
, hasImmSrc_(false)
, hasRDest_(false)
, hasPDest_(false)
, func2_(0)
, func3_(0)
, func7_(0)
{}
friend std::ostream &operator<<(std::ostream &, Instr &);
/* Setters used to "craft" the instruction. */
void setOpcode(Opcode opcode) { opcode_ = opcode; }
void setPred(RegNum pReg) { predicated_ = true; pred_ = pReg; }
void setDestReg(RegNum destReg) { hasRDest_ = true; rdest_ = destReg; }
void setSrcReg(RegNum srcReg) { rsrc_[nRsrc_++] = srcReg; }
void setFunc3(Word func3) { func3_ = func3; }
@@ -69,7 +80,6 @@ public:
void setVsew(Word sew);
void setVediv(Word ediv);
void setFunc6(Word func6) { func6_ = func6; }
void setPrivileged(bool privileged) { privileged_ = privileged; }
/* Getters used by encoders. */
Opcode getOpcode() const { return opcode_; }
@@ -80,10 +90,6 @@ public:
RegNum getRSrc(RegNum i) const { return rsrc_[i]; }
bool hasRDest() const { return hasRDest_; }
RegNum getRDest() const { return rdest_; }
bool hasPDest() const { return hasPDest_; }
RegNum getPDest() const { return pdest_; }
bool hasPred() const { return predicated_; }
RegNum getPred() const { return pred_; }
bool hasImm() const { return hasImmSrc_; }
Word getImm() const { return immsrc_; }
bool getVsetImm() const { return vsetImm_; }
@@ -95,7 +101,6 @@ public:
Word getVlmul() const { return vlmul_; }
Word getVsew() const { return vsew_; }
Word getVediv() const { return vediv_; }
bool getPrivileged() const { return privileged_; }
private:
@@ -104,20 +109,16 @@ private:
};
Opcode opcode_;
bool predicated_;
RegNum pred_;
int nRsrc_;
int nPsrc_;
RegNum rsrc_[MAX_REG_SOURCES];
bool hasImmSrc_;
bool hasRDest_;
Word immsrc_;
Word func2_;
Word func3_;
Word func7_;
bool hasRDest_;
bool hasPDest_;
RegNum rsrc_[MAX_REG_SOURCES];
RegNum rdest_;
RegNum pdest_;
bool privileged_;
//Vector
bool vsetImm_;