Fixed all Cache Warnings

rtl/VX_cache/VX_cache_config.v

@@ -46,12 +46,14 @@
 //                           `vx_clog2_h(value, 31) : \
 //                           0
 
-
+// 128
 `define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS
 
-
+// 8
 `define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES)
-`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / NUMBER_BANKS)
+// 4
+`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
+// 3:0
 `define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
 
 // Offset is fixed
@@ -62,31 +64,54 @@
 `define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
 `define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
 
-`define WORD_SELECT_NUM_BITS $clog2(`BANK_LINE_SIZE_WORDS)
-`define WORD_SELECT_SIZE_END `WORD_SELECT_NUM_BITS
-`define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END
-`define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END
+// 2
+`define WORD_SELECT_NUM_BITS ($clog2(`BANK_LINE_SIZE_WORDS))
+// 2
+`define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS)
+// 2
+`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
+// 3
+`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END)
+// 3:2
 `define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
 `define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0
 
-`define BANK_SELECT_NUM_BITS $clog2(NUMBER_BANKS)
-`define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS
-`define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END
-`define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START
+// 3
+`define BANK_SELECT_NUM_BITS ($clog2(NUMBER_BANKS))
+// 3
+`define BANK_SELECT_SIZE_END (`BANK_SELECT_NUM_BITS)
+// 4
+`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
+// 6
+`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1)
+// 6:4
 `define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
+// 2:0
 `define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0
 
-`define LINE_SELECT_NUM_BITS $clog2(`BANK_LINE_COUNT)
-`define LINE_SELECT_SIZE_END `LINE_SELECT_NUM_BITS
-`define LINE_SELECT_ADDR_START 1+`BANK_SELECT_ADDR_END
-`define LINE_SELECT_ADDR_END `LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START
+// 3
+`define LINE_SELECT_NUM_BITS ($clog2(`BANK_LINE_COUNT))
+// 3
+`define LINE_SELECT_SIZE_END (`LINE_SELECT_NUM_BITS)
+// 7
+`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
+// 9
+`define LINE_SELECT_ADDR_END (`LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START-1)
+// 9:7
 `define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
+// 2:0
 `define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0
 
-`define TAG_SELECT_NUM_BITS   32-(`OFFSET_ADDR_NUM_BITS + `WORD_SELECT_NUM_BITS + `BANK_SELECT_NUM_BITS + `LINE_SELECT_NUM_BITS)
-`define TAG_SELECT_SIZE_END   `TAG_SELECT_NUM_BITS
-`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_END
+
+// 10
+`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
+// 31:10
 `define TAG_SELECT_ADDR_RNG  31:`TAG_SELECT_ADDR_START
+// 22
+`define TAG_SELECT_NUM_BITS  (32-`TAG_SELECT_ADDR_START)
+// 22
+`define TAG_SELECT_SIZE_END   (`TAG_SELECT_NUM_BITS)
+// 21:0
 `define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0