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cache bank pipeline optimization

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Blaise Tine
2021-09-14 02:09:35 -07:00
parent 3d7baf1640
commit 4e8293c3e3
5 changed files with 138 additions and 148 deletions
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2
hw/rtl/VX_config.vh
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@@ -38,7 +38,7 @@
`endif
`ifndef L1_BLOCK_SIZE
`define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? (`NUM_THREADS * 4) : `MEM_BLOCK_SIZE)
`define L1_BLOCK_SIZE ((`L2_ENABLE || `L3_ENABLE) ? 16 : `MEM_BLOCK_SIZE)
`endif
`ifndef STARTUP_ADDR