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Fixed most of the cache issues, mat_add left

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This commit is contained in:
felsabbagh3
2020-03-22 15:59:45 -07:00
parent d146070275
commit 4e6de0dc38
9 changed files with 29220 additions and 28624 deletions
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11
rtl/VX_cache/VX_cache_miss_resrv.v
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@@ -71,7 +71,7 @@ module VX_cache_miss_resrv
output wire miss_resrv_valid_st0,
output wire[31:0] miss_resrv_addr_st0,
output wire[`WORD_SIZE_RNG] miss_resrv_data_st0,
output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[4:0] miss_resrv_rd_st0,
output wire[1:0] miss_resrv_wb_st0,
output wire[`NW_M1:0] miss_resrv_warp_num_st0,
@@ -90,8 +90,11 @@ module VX_cache_miss_resrv
reg[`vx_clog2(MRVQ_SIZE)-1:0] head_ptr;
reg[`vx_clog2(MRVQ_SIZE)-1:0] tail_ptr;
reg[31:0] size;
assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
// assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE);
wire enqueue_possible = !miss_resrv_full;
@@ -108,7 +111,7 @@ module VX_cache_miss_resrv
wire dequeue_possible = valid_table[head_ptr] && ready_table[head_ptr];
wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
wire[`vx_clog2(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_pc_st0 = pc_table[dequeue_index];
@@ -126,6 +129,7 @@ module VX_cache_miss_resrv
pc_table <= 0;
end else begin
if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin
size <= size + 1;
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= 0;
pc_table[enqueue_index] <= miss_add_pc;
@@ -139,6 +143,7 @@ module VX_cache_miss_resrv
end
if (miss_resrv_pop && dequeue_possible) begin
size <= size - 1;
valid_table[dequeue_index] <= 0;
ready_table[dequeue_index] <= 0;
addr_table[dequeue_index] <= 0;

6
rtl/VX_cache/VX_tag_data_access.v
View File

@@ -94,7 +94,7 @@ module VX_tag_data_access
wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data;
wire real_writefill = writefill_st1e && miss_st1e;
wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)));
wire fill_sent;
@@ -238,14 +238,14 @@ module VX_tag_data_access
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e;
wire force_write = writefill_st1e && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e));
wire force_write = real_writefill && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e));
wire[`DBANK_LINE_SIZE_RNG][3:0] we;
wire[`DBANK_LINE_SIZE_RNG][31:0] data_write;
genvar g;
generate
for (g = 0; g < `DBANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables
wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !writefill_st1e;
wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill;
assign we[g] = (force_write) ? 4'b1111 :
(normal_write && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :

6
rtl/simulate/test_bench.cpp
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@@ -12,7 +12,7 @@ int main(int argc, char **argv)
Verilated::traceEverOn(true);
#define ALL_TESTS
// #define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
@@ -88,9 +88,9 @@ int main(int argc, char **argv)
#else
// char testing[] = "../../runtime/mains/simple/vx_simple_main.hex";
char testing[] = "../../runtime/mains/simple/vx_simple_main.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
// const char *testing;