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scope refactoring

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This commit is contained in:
Blaise Tine
2020-10-03 18:53:21 -04:00
parent 878c89861b
commit 4e1007e5b2
28 changed files with 1014 additions and 693 deletions
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27
hw/rtl/VX_cluster.v
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@@ -3,11 +3,14 @@
module VX_cluster #(
parameter CLUSTER_ID = 0
) (
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_ISSUE_IO
`SCOPE_SIGNALS_EXECUTE_IO
`SCOPE_SIGNALS_ISTAGE_CLUSTER_IO
`SCOPE_SIGNALS_LSU_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L2_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L1D_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L1I_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L1S_CLUSTER_IO
`SCOPE_SIGNALS_ISSUE_CLUSTER_IO
`SCOPE_SIGNALS_EXECUTE_CLUSTER_IO
// Clock
input wire clk,
@@ -138,11 +141,13 @@ module VX_cluster #(
VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) core (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_SELECT(i)
`SCOPE_SIGNALS_LSU_SELECT(i)
`SCOPE_SIGNALS_BANK_L1D_CORE_SELECT(i)
`SCOPE_SIGNALS_BANK_L1I_CORE_SELECT(i)
`SCOPE_SIGNALS_BANK_L1S_CORE_SELECT(i)
`SCOPE_SIGNALS_ISSUE_SELECT(i)
`SCOPE_SIGNALS_EXECUTE_SELECT(i)
.clk (clk),
.reset (reset),
@@ -380,7 +385,7 @@ module VX_cluster #(
.SNP_REQ_TAG_WIDTH (`L2SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`DSNP_TAG_WIDTH)
) l2cache (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L2_CACHE_BIND
.clk (clk),
.reset (reset),

8
hw/rtl/VX_core.v
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@@ -5,7 +5,9 @@ module VX_core #(
) (
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_L1D_CORE_IO
`SCOPE_SIGNALS_BANK_L1I_CORE_IO
`SCOPE_SIGNALS_BANK_L1S_CORE_IO
`SCOPE_SIGNALS_ISSUE_IO
`SCOPE_SIGNALS_EXECUTE_IO
@@ -258,7 +260,9 @@ module VX_core #(
VX_mem_unit #(
.CORE_ID(CORE_ID)
) mem_unit (
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_BANK_L1D_CORE_BIND
`SCOPE_SIGNALS_BANK_L1I_CORE_BIND
`SCOPE_SIGNALS_BANK_L1S_CORE_BIND
.clk (clk),
.reset (reset),

8
hw/rtl/VX_define.vh
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@@ -248,7 +248,7 @@
////////////////////////// Dcache Configurable Knobs //////////////////////////
// Cache ID
`define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0)
`define DCACHE_ID 32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0
// TAG sharing enable
`define DCORE_TAG_ID_BITS `LOG2UP(`LSUQ_SIZE)
@@ -277,7 +277,7 @@
////////////////////////// Icache Configurable Knobs //////////////////////////
// Cache ID
`define ICACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 1)
`define ICACHE_ID 32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1
// Core request address bits
`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE))
@@ -309,7 +309,7 @@
////////////////////////// SM Configurable Knobs //////////////////////////////
// Cache ID
`define SCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 2)
`define SCACHE_ID 32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define SNUM_REQUESTS `NUM_THREADS
@@ -326,7 +326,7 @@
////////////////////////// L2cache Configurable Knobs /////////////////////////
// Cache ID
`define L2CACHE_ID (`L3_ENABLE ? 1 : 0)
`define L2CACHE_ID 32'(`L3_ENABLE) + CLUSTER_ID
// Core request tag bits
`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))

10
hw/rtl/VX_mem_unit.v
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@@ -3,7 +3,9 @@
module VX_mem_unit # (
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_L1D_CORE_IO
`SCOPE_SIGNALS_BANK_L1I_CORE_IO
`SCOPE_SIGNALS_BANK_L1S_CORE_IO
input wire clk,
input wire reset,
@@ -77,7 +79,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) smem (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L1S_CACHE_BIND
.clk (clk),
.reset (reset),
@@ -159,7 +161,7 @@ module VX_mem_unit # (
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) dcache (
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_BANK_L1D_CACHE_BIND
.clk (clk),
.reset (reset),
@@ -240,7 +242,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) icache (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L1I_CACHE_BIND
.clk (clk),
.reset (reset),

2
hw/rtl/VX_platform.vh
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@@ -41,7 +41,7 @@
`define STATIC_ASSERT(cond, msg) \
generate \
if (!(cond)) $error(msg); \
if (!(cond)) $error msg; \
endgenerate
`define ENABLE_TRACING /* verilator tracing_on */

467
hw/rtl/VX_scope.vh
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@@ -1,400 +1,89 @@
`ifndef VX_SCOPE
`define VX_SCOPE
`ifdef SCOPE
`define SCOPE_SIGNALS_DATA_LIST \
scope_dram_req_addr, \
scope_dram_req_rw, \
scope_dram_req_byteen, \
scope_dram_req_data, \
scope_dram_req_tag, \
scope_dram_rsp_data, \
scope_dram_rsp_tag, \
scope_snp_req_addr, \
scope_snp_req_invalidate, \
scope_snp_req_tag, \
scope_snp_rsp_tag, \
scope_icache_req_wid, \
scope_icache_req_addr, \
scope_icache_req_tag, \
scope_icache_rsp_data, \
scope_icache_rsp_tag, \
scope_dcache_req_wid, \
scope_dcache_req_pc, \
scope_dcache_req_addr, \
scope_dcache_req_rw, \
scope_dcache_req_byteen, \
scope_dcache_req_data, \
scope_dcache_req_tag, \
scope_dcache_rsp_data, \
scope_dcache_rsp_tag, \
scope_issue_wid, \
scope_issue_tmask, \
scope_issue_pc, \
scope_issue_ex_type, \
scope_issue_op_type, \
scope_issue_op_mod, \
scope_issue_wb, \
scope_issue_rd, \
scope_issue_rs1, \
scope_issue_rs2, \
scope_issue_rs3, \
scope_issue_imm, \
scope_issue_rs1_is_pc, \
scope_issue_rs2_is_imm, \
scope_gpr_rsp_wid, \
scope_gpr_rsp_pc, \
scope_gpr_rsp_a, \
scope_gpr_rsp_b, \
scope_gpr_rsp_c, \
scope_writeback_wid, \
scope_writeback_pc, \
scope_writeback_rd, \
scope_writeback_data, \
scope_bank_addr_st0, \
scope_bank_addr_st1, \
scope_bank_addr_st2, \
scope_bank_is_mrvq_st1, \
scope_bank_miss_st1, \
scope_bank_dirty_st1, \
scope_bank_force_miss_st1,
`define SCOPE_SIGNALS_UPD_LIST \
scope_dram_req_valid, \
scope_dram_req_ready, \
scope_dram_rsp_valid, \
scope_dram_rsp_ready, \
scope_snp_req_valid, \
scope_snp_req_ready, \
scope_snp_rsp_valid, \
scope_snp_rsp_ready, \
scope_icache_req_valid, \
scope_icache_req_ready, \
scope_icache_rsp_valid, \
scope_icache_rsp_ready, \
scope_dcache_req_valid, \
scope_dcache_req_ready, \
scope_dcache_rsp_valid, \
scope_dcache_rsp_ready, \
scope_bank_valid_st0, \
scope_bank_valid_st1, \
scope_bank_valid_st2, \
scope_bank_stall_pipe, \
scope_issue_valid, \
scope_issue_ready, \
scope_gpr_rsp_valid, \
scope_writeback_valid, \
scope_scoreboard_delay, \
scope_gpr_delay, \
scope_execute_delay, \
scope_busy
`include "scope-defs.vh"
`define SCOPE_SIGNALS_DECL \
wire scope_dram_req_valid; \
wire [31:0] scope_dram_req_addr; \
wire scope_dram_req_rw; \
wire [15:0] scope_dram_req_byteen; \
wire [127:0] scope_dram_req_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
wire scope_dram_req_ready; \
wire scope_dram_rsp_valid; \
wire [127:0] scope_dram_rsp_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \
wire scope_snp_req_valid; \
wire [31:0] scope_snp_req_addr; \
wire scope_snp_req_invalidate; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
wire scope_snp_req_ready; \
wire scope_snp_rsp_valid; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
wire scope_icache_req_valid; \
wire [`NW_BITS-1:0] scope_icache_req_wid; \
wire [31:0] scope_icache_req_addr; \
wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \
wire [31:0] scope_icache_rsp_data; \
wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \
wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \
wire [`NW_BITS-1:0] scope_dcache_req_wid; \
wire [31:0] scope_dcache_req_pc; \
wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr; \
wire scope_dcache_req_rw; \
wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen; \
wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data; \
wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \
wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \
wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data; \
wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_snp_rsp_ready; \
wire [`NW_BITS-1:0] scope_issue_wid; \
wire [`NUM_THREADS-1:0] scope_issue_tmask; \
wire [31:0] scope_issue_pc; \
wire [`EX_BITS-1:0] scope_issue_ex_type; \
wire [`OP_BITS-1:0] scope_issue_op_type; \
wire [`MOD_BITS-1:0] scope_issue_op_mod; \
wire scope_issue_wb; \
wire [`NR_BITS-1:0] scope_issue_rd; \
wire [`NR_BITS-1:0] scope_issue_rs1; \
wire [`NR_BITS-1:0] scope_issue_rs2; \
wire [`NR_BITS-1:0] scope_issue_rs3; \
wire [31:0] scope_issue_imm; \
wire scope_issue_rs1_is_pc; \
wire scope_issue_rs2_is_imm; \
wire scope_gpr_rsp_valid; \
wire [`NW_BITS-1:0] scope_gpr_rsp_wid; \
wire [31:0] scope_gpr_rsp_pc; \
wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a; \
wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b; \
wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c; \
wire scope_writeback_valid; \
wire [`NW_BITS-1:0] scope_writeback_wid; \
wire [31:0] scope_writeback_pc; \
wire [`NR_BITS-1:0] scope_writeback_rd; \
wire [`NUM_THREADS-1:0][31:0] scope_writeback_data; \
wire scope_bank_valid_st0; \
wire scope_bank_valid_st1; \
wire scope_bank_valid_st2; \
wire [31:0] scope_bank_addr_st0; \
wire [31:0] scope_bank_addr_st1; \
wire [31:0] scope_bank_addr_st2; \
wire scope_bank_is_mrvq_st1; \
wire scope_bank_miss_st1; \
wire scope_bank_dirty_st1; \
wire scope_bank_force_miss_st1; \
wire scope_bank_stall_pipe; \
wire scope_issue_valid; \
wire scope_issue_ready; \
wire scope_scoreboard_delay; \
wire scope_gpr_delay; \
wire scope_execute_delay; \
wire scope_busy;
`define SCOPE_ASSIGN(d,s) assign d = s
`define SCOPE_SIGNALS_ISTAGE_IO \
output wire scope_icache_req_valid, \
output wire [`NW_BITS-1:0] scope_icache_req_wid, \
output wire [31:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \
output wire [31:0] scope_icache_rsp_data, \
output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag, \
output wire scope_icache_rsp_ready,
`define SCOPE_SIGNALS_LSU_IO \
output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \
output wire [`NW_BITS-1:0] scope_dcache_req_wid, \
output wire [31:0] scope_dcache_req_pc, \
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr, \
output wire scope_dcache_req_rw, \
output wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen, \
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data, \
output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \
output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data, \
output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready,
`define SCOPE_SIGNALS_CACHE_IO \
output wire scope_bank_valid_st0, \
output wire scope_bank_valid_st1, \
output wire scope_bank_valid_st2, \
output wire [31:0] scope_bank_addr_st0, \
output wire [31:0] scope_bank_addr_st1, \
output wire [31:0] scope_bank_addr_st2, \
output wire scope_bank_is_mrvq_st1, \
output wire scope_bank_miss_st1, \
output wire scope_bank_dirty_st1, \
output wire scope_bank_force_miss_st1, \
output wire scope_bank_stall_pipe,
`define SCOPE_SIGNALS_ISSUE_IO \
output wire scope_issue_valid, \
output wire [`NW_BITS-1:0] scope_issue_wid, \
output wire [`NUM_THREADS-1:0] scope_issue_tmask, \
output wire [31:0] scope_issue_pc, \
output wire [`EX_BITS-1:0] scope_issue_ex_type, \
output wire [`OP_BITS-1:0] scope_issue_op_type, \
output wire [`MOD_BITS-1:0] scope_issue_op_mod, \
output wire scope_issue_wb, \
output wire [`NR_BITS-1:0] scope_issue_rd, \
output wire [`NR_BITS-1:0] scope_issue_rs1, \
output wire [`NR_BITS-1:0] scope_issue_rs2, \
output wire [`NR_BITS-1:0] scope_issue_rs3, \
output wire [31:0] scope_issue_imm, \
output wire scope_issue_rs1_is_pc, \
output wire scope_issue_rs2_is_imm, \
output wire scope_writeback_valid, \
output wire scope_gpr_rsp_valid, \
output wire [`NW_BITS-1:0] scope_gpr_rsp_wid, \
output wire [31:0] scope_gpr_rsp_pc, \
output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a, \
output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b, \
output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c, \
output wire [`NW_BITS-1:0] scope_writeback_wid, \
output wire [31:0] scope_writeback_pc, \
output wire [`NR_BITS-1:0] scope_writeback_rd, \
output wire [`NUM_THREADS-1:0][31:0] scope_writeback_data, \
output wire scope_issue_ready, \
output wire scope_scoreboard_delay, \
output wire scope_gpr_delay, \
output wire scope_execute_delay,
`define SCOPE_SIGNALS_EXECUTE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_wid (scope_icache_req_wid), \
.scope_icache_req_addr (scope_icache_req_addr), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
.scope_icache_rsp_valid (scope_icache_rsp_valid), \
.scope_icache_rsp_data (scope_icache_rsp_data), \
.scope_icache_rsp_tag (scope_icache_rsp_tag), \
.scope_icache_rsp_ready (scope_icache_rsp_ready),
`define SCOPE_SIGNALS_LSU_BIND \
.scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_wid (scope_dcache_req_wid), \
.scope_dcache_req_pc (scope_dcache_req_pc), \
.scope_dcache_req_addr (scope_dcache_req_addr), \
.scope_dcache_req_rw (scope_dcache_req_rw), \
.scope_dcache_req_byteen(scope_dcache_req_byteen), \
.scope_dcache_req_data (scope_dcache_req_data), \
.scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_data (scope_dcache_rsp_data), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
`define SCOPE_SIGNALS_CACHE_BIND \
.scope_bank_valid_st0 (scope_bank_valid_st0), \
.scope_bank_valid_st1 (scope_bank_valid_st1), \
.scope_bank_valid_st2 (scope_bank_valid_st2), \
.scope_bank_addr_st0 (scope_bank_addr_st0), \
.scope_bank_addr_st1 (scope_bank_addr_st1), \
.scope_bank_addr_st2 (scope_bank_addr_st2), \
.scope_bank_is_mrvq_st1 (scope_bank_is_mrvq_st1), \
.scope_bank_miss_st1 (scope_bank_miss_st1), \
.scope_bank_dirty_st1 (scope_bank_dirty_st1), \
.scope_bank_force_miss_st1(scope_bank_force_miss_st1), \
.scope_bank_stall_pipe (scope_bank_stall_pipe),
`define SCOPE_SIGNALS_CACHE_UNBIND \
/* verilator lint_off PINCONNECTEMPTY */ \
.scope_bank_valid_st0 (), \
.scope_bank_valid_st1 (), \
.scope_bank_valid_st2 (), \
.scope_bank_addr_st0 (), \
.scope_bank_addr_st1 (), \
.scope_bank_addr_st2 (), \
.scope_bank_is_mrvq_st1 (), \
.scope_bank_miss_st1 (), \
.scope_bank_dirty_st1 (), \
.scope_bank_force_miss_st1 (), \
.scope_bank_stall_pipe (), \
/* verilator lint_on PINCONNECTEMPTY */
`define SCOPE_SIGNALS_CACHE_BANK_SELECT \
/* verilator lint_off UNUSED */ \
wire [NUM_BANKS-1:0] scope_per_bank_valid_st0; \
wire [NUM_BANKS-1:0] scope_per_bank_valid_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_valid_st2; \
wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st0; \
wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st1; \
wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st2; \
wire [NUM_BANKS-1:0] scope_per_bank_is_mrvq_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_miss_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_dirty_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_force_miss_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_stall_pipe; \
/* verilator lint_on UNUSED */ \
assign scope_bank_valid_st0 = scope_per_bank_valid_st0[0]; \
assign scope_bank_valid_st1 = scope_per_bank_valid_st1[0]; \
assign scope_bank_valid_st2 = scope_per_bank_valid_st2[0]; \
assign scope_bank_addr_st0 = scope_per_bank_addr_st0[0]; \
assign scope_bank_addr_st1 = scope_per_bank_addr_st1[0]; \
assign scope_bank_addr_st2 = scope_per_bank_addr_st2[0]; \
assign scope_bank_is_mrvq_st1 = scope_per_bank_is_mrvq_st1[0]; \
assign scope_bank_miss_st1 = scope_per_bank_miss_st1[0]; \
assign scope_bank_dirty_st1 = scope_per_bank_dirty_st1[0]; \
assign scope_bank_force_miss_st1 = scope_per_bank_force_miss_st1[0]; \
assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0];
`define SCOPE_SIGNALS_CACHE_BANK_BIND \
.scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \
.scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \
.scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \
.scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \
.scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \
.scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \
.scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \
.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
.scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \
.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),
`define SCOPE_SIGNALS_ISSUE_BIND \
.scope_issue_valid (scope_issue_valid), \
.scope_issue_wid (scope_issue_wid), \
.scope_issue_tmask (scope_issue_tmask), \
.scope_issue_pc (scope_issue_pc), \
.scope_issue_ex_type (scope_issue_ex_type), \
.scope_issue_op_type (scope_issue_op_type), \
.scope_issue_op_mod (scope_issue_op_mod), \
.scope_issue_wb (scope_issue_wb), \
.scope_issue_rd (scope_issue_rd), \
.scope_issue_rs1 (scope_issue_rs1), \
.scope_issue_rs2 (scope_issue_rs2), \
.scope_issue_rs3 (scope_issue_rs3), \
.scope_issue_imm (scope_issue_imm), \
.scope_issue_rs1_is_pc (scope_issue_rs1_is_pc), \
.scope_issue_rs2_is_imm (scope_issue_rs2_is_imm), \
.scope_writeback_valid (scope_writeback_valid), \
.scope_writeback_wid (scope_writeback_wid), \
.scope_writeback_pc (scope_writeback_pc), \
.scope_writeback_rd (scope_writeback_rd), \
.scope_writeback_data (scope_writeback_data), \
.scope_issue_ready (scope_issue_ready), \
.scope_gpr_rsp_valid (scope_gpr_rsp_valid), \
.scope_gpr_rsp_wid (scope_gpr_rsp_wid), \
.scope_gpr_rsp_pc (scope_gpr_rsp_pc), \
.scope_gpr_rsp_a (scope_gpr_rsp_a), \
.scope_gpr_rsp_b (scope_gpr_rsp_b), \
.scope_gpr_rsp_c (scope_gpr_rsp_c), \
.scope_scoreboard_delay (scope_scoreboard_delay), \
.scope_gpr_delay (scope_gpr_delay), \
.scope_execute_delay (scope_execute_delay), \
`define SCOPE_SIGNALS_EXECUTE_BIND
`define SCOPE_ASSIGN(d,s) assign d = s
`else
`define SCOPE_SIGNALS_ISTAGE_IO
`define SCOPE_SIGNALS_LSU_IO
`define SCOPE_SIGNALS_CACHE_IO
`define SCOPE_SIGNALS_ISSUE_IO
`define SCOPE_SIGNALS_EXECUTE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND
`define SCOPE_SIGNALS_LSU_BIND
`define SCOPE_SIGNALS_CACHE_BIND
`define SCOPE_SIGNALS_ISSUE_BIND
`define SCOPE_SIGNALS_EXECUTE_BIND
`define SCOPE_SIGNALS_CACHE_UNBIND
`define SCOPE_SIGNALS_CACHE_BANK_SELECT
`define SCOPE_SIGNALS_CACHE_BANK_BIND
`define SCOPE_ASSIGN(d,s)
`define SCOPE_SIGNALS_ISTAGE_TOP_IO
`define SCOPE_SIGNALS_ISTAGE_TOP_BIND
`define SCOPE_SIGNALS_ISTAGE_CLUSTER_IO
`define SCOPE_SIGNALS_ISTAGE_CLUSTER_BIND
`define SCOPE_SIGNALS_ISTAGE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND
`define SCOPE_SIGNALS_ISTAGE_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_ISTAGE_SELECT(__i__)
`define SCOPE_SIGNALS_LSU_TOP_IO
`define SCOPE_SIGNALS_LSU_TOP_BIND
`define SCOPE_SIGNALS_LSU_CLUSTER_IO
`define SCOPE_SIGNALS_LSU_CLUSTER_BIND
`define SCOPE_SIGNALS_LSU_IO
`define SCOPE_SIGNALS_LSU_BIND
`define SCOPE_SIGNALS_LSU_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_LSU_SELECT(__i__)
`define SCOPE_SIGNALS_ISSUE_TOP_IO
`define SCOPE_SIGNALS_ISSUE_TOP_BIND
`define SCOPE_SIGNALS_ISSUE_CLUSTER_IO
`define SCOPE_SIGNALS_ISSUE_CLUSTER_BIND
`define SCOPE_SIGNALS_ISSUE_IO
`define SCOPE_SIGNALS_ISSUE_BIND
`define SCOPE_SIGNALS_ISSUE_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_ISSUE_SELECT(__i__)
`define SCOPE_SIGNALS_EXECUTE_TOP_IO
`define SCOPE_SIGNALS_EXECUTE_TOP_BIND
`define SCOPE_SIGNALS_EXECUTE_CLUSTER_IO
`define SCOPE_SIGNALS_EXECUTE_CLUSTER_BIND
`define SCOPE_SIGNALS_EXECUTE_IO
`define SCOPE_SIGNALS_EXECUTE_BIND
`define SCOPE_SIGNALS_EXECUTE_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_EXECUTE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L3_TOP_IO
`define SCOPE_SIGNALS_BANK_L3_TOP_BIND
`define SCOPE_SIGNALS_BANK_L2_TOP_IO
`define SCOPE_SIGNALS_BANK_L2_TOP_BIND
`define SCOPE_SIGNALS_BANK_L1D_TOP_IO
`define SCOPE_SIGNALS_BANK_L1D_TOP_BIND
`define SCOPE_SIGNALS_BANK_L1I_TOP_IO
`define SCOPE_SIGNALS_BANK_L1I_TOP_BIND
`define SCOPE_SIGNALS_BANK_L1S_TOP_IO
`define SCOPE_SIGNALS_BANK_L1S_TOP_BIND
`define SCOPE_SIGNALS_BANK_L2_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L2_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1D_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L1D_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1I_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L1I_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1S_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L1S_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1D_CORE_IO
`define SCOPE_SIGNALS_BANK_L1D_CORE_BIND
`define SCOPE_SIGNALS_BANK_L1I_CORE_IO
`define SCOPE_SIGNALS_BANK_L1I_CORE_BIND
`define SCOPE_SIGNALS_BANK_L1S_CORE_IO
`define SCOPE_SIGNALS_BANK_L1S_CORE_BIND
`define SCOPE_SIGNALS_BANK_CACHE_IO
`define SCOPE_SIGNALS_BANK_CACHE_BIND
`define SCOPE_SIGNALS_BANK_IO
`define SCOPE_SIGNALS_BANK_BIND
`define SCOPE_SIGNALS_BANK_L2_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1D_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1I_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1S_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1D_CORE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1I_CORE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1S_CORE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L3_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L2_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L1D_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L1I_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L1S_CACHE_BIND
`define SCOPE_SIGNALS_BANK_SELECT(__i__)
`define SCOPE_ASSIGN(d,s)
`endif
// VX_SCOPE
`endif

44
hw/rtl/Vortex.v
View File

@@ -1,11 +1,15 @@
`include "VX_define.vh"
module Vortex (
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_ISSUE_IO
`SCOPE_SIGNALS_EXECUTE_IO
`SCOPE_SIGNALS_ISTAGE_TOP_IO
`SCOPE_SIGNALS_LSU_TOP_IO
`SCOPE_SIGNALS_BANK_L3_TOP_IO
`SCOPE_SIGNALS_BANK_L2_TOP_IO
`SCOPE_SIGNALS_BANK_L1D_TOP_IO
`SCOPE_SIGNALS_BANK_L1I_TOP_IO
`SCOPE_SIGNALS_BANK_L1S_TOP_IO
`SCOPE_SIGNALS_ISSUE_TOP_IO
`SCOPE_SIGNALS_EXECUTE_TOP_IO
// Clock
input wire clk,
@@ -75,11 +79,14 @@ module Vortex (
VX_cluster #(
.CLUSTER_ID(0)
) cluster (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_LSU_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L2_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L1D_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L1I_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L1S_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_ISSUE_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_EXECUTE_CLUSTER_SELECT(0)
.clk (clk),
.reset (reset),
@@ -193,11 +200,14 @@ module Vortex (
VX_cluster #(
.CLUSTER_ID(i)
) cluster (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_LSU_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L2_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L1D_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L1I_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L1S_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_ISSUE_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_EXECUTE_CLUSTER_SELECT(i)
.clk (clk),
.reset (reset),
@@ -384,7 +394,7 @@ module Vortex (
assign l3_core_rsp_ready = (& per_cluster_dram_rsp_ready);
VX_cache #(
.CACHE_ID (0),
.CACHE_ID (`L3CACHE_ID),
.CACHE_SIZE (`L3CACHE_SIZE),
.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
.NUM_BANKS (`L3NUM_BANKS),
@@ -407,7 +417,7 @@ module Vortex (
.SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH)
) l3cache (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L3_CACHE_BIND
.clk (clk),
.reset (reset),

2
hw/rtl/cache/VX_bank.v vendored
View File

@@ -50,7 +50,7 @@ module VX_bank #(
// Snooping request tag width
parameter SNP_REQ_TAG_WIDTH = 0
) (
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_IO
input wire clk,
input wire reset,

6
hw/rtl/cache/VX_cache.v vendored
View File

@@ -59,7 +59,7 @@ module VX_cache #(
// Snooping forward tag width
parameter SNP_FWD_TAG_WIDTH = 1
) (
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_CACHE_IO
input wire clk,
input wire reset,
@@ -162,8 +162,6 @@ module VX_cache #(
wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
`SCOPE_SIGNALS_CACHE_BANK_SELECT
wire snp_req_valid_qual;
wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr_qual;
wire snp_req_invalidate_qual;
@@ -367,7 +365,7 @@ module VX_cache #(
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
) bank (
`SCOPE_SIGNALS_CACHE_BANK_BIND
`SCOPE_SIGNALS_BANK_SELECT(i)
.clk (clk),
.reset (reset),

1
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -2,7 +2,6 @@
`define VX_CACHE_CONFIG
`include "VX_platform.vh"
`include "VX_scope.vh"
`ifdef DBG_CORE_REQ_INFO
`include "VX_define.vh"

2
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -66,7 +66,7 @@ module VX_cache_miss_resrv #(
reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size")
`STATIC_ASSERT(MRVQ_SIZE > 5, ("invalid size"))
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -37,7 +37,7 @@ module VX_snp_forwarder #(
input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
);
`STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value")
`STATIC_ASSERT(NUM_REQUESTS > 1, ("invalid value"))
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];

2
hw/rtl/libs/VX_generic_queue.v
View File

@@ -17,7 +17,7 @@ module VX_generic_queue #(
output wire full,
output wire [SIZEW-1:0] size
);
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
`STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!"))
reg [SIZEW-1:0] size_r;
wire reading;