diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v
index 87524ca6..45904300 100644
--- a/hw/rtl/VX_execute.v
+++ b/hw/rtl/VX_execute.v
@@ -80,10 +80,14 @@ module VX_execute #(
     for (genvar i = 0; i < `NUM_THREADS; ++i) begin
         assign lsu_tag_in[i][`LSUQ_ADDR_BITS-1:0] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS-1:0];
         assign lsu_tag_in[i][`LSUQ_ADDR_BITS+:2] = '0;
+    `ifdef DBG_CACHE_REQ_INFO
         assign lsu_tag_in[i][(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW];
+    `endif
     end
     assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0] = lsu_tag_out[`LSUQ_ADDR_BITS-1:0];
+`ifdef DBG_CACHE_REQ_INFO
     assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW] = lsu_tag_out[(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW];
+`endif
     `UNUSED_VAR (lsu_tag_out)
 
     VX_tex_lsu_arb #(
diff --git a/hw/rtl/tex_unit/VX_tex_define.vh b/hw/rtl/tex_unit/VX_tex_define.vh
index f73413e0..c61648de 100644
--- a/hw/rtl/tex_unit/VX_tex_define.vh
+++ b/hw/rtl/tex_unit/VX_tex_define.vh
@@ -9,7 +9,7 @@
 `define FIXED_HALF      (`FIXED_ONE >> 1)
 `define FIXED_MASK      (`FIXED_ONE - 1)
 
-`define CLAMP(x,lo,hi)  ((x < lo) ? lo : ((x > hi) ? hi : x))
+`define CLAMP(x,lo,hi)  (($signed(x) < $signed(lo)) ? lo : ((x > hi) ? hi : x))
 
 `define BLEND_FRAC_64    8
 
diff --git a/hw/rtl/tex_unit/VX_tex_memory.v b/hw/rtl/tex_unit/VX_tex_memory.v
index 3a9f0aaf..2457bd87 100644
--- a/hw/rtl/tex_unit/VX_tex_memory.v
+++ b/hw/rtl/tex_unit/VX_tex_memory.v
@@ -179,7 +179,9 @@ module VX_tex_memory #(
 `ifdef DBG_CACHE_REQ_INFO
     assign dcache_req_if.tag = {`NUM_THREADS{q_req_PC, q_req_wid, texel_idx, q_ib_waddr}};
 `else
-    assign dcache_req_if.tag = {`NUM_THREADS{q_ib_waddr}};
+    assign dcache_req_if.tag = {`NUM_THREADS{texel_idx, q_ib_waddr}};
+    `UNUSED_VAR (q_req_wid)
+    `UNUSED_VAR (q_req_PC)
 `endif
 
     // Dcache Response
@@ -215,7 +217,7 @@ module VX_tex_memory #(
 
     assign mbuf_raddr = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0];
 
-    assign rsp_texel_idx = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1+:2];
+    assign rsp_texel_idx = dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:2];
 
     assign rsp_is_dup = ib_dup_reqs[rsp_texel_idx];
 
diff --git a/hw/rtl/tex_unit/VX_tex_wrap.v b/hw/rtl/tex_unit/VX_tex_wrap.v
index d6b0bb2e..75857f8f 100644
--- a/hw/rtl/tex_unit/VX_tex_wrap.v
+++ b/hw/rtl/tex_unit/VX_tex_wrap.v
@@ -14,6 +14,8 @@ module VX_tex_wrap #(
 
     wire [31:0] clamp = `CLAMP(coord_i, 0, `FIXED_MASK);
 
+    `UNUSED_VAR (clamp)
+
     always @(*) begin
         case (wrap_i)
             `TEX_WRAP_CLAMP: