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cache refactoring - phase 3 - added dedicated pipeline stage for tag access

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This commit is contained in:
Blaise Tine
2020-11-04 03:21:30 -08:00
parent cd8ce20bd6
commit 4c6a74fa87
11 changed files with 545 additions and 339 deletions
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2
hw/rtl/VX_decode.v
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@@ -295,7 +295,7 @@ module VX_decode #(
wire use_rs1 = is_fpu
|| is_gpu
|| ((is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || ~is_csr_imm || is_gpu) && (rs1 != 0));
|| ((is_jalr || is_btype || is_ltype || is_stype || is_itype || is_rtype || !is_csr_imm || is_gpu) && (rs1 != 0));
wire use_rs2 = (is_fpu && ~(is_fl || (fpu_op == `FPU_SQRT) || is_fcvti || is_fcvtf || is_fmvw_clss || is_fmvx))
|| (is_gpu && (gpu_op == `GPU_BAR || gpu_op == `GPU_WSPAWN))