performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
--- a/hw/syn/quartus/project.sdc
+++ b/hw/syn/quartus/project.sdc
@@ -1,6 +1,6 @@
 set_time_format -unit ns -decimal_places 3

-create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
+create_clock -name {clk} -period "220 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

 derive_pll_clocks -create_base_clocks
 derive_clock_uncertainty