performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
--- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v
+++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v
@@ -8,12 +8,10 @@ interface VX_cache_dram_rsp_if #(
    parameter DRAM_TAG_WIDTH  = 1
 ) ();

-    wire                        valid;
-    
-    wire [DRAM_LINE_WIDTH-1:0]  data;
-    wire [DRAM_TAG_WIDTH-1:0]   tag;  
-
-    wire                        ready;      
+    wire                       valid;    
+    wire [DRAM_LINE_WIDTH-1:0] data;
+    wire [DRAM_TAG_WIDTH-1:0]  tag;  
+    wire                       ready;      

 endinterface