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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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4
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -6,7 +6,6 @@
interface VX_alu_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -20,8 +19,7 @@ interface VX_alu_req_if ();
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire wb;
wire ready;
endinterface

8
hw/rtl/interfaces/VX_cache_core_rsp_if.v
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@@ -10,12 +10,10 @@ interface VX_cache_core_rsp_if #(
parameter CORE_TAG_ID_BITS = 0
) ();
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [NUM_REQS-1:0] valid;
wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag;
wire ready;
wire ready;
endinterface

6
hw/rtl/interfaces/VX_cache_dram_req_if.v
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@@ -9,14 +9,12 @@ interface VX_cache_dram_req_if #(
parameter DRAM_TAG_WIDTH = 1
) ();
wire valid;
wire valid;
wire rw;
wire [(DRAM_LINE_WIDTH/8)-1:0] byteen;
wire [DRAM_ADDR_WIDTH-1:0] addr;
wire [DRAM_LINE_WIDTH-1:0] data;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

10
hw/rtl/interfaces/VX_cache_dram_rsp_if.v
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@@ -8,12 +8,10 @@ interface VX_cache_dram_rsp_if #(
parameter DRAM_TAG_WIDTH = 1
) ();
wire valid;
wire [DRAM_LINE_WIDTH-1:0] data;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire [DRAM_LINE_WIDTH-1:0] data;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

12
hw/rtl/interfaces/VX_cache_snp_req_if.v
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@@ -8,13 +8,11 @@ interface VX_cache_snp_req_if #(
parameter SNP_TAG_WIDTH = 0
) ();
wire valid;
wire [DRAM_ADDR_WIDTH-1:0] addr;
wire invalidate;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
wire valid;
wire [DRAM_ADDR_WIDTH-1:0] addr;
wire invalidate;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_cache_snp_rsp_if.v
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@@ -7,10 +7,8 @@ interface VX_cache_snp_rsp_if #(
parameter SNP_TAG_WIDTH = 0
) ();
wire valid;
wire valid;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_cmt_to_csr_if.v
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@@ -5,7 +5,7 @@
interface VX_cmt_to_csr_if ();
wire valid;
wire valid;
wire [$clog2(3*`NUM_THREADS+1)-1:0] commit_size;
endinterface

2
hw/rtl/interfaces/VX_commit_if.v
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@@ -6,14 +6,12 @@
interface VX_commit_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_csr_io_req_if.v
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@@ -5,12 +5,10 @@
interface VX_csr_io_req_if ();
wire valid;
wire valid;
wire [`CSR_ADDR_BITS-1:0] addr;
wire rw;
wire [31:0] data;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_csr_io_rsp_if.v
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@@ -5,10 +5,8 @@
interface VX_csr_io_rsp_if ();
wire valid;
wire valid;
wire [31:0] data;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_csr_pipe_req_if.v
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@@ -6,7 +6,6 @@
interface VX_csr_pipe_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -15,8 +14,7 @@ interface VX_csr_pipe_req_if ();
wire [31:0] csr_mask;
wire [`NR_BITS-1:0] rd;
wire wb;
wire is_io;
wire is_io;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -6,7 +6,6 @@
interface VX_csr_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -16,8 +15,7 @@ interface VX_csr_req_if ();
wire rs2_is_imm;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rd;
wire wb;
wire wb;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_decode_if.v
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@@ -6,7 +6,6 @@
interface VX_decode_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -21,8 +20,7 @@ interface VX_decode_if ();
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire [`NUM_REGS-1:0] used_regs;
wire [`NUM_REGS-1:0] used_regs;
wire ready;
endinterface

6
hw/rtl/interfaces/VX_fpu_req_if.v
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@@ -9,8 +9,7 @@
interface VX_fpu_req_if ();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -20,8 +19,7 @@ interface VX_fpu_req_if ();
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire wb;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -5,12 +5,10 @@
interface VX_ifetch_req_if ();
wire valid;
wire valid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_ifetch_rsp_if.v
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@@ -6,12 +6,10 @@
interface VX_ifetch_rsp_if ();
wire valid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire [31:0] instr;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -6,7 +6,6 @@
interface VX_lsu_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -16,8 +15,7 @@ interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire [`NR_BITS-1:0] rd;
wire wb;
wire wb;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_mul_req_if.v
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@@ -10,7 +10,6 @@
interface VX_mul_req_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -18,8 +17,7 @@ interface VX_mul_req_if ();
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire wb;
wire ready;
endinterface