performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
--- a/hw/rtl/VX_writeback.v
+++ b/hw/rtl/VX_writeback.v
@@ -71,8 +71,7 @@ module VX_writeback #(
                        fpu_valid ? fpu_commit_if.data :                                                               
                                    0;

-    wire stall =~writeback_if.ready && writeback_if.valid;
-    always @(*) assert(writeback_if.ready); // the writeback currently has no backpressure from issue stage
+    wire stall = ~writeback_if.ready && writeback_if.valid;
    
    VX_generic_register #(
        .N(1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32)),