Simulate debug

2019-10-29 14:28:20 -04:00
parent 557c987bb0
commit 4aa04e76e6
12 changed files with 242 additions and 33 deletions
--- a/models/memory/cln28hpm/rf2_32x128_wm1/vsim/Makefile
+++ b/models/memory/cln28hpm/rf2_32x128_wm1/vsim/Makefile
@@ -0,0 +1,36 @@
+
+
+ALL:sim
+
+#TOOL INPUT
+SRC = \
+rf2_32x128_wm1_tb.v \
+../rf2_32x128_wm1.v 
+
+
+
+CMD= \
+-do "vcd file rf2_32x128_wm1_tb.vcd; \
+	 vcd add -r /rf2_32x128_wm1_tb/*; \
+	 run -all; \
+	 quit -f"
+
+
+OPT=-sv -sv12compat
+
+LIB = rf_lib
+
+# LOG=-logfile rf2_32x128_wm1_tb.log
+LOG=
+
+comp:
+	vlog $(OPT) -work $(LIB) $(SRC)
+
+
+sim: comp
+	vsim rf2_32x128_wm1_tb $(LOG) -c -lib $(LIB) $(CMD)
+
+
+
+
+