Simulate debug

models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v

@@ -47,6 +47,8 @@
 //
 //      Known Work Arounds: N/A
 //
+`define ARM_UD_MODEL
+
 `timescale 1 ns/1 ps
 `define ARM_MEM_PROP 1.000
 `define ARM_MEM_RETAIN 1.000

models/memory/cln28hpm/rf2_32x128_wm1/vsim/Makefile

@@ -0,0 +1,36 @@
+
+
+ALL:sim
+
+#TOOL INPUT
+SRC = \
+rf2_32x128_wm1_tb.v \
+../rf2_32x128_wm1.v 
+
+
+
+CMD= \
+-do "vcd file rf2_32x128_wm1_tb.vcd; \
+	 vcd add -r /rf2_32x128_wm1_tb/*; \
+	 run -all; \
+	 quit -f"
+
+
+OPT=-sv -sv12compat
+
+LIB = rf_lib
+
+# LOG=-logfile rf2_32x128_wm1_tb.log
+LOG=
+
+comp:
+	vlog $(OPT) -work $(LIB) $(SRC)
+
+
+sim: comp
+	vsim rf2_32x128_wm1_tb $(LOG) -c -lib $(LIB) $(CMD)
+
+
+
+
+

models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v

@@ -0,0 +1,89 @@
+`timescale 1ns/1ps
+
+
+module rf2_32x128_wm1_tb (
+	output [127 : 0] out_a_reg_data,
+	output reg clk,
+	output reg [4 : 0] rs1,
+	output reg [127 : 0] write_bit_mask,
+	output reg [4 : 0] rd,
+	output reg [127 : 0] write_data,
+	output reg cena,
+	output reg cenb
+);
+
+	initial begin
+		clk <= 1'b0;
+		rs1 <= 5'b0;
+		write_bit_mask <= {128{1'b1}};
+		rd <= 5'b0;
+		write_data <= 128'b0;
+		cena <= 1'b1;
+		cenb <= 1'b1;
+
+
+		
+		#100
+		cenb <= 1'b0;
+		write_bit_mask <= {{96{1'b1}}, {32{1'b0}}};
+		rd <= 5'h0a;
+		write_data <= 128'h0000_0002_0000_0002_0000_0002_0000_0002;
+		#10
+		cenb <= 1'b1;
+		write_bit_mask <= {128{1'b1}};
+		rd <= 5'b0;
+		write_data <= 128'b0;
+		
+		#100
+		cena <= 1'b0;
+		rs1 <= 5'h0a;
+
+      #1000
+      $finish;
+
+
+	end
+
+	always @(clk) #5 clk <= ~clk;
+
+
+
+   rf2_32x128_wm1 first_ram (
+         .CENYA(),
+         .AYA(),
+         .CENYB(),
+         .WENYB(),
+         .AYB(),
+         .QA(out_a_reg_data),
+         .SOA(),
+         .SOB(),
+         .CLKA(clk),
+         .CENA(cena),
+         .AA(rs1),
+         .CLKB(clk),
+         .CENB(cenb),
+         .WENB(write_bit_mask),
+         .AB(rd),
+         .DB(write_data),
+         .EMAA(3'b011),
+         .EMASA(1'b0),
+         .EMAB(3'b011),
+         .TENA(1'b1),
+         .TCENA(1'b0),
+         .TAA(5'b0),
+         .TENB(1'b1),
+         .TCENB(1'b0),
+         .TWENB(128'b0),
+         .TAB(5'b0),
+         .TDB(128'b0),
+         .RET1N(1'b1),
+         .SIA(2'b0),
+         .SEA(1'b0),
+         .DFTRAMBYP(1'b0),
+         .SIB(2'b0),
+         .SEB(1'b0),
+         .COLLDISN(1'b1)
+   );
+
+endmodule 
+

models/memory/cln28hpm/rf2_32x128_wm1/vsim/transcript

@@ -0,0 +1,26 @@
+# vsim rf2_32x128_wm1_tb -c -lib rf_lib -do "vcd file rf2_32x128_wm1_tb.vcd; vcd add -r /rf2_32x128_wm1_tb/*; run -all; quit -f" 
+# Start time: 13:02:14 on Oct 29,2019
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# //  ModelSim SE-64 10.6a Mar 16 2017Linux 3.10.0-1062.1.2.el7.x86_64
+# //
+# //  Copyright 1991-2017 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  ModelSim SE-64 and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading sv_std.std
+# Loading work.rf2_32x128_wm1_tb(fast)
+# Loading work.rf2_32x128_wm1(fast)
+# vcd file rf2_32x128_wm1_tb.vcd
+#  vcd add -r /rf2_32x128_wm1_tb/*
+#  run -all
+# ** Note: $finish    : rf2_32x128_wm1_tb.v(42)
+#    Time: 220 ns  Iteration: 0  Instance: /rf2_32x128_wm1_tb
+# End time: 13:02:16 on Oct 29,2019, Elapsed time: 0:00:02
+# Errors: 0, Warnings: 0