From 4a4498cd5305cf4af74acf021fbbd6bc713be665 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 11 Oct 2021 18:32:17 -0400 Subject: [PATCH] minor update --- sim/rtlsim/Makefile | 6 ++++-- sim/rtlsim/simulator.cpp | 3 ++- sim/simX/Makefile | 1 + sim/vlsim/Makefile | 8 +++----- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/sim/rtlsim/Makefile b/sim/rtlsim/Makefile index 61cf2408..6059e711 100644 --- a/sim/rtlsim/Makefile +++ b/sim/rtlsim/Makefile @@ -34,7 +34,7 @@ SRCS += main.cpp simulator.cpp ifdef AXI_BUS TOP = Vortex_axi - CFLAGS += -DAXI_BUS + CXXFLAGS += -DAXI_BUS else TOP = Vortex endif @@ -44,9 +44,11 @@ VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += verilator.vlt -VL_FLAGS += $(CONFIGS) VL_FLAGS += $(RTL_INCLUDE) +VL_FLAGS += $(CONFIGS) +CXXFLAGS += $(CONFIGS) + # Debugigng ifdef DEBUG VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) diff --git a/sim/rtlsim/simulator.cpp b/sim/rtlsim/simulator.cpp index cc7f1551..8d3f9acf 100644 --- a/sim/rtlsim/simulator.cpp +++ b/sim/rtlsim/simulator.cpp @@ -219,6 +219,7 @@ void Simulator::reset_axi_bus() { vl_obj_->device->m_axi_awready = 0; vl_obj_->device->m_axi_arready = 0; vl_obj_->device->m_axi_rvalid = 0; + vl_obj_->device->m_axi_bvalid = 0; } void Simulator::eval_axi_bus(bool clk) { @@ -369,7 +370,7 @@ void Simulator::eval_axi_bus(bool clk) { mem_req_t mem_req; mem_req.tag = vl_obj_->device->m_axi_arid; mem_req.addr = vl_obj_->device->m_axi_araddr; - ram_->read(vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE, mem_req.block.data()); + ram_->read(mem_req.block.data(), vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE); mem_req.cycles_left = MEM_LATENCY; mem_req.write = 0; for (auto& rsp : mem_rsp_vec_[req_bank]) { diff --git a/sim/simX/Makefile b/sim/simX/Makefile index 59281fb5..29b53fc3 100644 --- a/sim/simX/Makefile +++ b/sim/simX/Makefile @@ -4,6 +4,7 @@ CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors CXXFLAGS += -fPIC -Wno-maybe-uninitialized CXXFLAGS += -I. -I../common -I../../hw CXXFLAGS += -I../common/softfloat/source/include +CXXFLAGS += $(CONFIGS) LDFLAGS += ../common/softfloat/build/Linux-x86_64-GCC/softfloat.a diff --git a/sim/vlsim/Makefile b/sim/vlsim/Makefile index 8c7a0e20..7de01df9 100644 --- a/sim/vlsim/Makefile +++ b/sim/vlsim/Makefile @@ -25,10 +25,6 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO -CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 - -CXXFLAGS += $(CONFIGS) - SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp SRCS += fpga.cpp opae_sim.cpp @@ -44,9 +40,11 @@ VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += verilator.vlt -VL_FLAGS += $(CONFIGS) VL_FLAGS += $(RTL_INCLUDE) +VL_FLAGS += $(CONFIGS) +CXXFLAGS += $(CONFIGS) + # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #VL_FLAGS += --threads $(THREADS)