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using single-port block ram for cache tags, restoring core reset signal

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This commit is contained in:
Blaise Tine
2021-01-02 19:53:41 -08:00
parent a766c16ac9
commit 4815ab099c
9 changed files with 213 additions and 23 deletions
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10
driver/opae/vlsim/opae_sim.cpp
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@@ -8,6 +8,8 @@
#define CCI_RQ_SIZE 16 #define CCI_RQ_SIZE 16
#define CCI_WQ_SIZE 16 #define CCI_WQ_SIZE 16
#define RESET_DELAY 1
#define ENABLE_DRAM_STALLS #define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 24 #define DRAM_LATENCY 24
#define DRAM_RQ_SIZE 16 #define DRAM_RQ_SIZE 16
@@ -138,8 +140,7 @@ void opae_sim::reset() {
vortex_afu_->reset = 0; vortex_afu_->reset = 0;
// Turn on assertion after reset reset_time_ = timestamp;
Verilated::assertOn(true);
} }
void opae_sim::step() { void opae_sim::step() {
@@ -153,6 +154,11 @@ void opae_sim::step() {
vortex_afu_->clk = 1; vortex_afu_->clk = 1;
this->eval(); this->eval();
if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
// Turn on assertion after reset
Verilated::assertOn(true);
}
#ifndef NDEBUG #ifndef NDEBUG
fflush(stdout); fflush(stdout);
#endif #endif

2
driver/opae/vlsim/opae_sim.h
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@@ -85,6 +85,8 @@ private:
std::mutex mutex_; std::mutex mutex_;
uint64_t reset_time_;
RAM ram_; RAM ram_;
Vvortex_afu_shim *vortex_afu_; Vvortex_afu_shim *vortex_afu_;
#ifdef VCD_OUTPUT #ifdef VCD_OUTPUT

8
hw/rtl/VX_cluster.v
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@@ -68,13 +68,19 @@ module VX_cluster #(
wire [`NUM_CORES-1:0] per_core_ebreak; wire [`NUM_CORES-1:0] per_core_ebreak;
for (genvar i = 0; i < `NUM_CORES; i++) begin for (genvar i = 0; i < `NUM_CORES; i++) begin
reg core_reset;
always @(posedge clk) begin
core_reset <= reset;
end
VX_core #( VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) .CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) core ( ) core (
`SCOPE_BIND_VX_cluster_core(i) `SCOPE_BIND_VX_cluster_core(i)
.clk (clk), .clk (clk),
.reset (reset), .reset (core_reset),
.dram_req_valid (per_core_dram_req_valid[i]), .dram_req_valid (per_core_dram_req_valid[i]),
.dram_req_rw (per_core_dram_req_rw [i]), .dram_req_rw (per_core_dram_req_rw [i]),

5
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -132,8 +132,9 @@ module VX_miss_resrv #(
VX_dp_ram #( VX_dp_ram #(
.DATAW(`MSHR_DATA_WIDTH), .DATAW(`MSHR_DATA_WIDTH),
.SIZE(MSHR_SIZE), .SIZE(MSHR_SIZE),
.RWCHECK(1) .RWCHECK(1),
) datatable ( .FASTRAM(1)
) entries (
.clk(clk), .clk(clk),
.waddr(tail_ptr), .waddr(tail_ptr),
.raddr(schedule_ptr), .raddr(schedule_ptr),

4
hw/rtl/cache/VX_tag_access.v vendored
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@@ -65,7 +65,8 @@ module VX_tag_access #(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.read_addr (addrline), .addr (addrline),
.read_valid (read_valid), .read_valid (read_valid),
.read_dirty (read_dirty), .read_dirty (read_dirty),
.read_tag (read_tag), .read_tag (read_tag),
@@ -73,7 +74,6 @@ module VX_tag_access #(
.do_fill (do_fill), .do_fill (do_fill),
.do_write (do_write), .do_write (do_write),
.invalidate (do_invalidate), .invalidate (do_invalidate),
.write_addr (addrline),
.write_tag (addrtag) .write_tag (addrtag)
); );

22
hw/rtl/cache/VX_tag_store.v vendored
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@@ -15,13 +15,13 @@ module VX_tag_store #(
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire[`LINE_SELECT_BITS-1:0] addr,
input wire do_fill, input wire do_fill,
input wire do_write, input wire do_write,
input wire invalidate, input wire invalidate,
input wire[`LINE_SELECT_BITS-1:0] write_addr,
input wire[`TAG_SELECT_BITS-1:0] write_tag, input wire[`TAG_SELECT_BITS-1:0] write_tag,
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire[`TAG_SELECT_BITS-1:0] read_tag, output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire read_valid, output wire read_valid,
output wire read_dirty output wire read_dirty
@@ -37,25 +37,23 @@ module VX_tag_store #(
end end
end else begin end else begin
if (do_fill) begin if (do_fill) begin
valid[write_addr] <= 1; valid[addr] <= 1;
dirty[write_addr] <= 0; dirty[addr] <= 0;
end else if (do_write) begin end else if (do_write) begin
dirty[write_addr] <= 1; dirty[addr] <= 1;
end else if (invalidate) begin end else if (invalidate) begin
valid[write_addr] <= 0; valid[addr] <= 0;
end end
end end
end end
VX_dp_ram #( VX_sp_ram #(
.DATAW(`TAG_SELECT_BITS), .DATAW(`TAG_SELECT_BITS),
.SIZE(`LINES_PER_BANK), .SIZE(`LINES_PER_BANK),
.FASTRAM(1),
.RWCHECK(1) .RWCHECK(1)
) tags ( ) tags (
.clk(clk), .clk(clk),
.waddr(write_addr), .addr(addr),
.raddr(read_addr),
.wren(do_fill), .wren(do_fill),
.byteen(1'b1), .byteen(1'b1),
.rden(1'b1), .rden(1'b1),
@@ -63,7 +61,7 @@ module VX_tag_store #(
.dout(read_tag) .dout(read_tag)
); );
assign read_valid = valid[read_addr]; assign read_valid = valid[addr];
assign read_dirty = dirty[read_addr]; assign read_dirty = dirty[addr];
endmodule endmodule

169
hw/rtl/libs/VX_sp_ram.v Normal file
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@@ -0,0 +1,169 @@
`include "VX_platform.vh"
`TRACING_OFF
module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter FASTRAM = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
localparam DATA32W = DATAW / 32;
localparam BYTEEN32W = BYTEENW / 4;
if (FASTRAM) begin
if (BUFFERED) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
if (rden)
dout_r <= mem[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
if (rden)
dout_r <= mem[addr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[addr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
end
assign dout = mem[addr];
end
end
end else begin
if (BUFFERED) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
if (rden)
dout_r <= mem[addr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
if (rden)
dout_r <= mem[addr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
if (BYTEENW > 1) begin
reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[addr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
end
assign dout = mem[addr];
end
end else begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren) begin
for (integer j = 0; j < BYTEEN32W; j++) begin
for (integer i = 0; i < 4; i++) begin
if (byteen[j * 4 + i])
mem[addr][j][i] <= din[j * 32 + i * 8 +: 8];
end
end
end
end
assign dout = mem[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
always @(posedge clk) begin
if (wren && byteen)
mem[addr] <= din;
end
assign dout = mem[addr];
end
end
end
end
endmodule
`TRACING_ON

10
hw/simulate/simulator.cpp
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@@ -3,6 +3,8 @@
#include <fstream> #include <fstream>
#include <iomanip> #include <iomanip>
#define RESET_DELAY 1
#define ENABLE_DRAM_STALLS #define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 24 #define DRAM_LATENCY 24
#define DRAM_RQ_SIZE 16 #define DRAM_RQ_SIZE 16
@@ -81,8 +83,7 @@ void Simulator::reset() {
vortex_->reset = 0; vortex_->reset = 0;
// Turn on assertion after reset reset_time_ = timestamp;
Verilated::assertOn(true);
} }
void Simulator::step() { void Simulator::step() {
@@ -100,6 +101,11 @@ void Simulator::step() {
this->eval_io_bus(); this->eval_io_bus();
this->eval_csr_bus(); this->eval_csr_bus();
if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
// Turn on assertion after reset
Verilated::assertOn(true);
}
#ifndef NDEBUG #ifndef NDEBUG
fflush(stdout); fflush(stdout);
#endif #endif

2
hw/simulate/simulator.h
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@@ -69,6 +69,8 @@ private:
bool csr_req_active_; bool csr_req_active_;
uint32_t* csr_rsp_value_; uint32_t* csr_rsp_value_;
uint64_t reset_time_;
RAM *ram_; RAM *ram_;
VVortex *vortex_; VVortex *vortex_;
#ifdef VCD_OUTPUT #ifdef VCD_OUTPUT