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minor update

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This commit is contained in:
Blaise Tine
2021-06-13 10:58:48 -07:00
parent a315d0087d
commit 47c3234659
11 changed files with 39 additions and 109 deletions
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25
hw/rtl/VX_mem_unit.v
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@@ -256,26 +256,19 @@ module VX_mem_unit # (
);
end else begin
// core to D-cache request
for (genvar i = 0; i < `DNUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (`DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH)
) core_req_buf (
.clk (clk),
.reset (reset),
.valid_in (dcache_core_req_if.valid[i]),
.data_in ({dcache_core_req_if.addr[i], dcache_core_req_if.rw[i], dcache_core_req_if.byteen[i], dcache_core_req_if.data[i], dcache_core_req_if.tag[i]}),
.ready_in (dcache_core_req_if.ready[i]),
.valid_out (dcache_req_if.valid[i]),
.data_out ({dcache_req_if.addr[i], dcache_req_if.rw[i], dcache_req_if.byteen[i], dcache_req_if.data[i], dcache_req_if.tag[i]}),
.ready_out (dcache_req_if.ready[i])
);
end
assign dcache_req_if.valid = dcache_core_req_if.valid;
assign dcache_req_if.addr = dcache_core_req_if.addr;
assign dcache_req_if.rw = dcache_core_req_if.rw;
assign dcache_req_if.byteen = dcache_core_req_if.byteen;
assign dcache_req_if.data = dcache_core_req_if.data;
assign dcache_req_if.tag = dcache_core_req_if.tag;
assign dcache_core_req_if.ready = dcache_req_if.ready;
// D-cache to core reponse
assign dcache_core_rsp_if.valid = dcache_rsp_if.valid;
assign dcache_core_rsp_if.tag = dcache_rsp_if.tag;
assign dcache_core_rsp_if.data = dcache_rsp_if.data;
assign dcache_rsp_if.ready = dcache_core_rsp_if.ready;
assign dcache_rsp_if.ready = dcache_core_rsp_if.ready;
end
wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag);
@@ -289,7 +282,7 @@ module VX_mem_unit # (
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
.BUFFERED_REQ (1),
.BUFFERED_RSP (0)
.BUFFERED_RSP (1)
) mem_arb (
.clk (clk),
.reset (reset),