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MULTICORE WITH L2 WORKING

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This commit is contained in:
felsabbagh3
2020-03-09 01:17:11 -07:00
parent 24f20a2da4
commit 469334f23e
28 changed files with 642 additions and 557 deletions
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96
rtl/simulate/multi_test_bench.h
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@@ -78,7 +78,6 @@ class Vortex
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
std::vector<dram_req_t> I_dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
@@ -165,84 +164,6 @@ void Vortex::print_stats(bool cycle_test)
bool Vortex::ibus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->I_dram_req_vec.size(); i++)
{
if (this->I_dram_req_vec[i].cycles_left > 0)
{
this->I_dram_req_vec[i].cycles_left -= 1;
}
if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->I_dram_req)
{
// std::cout << "Icache Dram Request received!\n";
if (vortex->I_dram_req_read)
{
// std::cout << "Icache Dram Request is read!\n";
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->I_dram_expected_lat;
dram_req.data_length = vortex->I_dram_req_size / 4;
dram_req.base_addr = vortex->I_dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram.getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->I_dram_req_vec.push_back(dram_req);
}
if (vortex->I_dram_req_write)
{
unsigned base_addr = vortex->I_dram_req_addr;
unsigned data_length = vortex->I_dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->I_dram_req_data[i];
ram.writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->I_dram_fill_accept && dequeue_valid)
{
// std::cout << "Icache Dram Response Sending...!\n";
vortex->I_dram_fill_rsp = 1;
vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++)
{
vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i];
}
free(this->I_dram_req_vec[dequeue_index].data);
this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->I_dram_fill_rsp = 0;
vortex->I_dram_fill_rsp_addr = 0;
}
return false;
@@ -251,15 +172,18 @@ bool Vortex::ibus_driver()
void Vortex::io_handler()
{
// std::cout << "Checking\n";
if (vortex->io_valid)
for (int c = 0; c < vortex->number_cores; c++)
{
uint32_t data_write = (uint32_t) vortex->io_data;
// std::cout << "IO VALID!\n";
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
if (vortex->io_valid[c])
{
uint32_t data_write = (uint32_t) vortex->io_data[c];
// std::cout << "IO VALID!\n";
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
std::cout << std::flush;
}
}
}