timimg fixes

hw/rtl/tex_unit/VX_tex_lerp.v

@@ -7,29 +7,11 @@ module VX_tex_lerp #(
     input wire  [31:0] in2,
     output wire [31:0] out
 );  
-    wire [63:0] in1_w, in2_w;
-    wire [63:0] lerp1, lerp2;
-
-    `UNUSED_VAR (lerp1)
-    `UNUSED_VAR (lerp2)
-
-    assign in1_w[15:00] = {8'h00, in1[07:00]};
-    assign in1_w[31:16] = {8'h00, in1[15:08]};
-    assign in1_w[47:32] = {8'h00, in1[23:16]};
-    assign in1_w[63:48] = {8'h00, in1[31:24]};
-
-    assign in2_w[15:00] = {8'h00, in2[07:00]};
-    assign in2_w[31:16] = {8'h00, in2[15:08]};
-    assign in2_w[47:32] = {8'h00, in2[23:16]};
-    assign in2_w[63:48] = {8'h00, in2[31:24]};
-
-    assign lerp1 = (in2_w - in1_w) * blend;
-    
-    assign lerp2 = in1_w + {8'h00,lerp1[63:56], 8'h00,lerp1[47:40], 8'h00,lerp1[31:24], 8'h00,lerp1[15:8]};
-    
-    assign out[07:00] = lerp2[07:00];
-    assign out[15:08] = lerp2[23:16];
-    assign out[23:16] = lerp2[39:32];
-    assign out[31:24] = lerp2[55:48];
+    for (genvar i = 0; i < 4; ++i) begin
+        wire [8:0]  m1 = (8'hff - blend);
+        wire [16:0] sum = in1[i*8+:8] * blend + in2[i*8+:8] * m1;
+        `UNUSED_VAR (sum)
+        assign out[i*8+:8] = sum[15:8];
+    end
 
 endmodule