minor updates
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7
hw/rtl/cache/VX_bank.v
vendored
7
hw/rtl/cache/VX_bank.v
vendored
@@ -237,13 +237,12 @@ module VX_bank #(
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wire is_mshr_miss_st1 = valid_st1 && is_mshr_st1 && (miss_st1 || force_miss_st1);
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// determine which queue to pop next in piority order
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wire mshr_pop_unqual = mshr_valid;
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// determine which queue to pop next in piority order
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wire mshr_pop_unqual = mshr_valid && !is_mshr_miss_st1;
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wire drsq_pop_unqual = !mshr_pop_unqual && !drsq_empty;
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wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !mshr_almost_full && !dreq_almost_full;
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assign mshr_pop = mshr_pop_unqual && !pipeline_stall
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&& !is_mshr_miss_st1; // stop if previous request was a miss
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assign mshr_pop = mshr_pop_unqual && !pipeline_stall;
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assign drsq_pop = drsq_pop_unqual && !pipeline_stall;
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assign creq_pop = creq_pop_unqual && !pipeline_stall;
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