vlsim fix, verilator fst trace, use ram optimization

2020-10-25 16:40:50 -07:00
parent 81dc8c7279
commit 43ae82e788
23 changed files with 424 additions and 422 deletions
--- a/hw/rtl/libs/VX_generic_queue.v
+++ b/hw/rtl/libs/VX_generic_queue.v
@@ -85,7 +85,7 @@ module VX_generic_queue #(
                .DATAW(DATAW),
                .SIZE(SIZE),
                .BUFFERED(0),
-                .RWCHECK(0)
+                .RWCHECK(1)
            ) dp_ram (
                .clk(clk),	
                .waddr(wr_ptr_a),