vlsim fix, verilator fst trace, use ram optimization

This commit is contained in:
Blaise Tine
2020-10-25 16:40:50 -07:00
parent 81dc8c7279
commit 43ae82e788
23 changed files with 424 additions and 422 deletions

View File

@@ -1,6 +1,6 @@
#pragma once
//#define HANG_TIMEOUT 60
#define HANG_TIMEOUT 60
int vx_scope_start(fpga_handle hfpga, uint64_t delay = -1);