fixed lmp_mult parameters, ram init filepath

2020-09-04 07:51:46 -07:00
parent dccea80b68
commit 42e3b6c45d
36 changed files with 738 additions and 495 deletions
--- a/hw/rtl/fp_cores/altera/acl_fp_div.sv
+++ b/hw/rtl/fp_cores/altera/acl_fp_div.sv
@@ -15,12 +15,12 @@
 // applicable agreement for further details.
 // ---------------------------------------------------------------------------

-// SystemVerilog created from acl_fp_div
-// SystemVerilog created on Mon Aug 31 06:15:17 2020
+// SystemVerilog created from acl_fdiv
+// SystemVerilog created on Wed Sep  2 07:11:09 2020


 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
-module acl_fp_div (
+module acl_fdiv (
    input wire [31:0] a,
    input wire [31:0] b,
    input wire [0:0] en,
@@ -623,7 +623,7 @@ module acl_fp_div (
        .outdata_aclr_a("CLEAR0"),
        .clock_enable_input_a("NORMAL"),
        .power_up_uninitialized("FALSE"),
-        .init_file("acl_fp_div_memoryC2_uid118_invTables_lutmem.hex"),
+        .init_file("acl_fdiv_memoryC2_uid118_invTables_lutmem.hex"),
        .init_file_layout("PORT_A"),
        .intended_device_family("Arria 10")
    ) memoryC2_uid118_invTables_lutmem_dmem (
@@ -755,7 +755,7 @@ module acl_fp_div (
        .outdata_aclr_a("CLEAR0"),
        .clock_enable_input_a("NORMAL"),
        .power_up_uninitialized("FALSE"),
-        .init_file("acl_fp_div_memoryC1_uid115_invTables_lutmem.hex"),
+        .init_file("acl_fdiv_memoryC1_uid115_invTables_lutmem.hex"),
        .init_file_layout("PORT_A"),
        .intended_device_family("Arria 10")
    ) memoryC1_uid115_invTables_lutmem_dmem (
@@ -1060,7 +1060,7 @@ module acl_fp_div (
        .outdata_aclr_a("CLEAR0"),
        .clock_enable_input_a("NORMAL"),
        .power_up_uninitialized("FALSE"),
-        .init_file("acl_fp_div_memoryC0_uid112_invTables_lutmem.hex"),
+        .init_file("acl_fdiv_memoryC0_uid112_invTables_lutmem.hex"),
        .init_file_layout("PORT_A"),
        .intended_device_family("Arria 10")
    ) memoryC0_uid112_invTables_lutmem_dmem (
--- a/hw/rtl/fp_cores/altera/acl_fp_div_memoryC0_uid112_invTables_lutmem.hex
+++ b/hw/rtl/fp_cores/altera/acl_fp_div_memoryC0_uid112_invTables_lutmem.hex
--- a/hw/rtl/fp_cores/altera/acl_fp_div_memoryC1_uid115_invTables_lutmem.hex
+++ b/hw/rtl/fp_cores/altera/acl_fp_div_memoryC1_uid115_invTables_lutmem.hex
--- a/hw/rtl/fp_cores/altera/acl_fp_div_memoryC2_uid118_invTables_lutmem.hex
+++ b/hw/rtl/fp_cores/altera/acl_fp_div_memoryC2_uid118_invTables_lutmem.hex
--- a/hw/rtl/fp_cores/altera/acl_fp_sqrt.sv
+++ b/hw/rtl/fp_cores/altera/acl_fp_sqrt.sv
@@ -15,12 +15,12 @@
 // applicable agreement for further details.
 // ---------------------------------------------------------------------------

-// SystemVerilog created from acl_fp_sqrt
-// SystemVerilog created on Mon Aug 31 06:15:18 2020
+// SystemVerilog created from acl_fsqrt
+// SystemVerilog created on Wed Sep  2 07:11:09 2020


 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
-module acl_fp_sqrt (
+module acl_fsqrt (
    input wire [31:0] a,
    input wire [0:0] en,
    output wire [31:0] q,
@@ -279,7 +279,7 @@ module acl_fp_sqrt (
        .outdata_aclr_a("CLEAR0"),
        .clock_enable_input_a("NORMAL"),
        .power_up_uninitialized("FALSE"),
-        .init_file("acl_fp_sqrt_memoryC2_uid68_sqrtTables_lutmem.hex"),
+        .init_file("acl_fsqrt_memoryC2_uid68_sqrtTables_lutmem.hex"),
        .init_file_layout("PORT_A"),
        .intended_device_family("Arria 10")
    ) memoryC2_uid68_sqrtTables_lutmem_dmem (
@@ -412,7 +412,7 @@ module acl_fp_sqrt (
        .outdata_aclr_a("CLEAR0"),
        .clock_enable_input_a("NORMAL"),
        .power_up_uninitialized("FALSE"),
-        .init_file("acl_fp_sqrt_memoryC1_uid65_sqrtTables_lutmem.hex"),
+        .init_file("acl_fsqrt_memoryC1_uid65_sqrtTables_lutmem.hex"),
        .init_file_layout("PORT_A"),
        .intended_device_family("Arria 10")
    ) memoryC1_uid65_sqrtTables_lutmem_dmem (
@@ -723,7 +723,7 @@ module acl_fp_sqrt (
        .outdata_aclr_a("CLEAR0"),
        .clock_enable_input_a("NORMAL"),
        .power_up_uninitialized("FALSE"),
-        .init_file("acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex"),
+        .init_file("acl_fsqrt_memoryC0_uid62_sqrtTables_lutmem.hex"),
        .init_file_layout("PORT_A"),
        .intended_device_family("Arria 10")
    ) memoryC0_uid62_sqrtTables_lutmem_dmem (
--- a/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex
+++ b/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex
--- a/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC1_uid65_sqrtTables_lutmem.hex
+++ b/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC1_uid65_sqrtTables_lutmem.hex
--- a/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC2_uid68_sqrtTables_lutmem.hex
+++ b/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC2_uid68_sqrtTables_lutmem.hex
--- a/hw/rtl/fp_cores/altera/acl_fp_ftoi.sv
+++ b/hw/rtl/fp_cores/altera/acl_fp_ftoi.sv
@@ -15,12 +15,12 @@
 // applicable agreement for further details.
 // ---------------------------------------------------------------------------

-// SystemVerilog created from acl_fp_ftoi
-// SystemVerilog created on Mon Aug 31 06:15:18 2020
+// SystemVerilog created from acl_ftoi
+// SystemVerilog created on Wed Sep  2 07:11:09 2020


 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
-module acl_fp_ftoi (
+module acl_ftoi (
    input wire [31:0] a,
    input wire [0:0] en,
    output wire [31:0] q,
--- a/hw/rtl/fp_cores/altera/acl_fp_ftou.sv
+++ b/hw/rtl/fp_cores/altera/acl_fp_ftou.sv
@@ -15,12 +15,12 @@
 // applicable agreement for further details.
 // ---------------------------------------------------------------------------

-// SystemVerilog created from acl_fp_ftou
-// SystemVerilog created on Mon Aug 31 06:15:18 2020
+// SystemVerilog created from acl_ftou
+// SystemVerilog created on Wed Sep  2 07:11:09 2020


 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
-module acl_fp_ftou (
+module acl_ftou (
    input wire [31:0] a,
    input wire [0:0] en,
    output wire [31:0] q,
--- a/hw/rtl/fp_cores/altera/acl_gen.log
+++ b/hw/rtl/fp_cores/altera/acl_gen.log
@@ -0,0 +1,169 @@
+starting execution ... 
+build model options ... 
+argc=21
+Generation context:
+    HardFP is enabled enabling set to true 
+    Faithful rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fdiv
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3 
+The pipeline depth of the block is 15 cycle(s)
+@@start
+@name FPDiv@
+@latency 15@
+@LUT 539@
+@DSP 5@
+@RAMBits 32768@
+@RAMBlockUsage 3@
+@enable 1@
+@subnormals 0@
+@error 1.00@
+@rounding NA@
+@method polynomial approximation@
+@inPort 0 fpieee 8 23@
+@inPort 1 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=20
+Generation context:
+    HardFP is enabled enabling set to true 
+    Faithful rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_fsqrt
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3 
+The pipeline depth of the block is 10 cycle(s)
+@@start
+@name FPSqrt@
+@latency 10@
+@LUT 271@
+@DSP 3@
+@RAMBits 15872@
+@RAMBlockUsage 3@
+@enable 1@
+@subnormals 0@
+@error 1.00@
+@rounding NA@
+@method polynomial approximation@
+@inPort 0 fpieee 8 23@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=23
+Generation context:
+    HardFP is enabled enabling set to true 
+    Faithful rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_ftoi
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPToFXP@
+@latency 3@
+@LUT 327@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 1.00@
+@rounding NA@
+@method default@
+@inPort 0 fpieee 8 23@
+@outPort 0 fxp 32 0 1@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=23
+Generation context:
+    HardFP is enabled enabling set to true 
+    Faithful rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_ftou
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 3 cycle(s)
+@@start
+@name FPToFXP@
+@latency 3@
+@LUT 287@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 1.00@
+@rounding NA@
+@method default@
+@inPort 0 fpieee 8 23@
+@outPort 0 fxp 32 0 0@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=23
+Generation context:
+    HardFP is enabled enabling set to true 
+    Faithful rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_itof
+    Frequency 250MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 7 cycle(s)
+@@start
+@name FXPToFP@
+@latency 7@
+@LUT 397@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 1.00@
+@rounding NA@
+@method default@
+@inPort 0 fxp 32 0 1@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
+starting execution ... 
+build model options ... 
+argc=23
+Generation context:
+    HardFP is enabled enabling set to true 
+    Faithful rounding constraint detected 
+        Will not generate valid and channel signals 
+    The new component name is acl_utof
+    Frequency 300MHz 
+    Deployment FPGA Arria10 
+Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0 
+The pipeline depth of the block is 7 cycle(s)
+@@start
+@name FXPToFP@
+@latency 7@
+@LUT 363@
+@DSP 0@
+@RAMBits 0@
+@RAMBlockUsage 0@
+@enable 1@
+@subnormals 0@
+@error 1.00@
+@rounding NA@
+@method default@
+@inPort 0 fxp 32 0 0@
+@outPort 0 fpieee 8 23@
+@nochanvalid 1@
+@@end
--- a/hw/rtl/fp_cores/altera/acl_gen.sh
+++ b/hw/rtl/fp_cores/altera/acl_gen.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+
+CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
+
+OPTIONS="-target Arria10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding  -noChanValid -enable -speedgrade 2"
+
+export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
+
+CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
+
+EXP_BITS=8
+MAN_BITS=23
+FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
+
+echo Generating IP cores for $FBITS
+{
+    $CMD -name acl_fdiv  -frequency 250 FPDiv   $EXP_BITS $MAN_BITS 0
+    $CMD -name acl_fsqrt -frequency 250 FPSqrt  $EXP_BITS $MAN_BITS
+    $CMD -name acl_ftoi  -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
+    $CMD -name acl_ftou  -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
+    $CMD -name acl_itof  -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
+    $CMD -name acl_utof  -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
+} > acl_gen.log 2>&1
+
+#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
--- a/hw/rtl/fp_cores/altera/acl_fp_itof.sv
+++ b/hw/rtl/fp_cores/altera/acl_fp_itof.sv
@@ -15,12 +15,12 @@
 // applicable agreement for further details.
 // ---------------------------------------------------------------------------

-// SystemVerilog created from acl_fp_itof
-// SystemVerilog created on Mon Aug 31 06:15:18 2020
+// SystemVerilog created from acl_itof
+// SystemVerilog created on Wed Sep  2 07:11:09 2020


 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
-module acl_fp_itof (
+module acl_itof (
    input wire [31:0] a,
    input wire [0:0] en,
    output wire [31:0] q,
--- a/hw/rtl/fp_cores/altera/acl_fp_utof.sv
+++ b/hw/rtl/fp_cores/altera/acl_fp_utof.sv
@@ -15,12 +15,12 @@
 // applicable agreement for further details.
 // ---------------------------------------------------------------------------

-// SystemVerilog created from acl_fp_utof
-// SystemVerilog created on Mon Aug 31 06:15:18 2020
+// SystemVerilog created from acl_utof
+// SystemVerilog created on Wed Sep  2 07:11:09 2020


 (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
-module acl_fp_utof (
+module acl_utof (
    input wire [31:0] a,
    input wire [0:0] en,
    output wire [31:0] q,
--- a/hw/rtl/fp_cores/altera/generate.sh
+++ b/hw/rtl/fp_cores/altera/generate.sh
@@ -1,25 +0,0 @@
-#!/bin/bash
-
-CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
-
-OPTIONS="-target Arria10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding  -noChanValid -enable -speedgrade 2"
-
-export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
-
-CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS"
-
-EXP_BITS=8
-MAN_BITS=23
-FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
-
-echo Generating IP cores for $FBITS
-{
-    $CMD -name acl_fp_div  -frequency 250 FPDiv  $EXP_BITS $MAN_BITS 0
-    $CMD -name acl_fp_sqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
-    $CMD -name acl_fp_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
-    $CMD -name acl_fp_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
-    $CMD -name acl_fp_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
-    $CMD -name acl_fp_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
-} > log.txt 2>&1
-
-cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .