cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
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@@ -22,6 +22,7 @@ module VX_fpu_unit #(
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wire valid_out;
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wire ready_out;
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wire [63:0] rsp_uuid;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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@@ -39,7 +40,7 @@ module VX_fpu_unit #(
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wire fpuq_pop = valid_out && ready_out;
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VX_index_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1),
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.DATAW (64 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1),
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.SIZE (`FPUQ_SIZE)
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) req_metadata (
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.clk (clk),
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@@ -48,8 +49,8 @@ module VX_fpu_unit #(
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.write_addr (tag_in),
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.read_addr (tag_out),
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.release_addr (tag_out),
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.write_data ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}),
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.read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}),
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.write_data ({fpu_req_if.uuid, fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}),
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.read_data ({rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}),
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.release_slot (fpuq_pop),
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.full (fpuq_full),
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`UNUSED_PIN (empty)
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@@ -180,14 +181,14 @@ module VX_fpu_unit #(
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wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFLAGS_BITS),
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.DATAW (1 + 64 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFLAGS_BITS),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_out),
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.data_in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, rsp_fflags}),
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.data_out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, has_fflags_r, fflags_r})
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.data_in ({valid_out, rsp_uuid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, rsp_fflags}),
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.data_out ({fpu_commit_if.valid, fpu_commit_if.uuid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, has_fflags_r, fflags_r})
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);
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assign fpu_commit_if.eop = 1'b1;
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