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non-cacheable memory address fixes

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Blaise Tine
2021-06-06 20:54:36 -07:00
parent ba4f705807
commit 41069ba188
7 changed files with 207 additions and 192 deletions
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10
hw/rtl/cache/VX_cache.v vendored
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@@ -243,7 +243,7 @@ module VX_cache #(
assign mem_rsp_ready_out = !mrsq_full;
// trim out shared memory and non-cacheable flags
assign mem_rsp_tag_out_a = mem_rsp_tag_out[2 +: `MEM_ADDR_WIDTH];
assign mem_rsp_tag_out_a = mem_rsp_tag_out[NC_ENABLE +: `MEM_ADDR_WIDTH];
VX_fifo_queue #(
.DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH),
@@ -534,8 +534,12 @@ module VX_cache #(
.ready_out (mem_req_ready_in)
);
// build memory tag adding shared memory and non-cacheable flags
assign mem_req_tag_in = MEM_TAG_WIDTH'({mem_req_addr_in, 1'b0, 1'b0});
// build memory tag adding non-cacheable flag
if (NC_ENABLE) begin
assign mem_req_tag_in = MEM_TAG_WIDTH'({mem_req_addr_in, 1'b0});
end else begin
assign mem_req_tag_in = MEM_TAG_WIDTH'(mem_req_addr_in);
end
`ifdef PERF_ENABLE
// per cycle: core_reads, core_writes