miss output vector added to cache.v and bank.v

hw/rtl/cache/VX_bank.v

@@ -98,7 +98,10 @@ module VX_bank #(
 
     output wire                                   snp_rsp_valid,
     output wire [SNP_REQ_TAG_WIDTH-1:0]           snp_rsp_tag,
-    input  wire                                   snp_rsp_ready
+    input  wire                                   snp_rsp_ready,
+
+    //Misses
+    output wire misses
 );
 
 `ifdef DBG_CORE_REQ_INFO
@@ -444,6 +447,9 @@ module VX_bank #(
         .mrvq_init_ready_state_st1(mrvq_init_ready_state_st1)
     );
 
+    assign misses = miss_st1; 
+
+
 `ifdef DBG_CORE_REQ_INFO
     if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
         assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = inst_meta_st1;