minor update

hw/syn/opae/README

@@ -98,11 +98,11 @@ make -C unittest clean && make -C unittest > unittest/build.log 2>&1 &
 make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 &
 make -C cache clean && make -C cache > cache/build.log 2>&1 &
 make -C core clean && make -C core > core/build.log 2>&1 &
-make -C core8 clean && make -C core8 > core8/build.log 2>&1 &
 make -C vortex clean && make -C vortex > vortex/build.log 2>&1 &
-make -C top clean && make -C top > top/build.log 2>&1 &
 make -C top1 clean && make -C top1 > top1/build.log 2>&1 &
 make -C top2 clean && make -C top2 > top2/build.log 2>&1 &
+make -C top4 clean && make -C top4 > top4/build.log 2>&1 &
 make -C top8 clean && make -C top8 > top8/build.log 2>&1 &
 make -C top16 clean && make -C top16 > top16/build.log 2>&1 &
 make -C top32 clean && make -C top32 > top32/build.log 2>&1 &
+make -C top64 clean && make -C top64 > top64/build.log 2>&1 &

hw/syn/quartus/.gitignore

@@ -4,9 +4,6 @@
 /cache/*
 !/cache/Makefile
 
-/top/*
-!/top/Makefile
-
 /vortex/*
 !/vortex/Makefile
 
@@ -22,6 +19,9 @@
 /top2/*
 !/top2/Makefile
 
+/top4/*
+!/top4/Makefile
+
 /top8/*
 !/top8/Makefile
 

hw/syn/quartus/top1/Makefile

@@ -17,7 +17,7 @@ RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1
+SYN_ARGS = --parallel --read_settings_files=on
 FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
 ASM_ARGS =
 STA_ARGS = --parallel --do_report_timing

hw/syn/quartus/top16/Makefile

@@ -17,7 +17,7 @@ RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1
+SYN_ARGS = --parallel --read_settings_files=on
 FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
 ASM_ARGS =
 STA_ARGS = --parallel --do_report_timing

hw/syn/quartus/top2/Makefile

@@ -17,7 +17,7 @@ RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1
+SYN_ARGS = --parallel --read_settings_files=on
 FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
 ASM_ARGS =
 STA_ARGS = --parallel --do_report_timing

hw/syn/quartus/top32/Makefile

@@ -17,7 +17,7 @@ RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1
+SYN_ARGS = --parallel --read_settings_files=on
 FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
 ASM_ARGS =
 STA_ARGS = --parallel --do_report_timing
@@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES)
 
 # Project initialization
 $(PROJECT_FILES):
-	quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=4"
+	quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=8"
 	
 syn.chg:
 	$(STAMP) syn.chg

hw/syn/quartus/top64/Makefile

@@ -0,0 +1,79 @@
+#FAMILY = "Arria 10"
+#DEVICE = 10AX115N3F40E2SG
+#FPU_CORE_PATH=../../../rtl/fp_cores/altera/arria10
+
+FAMILY = "Stratix 10"
+DEVICE = 1SX280HN2F43E2VG
+FPU_CORE_PATH=../../../rtl/fp_cores/altera/stratix10
+
+PROJECT = vortex_afu
+TOP_LEVEL_ENTITY = vortex_afu
+SRC_FILE = vortex_afu.sv
+
+RTL_DIR=../../../rtl
+FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
+RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;../../../rtl/afu;../../../rtl/afu/ccip;$(FPU_INCLUDE)
+
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --parallel --do_report_timing
+
+# Build targets
+all: $(PROJECT).sta.rpt
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
+	quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8" -set "NUM_CLUSTERS=8"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
+	
+clean:
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/top8/Makefile

@@ -17,7 +17,7 @@ RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;
 PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
 
 # Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on --set=VERILOG_MACRO=NOPAE=1
+SYN_ARGS = --parallel --read_settings_files=on
 FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
 ASM_ARGS =
 STA_ARGS = --parallel --do_report_timing
@@ -58,7 +58,7 @@ smart.log: $(PROJECT_FILES)
 
 # Project initialization
 $(PROJECT_FILES):
-	quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=8"
+	quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../project.sdc -inc "$(RTL_INCLUDE)" -set "NOPAE" -set "NUM_CORES=4" -set "NUM_CLUSTERS=2"
 	
 syn.chg:
 	$(STAMP) syn.chg