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block ram read enable fix

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This commit is contained in:
Blaise Tine
2021-09-14 01:45:01 -07:00
parent 6652e2f0e9
commit 3d7baf1640
13 changed files with 32 additions and 64 deletions
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26
hw/rtl/libs/VX_dp_ram.v
View File

@@ -5,10 +5,10 @@ module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUT_REG = 0,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter ADDRW = $clog2(SIZE),
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
@@ -17,7 +17,6 @@ module VX_dp_ram #(
input wire [BYTEENW-1:0] wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire rden,
input wire [ADDRW-1:0] raddr,
output wire [DATAW-1:0] rdata
);
@@ -47,8 +46,7 @@ module VX_dp_ram #(
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
@@ -58,13 +56,11 @@ module VX_dp_ram #(
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -103,8 +99,7 @@ module VX_dp_ram #(
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -114,13 +109,11 @@ module VX_dp_ram #(
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -185,8 +178,7 @@ module VX_dp_ram #(
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -196,13 +188,11 @@ module VX_dp_ram #(
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;

6
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -2,10 +2,10 @@
`TRACING_OFF
module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUT_REG = 0,
parameter LUTRAM = 0
parameter LUTRAM = 0
) (
input wire clk,
input wire reset,

18
hw/rtl/libs/VX_fifo_queue.v
View File

@@ -2,14 +2,14 @@
`TRACING_OFF
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUT_REG = 0,
parameter LUTRAM = 1
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUT_REG = 0,
parameter LUTRAM = 1
) (
input wire clk,
input wire reset,
@@ -163,7 +163,6 @@ module VX_fifo_queue #(
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_r),
.rdata (data_out)
);
@@ -206,7 +205,6 @@ module VX_fifo_queue #(
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_n_r),
.rdata (dout)
);

1
hw/rtl/libs/VX_index_buffer.v
View File

@@ -76,7 +76,6 @@ module VX_index_buffer #(
.wren (acquire_slot),
.waddr (write_addr_r),
.wdata (write_data),
.rden (1'b1),
.raddr (read_addr),
.rdata (read_data)
);

2
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -5,7 +5,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter OUT_REG = 0
parameter OUT_REG = 0
) (
input wire clk,
input wire reset,

28
hw/rtl/libs/VX_sp_ram.v
View File

@@ -5,10 +5,10 @@ module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUT_REG = 0,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter ADDRW = $clog2(SIZE),
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
@@ -16,8 +16,7 @@ module VX_sp_ram #(
input wire clk,
input wire [ADDRW-1:0] addr,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] wdata,
input wire rden,
input wire [DATAW-1:0] wdata,
output wire [DATAW-1:0] rdata
);
@@ -47,8 +46,7 @@ module VX_sp_ram #(
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
@@ -58,13 +56,11 @@ module VX_sp_ram #(
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -103,8 +99,7 @@ module VX_sp_ram #(
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -114,13 +109,11 @@ module VX_sp_ram #(
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -185,8 +178,7 @@ module VX_sp_ram #(
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
@@ -196,13 +188,11 @@ module VX_sp_ram #(
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;