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bus arbiters refactoring

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This commit is contained in:
Blaise Tine
2021-07-30 16:00:09 -07:00
parent b6596494ff
commit 3d19588e57
5 changed files with 330 additions and 146 deletions
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114
hw/rtl/libs/VX_stream_arbiter.v
View File

@@ -2,6 +2,7 @@
module VX_stream_arbiter #(
parameter NUM_REQS = 1,
parameter LANES = 1,
parameter DATAW = 1,
parameter TYPE = "R",
parameter LOCK_ENABLE = 1,
@@ -10,21 +11,36 @@ module VX_stream_arbiter #(
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] valid_in,
input wire [NUM_REQS-1:0][DATAW-1:0] data_in,
output wire [NUM_REQS-1:0] ready_in,
input wire [NUM_REQS-1:0][LANES-1:0] valid_in,
input wire [NUM_REQS-1:0][LANES-1:0][DATAW-1:0] data_in,
output wire [NUM_REQS-1:0][LANES-1:0] ready_in,
output wire valid_out,
output wire [DATAW-1:0] data_out,
input wire ready_out
output wire [LANES-1:0] valid_out,
output wire [LANES-1:0][DATAW-1:0] data_out,
input wire [LANES-1:0] ready_out
);
localparam LOG_NUM_REQS = $clog2(NUM_REQS);
if (NUM_REQS > 1) begin
wire sel_valid;
wire sel_ready;
wire [NUM_REQS-1:0] sel_1hot;
wire sel_valid;
wire sel_ready;
wire [NUM_REQS-1:0] sel_1hot;
wire [NUM_REQS-1:0] valid_in_any;
wire [LANES-1:0] ready_in_sel;
if (LANES > 1) begin
for (genvar i = 0; i < NUM_REQS; i++) begin
assign valid_in_any[i] = (| valid_in[i]);
end
assign sel_ready = (| ready_in_sel);
end else begin
for (genvar i = 0; i < NUM_REQS; i++) begin
assign valid_in_any[i] = valid_in[i];
end
assign sel_ready = ready_in_sel;
end
if (TYPE == "X") begin
VX_fixed_arbiter #(
@@ -33,7 +49,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.requests (valid_in_any),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_onehot (sel_1hot),
@@ -46,7 +62,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.requests (valid_in_any),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_onehot (sel_1hot),
@@ -59,7 +75,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.requests (valid_in_any),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_onehot (sel_1hot),
@@ -72,7 +88,7 @@ module VX_stream_arbiter #(
) sel_arb (
.clk (clk),
.reset (reset),
.requests (valid_in),
.requests (valid_in_any),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_onehot (sel_1hot),
@@ -82,34 +98,58 @@ module VX_stream_arbiter #(
$error ("invalid parameter");
end
wire [DATAW-1:0] data_in_sel;
wire [LANES-1:0] valid_in_sel;
wire [LANES-1:0][DATAW-1:0] data_in_sel;
VX_onehot_mux #(
.DATAW (DATAW),
.N (NUM_REQS)
) data_in_mux (
.data_in (data_in),
.sel_in (sel_1hot),
.data_out (data_in_sel)
);
if (LANES > 1) begin
wire [NUM_REQS-1:0][(LANES * (1 + DATAW))-1:0] valid_data_in;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (sel_valid),
.data_in (data_in_sel),
.ready_in (sel_ready),
.valid_out (valid_out),
.data_out (data_out),
.ready_out (ready_out)
);
for (genvar i = 0; i < NUM_REQS; i++) begin
assign valid_data_in[i] = {valid_in[i], data_in[i]};
end
VX_onehot_mux #(
.DATAW (LANES * (1 + DATAW)),
.N (NUM_REQS)
) data_in_mux (
.data_in (valid_data_in),
.sel_in (sel_1hot),
.data_out ({valid_in_sel, data_in_sel})
);
`UNUSED_VAR (sel_valid)
end else begin
VX_onehot_mux #(
.DATAW (DATAW),
.N (NUM_REQS)
) data_in_mux (
.data_in (data_in),
.sel_in (sel_1hot),
.data_out (data_in_sel)
);
assign valid_in_sel = sel_valid;
end
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && sel_ready;
assign ready_in[i] = ready_in_sel & {LANES{sel_1hot[i]}};
end
for (genvar i = 0; i < LANES; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (valid_in_sel[i]),
.data_in (data_in_sel[i]),
.ready_in (ready_in_sel[i]),
.valid_out (valid_out[i]),
.data_out (data_out[i]),
.ready_out (ready_out[i])
);
end
end else begin

75
hw/rtl/libs/VX_stream_demux.v
View File

@@ -2,6 +2,7 @@
module VX_stream_demux #(
parameter NUM_REQS = 1,
parameter LANES = 1,
parameter DATAW = 1,
parameter BUFFERED = 0,
localparam LOG_NUM_REQS = `LOG2UP(NUM_REQS)
@@ -9,60 +10,58 @@ module VX_stream_demux #(
input wire clk,
input wire reset,
input wire [LOG_NUM_REQS-1:0] sel,
input wire [LANES-1:0][LOG_NUM_REQS-1:0] sel_in,
input wire valid_in,
input wire [DATAW-1:0] data_in,
output wire ready_in,
input wire [LANES-1:0] valid_in,
input wire [LANES-1:0][DATAW-1:0] data_in,
output wire [LANES-1:0] ready_in,
output wire [NUM_REQS-1:0] valid_out,
output wire [NUM_REQS-1:0][DATAW-1:0] data_out,
input wire [NUM_REQS-1:0] ready_out
output wire [NUM_REQS-1:0][LANES-1:0] valid_out,
output wire [NUM_REQS-1:0][LANES-1:0][DATAW-1:0] data_out,
input wire [NUM_REQS-1:0][LANES-1:0] ready_out
);
if (NUM_REQS > 1) begin
reg [NUM_REQS-1:0] valid_out_unqual;
wire [NUM_REQS-1:0][DATAW-1:0] data_out_unqual;
wire [NUM_REQS-1:0] ready_out_unqual;
for (genvar j = 0; j < LANES; ++j) begin
always @(*) begin
valid_out_unqual = '0;
valid_out_unqual[sel] = valid_in;
end
for (genvar i = 0; i < NUM_REQS; i++) begin
assign data_out_unqual[i] = data_in;
end
assign ready_in = ready_out_unqual[sel];
reg [NUM_REQS-1:0] valid_in_sel;
wire [NUM_REQS-1:0] ready_in_sel;
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (valid_out_unqual[i]),
.data_in (data_out_unqual[i]),
.ready_in (ready_out_unqual[i]),
.valid_out (valid_out[i]),
.data_out (data_out[i]),
.ready_out (ready_out[i])
);
always @(*) begin
valid_in_sel = '0;
valid_in_sel[sel_in[j]] = valid_in[j];
end
assign ready_in[j] = ready_in_sel[sel_in[j]];
for (genvar i = 0; i < NUM_REQS; i++)
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),
.valid_in (valid_in_sel[i]),
.data_in (data_in[j]),
.ready_in (ready_in_sel[i]),
.valid_out (valid_out[i][j]),
.data_out (data_out[i][j]),
.ready_out (ready_out[i][j])
);
end
end
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (sel)
`UNUSED_VAR (sel_in)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
assign ready_in = ready_out;
end