fmax optimization bundle (250 MHz).
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@@ -85,8 +85,7 @@ module VX_fp_cvt #(
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assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i];
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assign fmt_mantissa = INT_MAN_WIDTH'({fp_clss[i].is_normal, dataa[i][MAN_BITS-1:0]});
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assign fmt_exponent[i] = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} +
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{1'b0, fp_clss[i].is_subnormal} +
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(FMT_SHIFT_COMPENSATION - EXP_BIAS);
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{1'b0, fp_clss[i].is_subnormal};
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assign encoded_mant[i] = is_itof ? int_mantissa : fmt_mantissa;
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assign input_sign[i] = is_itof ? int_sign : fmt_sign;
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`IGNORE_WARNINGS_END
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@@ -144,7 +143,7 @@ module VX_fp_cvt #(
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assign input_mant_s0[i] = encoded_mant_s0[i] << renorm_shamt_s0[i];
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// Unbias exponent and compensate for shift
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wire [INT_EXP_WIDTH-1:0] fp_input_exp = fmt_exponent_s0[i] - {1'b0, renorm_shamt_s0[i]};
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wire [INT_EXP_WIDTH-1:0] fp_input_exp = fmt_exponent_s0[i] + (FMT_SHIFT_COMPENSATION - EXP_BIAS) - {1'b0, renorm_shamt_s0[i]};
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wire [INT_EXP_WIDTH-1:0] int_input_exp = (INT_MAN_WIDTH-1) - {1'b0, renorm_shamt_s0[i]};
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assign input_exp_s0[i] = is_itof_s0 ? int_input_exp : fp_input_exp;
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@@ -100,7 +100,7 @@ module VX_fp_ncomp #(
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VX_pipe_register #(
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.DATAW (1 + TAGW + `INST_FPU_BITS + `INST_FRM_BITS + LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fp_class_t) + 1 + 1)),
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.RESETW (1),
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.DEPTH (0)
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.DEPTH (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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