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cache specialization for in-order DRAM reponses

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Blaise Tine
2021-02-13 20:23:29 -08:00
parent 4aaaebab6e
commit 3c37db877a
7 changed files with 84 additions and 64 deletions
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9
hw/rtl/cache/VX_flush_ctrl.v vendored
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@@ -2,7 +2,7 @@
module VX_flush_ctrl #(
// Size of cache in bytes
parameter CACHE_SIZE = 16384,
parameter CACHE_SIZE = 16384,
// Size of line inside a bank in bytes
parameter CACHE_LINE_SIZE = 1,
// Number of banks
@@ -13,8 +13,7 @@ module VX_flush_ctrl #(
input wire clk,
input wire reset,
input wire flush,
output wire [`LINE_ADDR_WIDTH-1:0] addr,
input wire ready_out,
output wire [`LINE_SELECT_BITS-1:0] addr_out,
output wire valid_out
);
reg flush_enable;
@@ -25,7 +24,7 @@ module VX_flush_ctrl #(
flush_enable <= 1;
flush_ctr <= 0;
end else begin
if (flush_enable && ready_out) begin
if (flush_enable) begin
if (flush_ctr == ((2 ** `LINE_SELECT_BITS)-1)) begin
flush_enable <= 0;
end
@@ -34,7 +33,7 @@ module VX_flush_ctrl #(
end
end
assign addr = `LINE_ADDR_WIDTH'(flush_ctr);
assign addr_out = flush_ctr;
assign valid_out = flush_enable;
endmodule