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cache specialization for in-order DRAM reponses

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Blaise Tine
2021-02-13 20:23:29 -08:00
parent 4aaaebab6e
commit 3c37db877a
7 changed files with 84 additions and 64 deletions
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4
hw/rtl/VX_config.vh
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@@ -244,7 +244,7 @@
// Size of LSU Request Queue
`ifndef LSUQ_SIZE
`define LSUQ_SIZE (`NUM_WARPS * `NUM_THREADS)
`define LSUQ_SIZE 8
`endif
// Size of FPU Request Queue
@@ -313,7 +313,7 @@
// Miss Handling Register Size
`ifndef DMSHR_SIZE
`define DMSHR_SIZE (`LSUQ_SIZE / 2)
`define DMSHR_SIZE `LSUQ_SIZE
`endif
// DRAM Request Queue Size