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GPR ASIC Working

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This commit is contained in:
felsabbagh3
2019-10-29 23:20:16 -04:00
parent 3caae2b88e
commit 3b49b82c46
15 changed files with 168 additions and 99 deletions
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65
rtl/VX_gpr.v
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@@ -16,43 +16,31 @@ module VX_gpr (
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0));
`ifndef ASIC
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0)) && (VX_writeback_inter.rd != 0);
// `ifndef SYN
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.reset (reset),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
// byte_enabled_simple_dual_port_ram first_ram(
// .we (write_enable),
// .clk (clk),
// .reset (reset),
// .waddr (VX_writeback_inter.rd),
// .raddr1(VX_gpr_read.rs1),
// .raddr2(VX_gpr_read.rs2),
// .be (VX_writeback_inter.wb_valid),
// .wdata (VX_writeback_inter.write_data),
// .q1 (out_a_reg_data),
// .q2 (out_b_reg_data)
// );
`else
// `else
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0));
wire writing_to_zero = (VX_writeback_inter.rd == 5'h0);
reg[31:0] use_before;
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
integer i;
always @(posedge clk) begin
if (reset) begin
use_before = 0;
end else if (going_to_write) begin
use_before[VX_writeback_inter.rd] = 1;
end
end
wire[`NT_M1:0][31:0] write_bit_mask;
genvar curr_t;
@@ -65,15 +53,15 @@ module VX_gpr (
wire cenb = !going_to_write;
wire cena_1 = (VX_gpr_read.rs1 == 0);
wire cena_2 = (VX_gpr_read.rs2 == 0);
// wire cena_1 = (VX_gpr_read.rs1 == 0);
// wire cena_2 = (VX_gpr_read.rs2 == 0);
wire cena_1 = 0;
wire cena_2 = 0;
wire[`NT_M1:0][31:0] temp_a;
wire[`NT_M1:0][31:0] temp_b;
`ifndef SYN
genvar thread;
genvar curr_bit;
for (thread = 0; thread < `NT; thread = thread + 1)
@@ -84,18 +72,10 @@ module VX_gpr (
assign out_b_reg_data[thread][curr_bit] = (temp_b[thread][curr_bit] === 1'dx) ? 1'b0 : temp_b[thread][curr_bit];
end
end
`else
assign out_a_reg_data = (cena_1 | !use_before[VX_gpr_read.rs1]) ? 0 : temp_a;
assign out_b_reg_data = (cena_2 | !use_before[VX_gpr_read.rs2]) ? 0 : temp_b;
`endif
wire[`NT_M1:0][31:0] to_write = writing_to_zero ? 0 : VX_writeback_inter.write_data;
wire[`NT_M1:0][31:0] to_write = (VX_writeback_inter.rd != 0) ? VX_writeback_inter.write_data : 0;
// wire cena_1 = 0;
// wire cena_2 = 0;
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
.CENYA(),
@@ -173,6 +153,7 @@ module VX_gpr (
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// `endif
`endif
endmodule