From 3a9e79d97945342edd485ff79203e60d4e8b11fb Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 23 May 2020 22:23:25 -0400 Subject: [PATCH] revert byte_enable tag structure --- driver/rtlsim/Makefile | 2 +- hw/rtl/cache/VX_cache_config.vh | 1 - hw/rtl/cache/VX_tag_data_access.v | 6 +++--- hw/rtl/cache/VX_tag_data_structure.v | 18 +++++++++--------- hw/simulate/simulator.cpp | 2 +- 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index f5fe8ee2..ec49ac18 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -15,7 +15,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ #DBG_PRINT=$(DBG_PRINT_FLAGS) #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 +MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG = 1 diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index c4085e64..ce15198f 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -16,7 +16,6 @@ `define BANK_BITS `LOG2UP(NUM_BANKS) `define WORD_WIDTH (8 * WORD_SIZE) -`define BYTE_WIDTH (`WORD_WIDTH / 4) `define BANK_LINE_WIDTH (8 * BANK_LINE_SIZE) diff --git a/hw/rtl/cache/VX_tag_data_access.v b/hw/rtl/cache/VX_tag_data_access.v index 1a770aa2..5656ebe9 100644 --- a/hw/rtl/cache/VX_tag_data_access.v +++ b/hw/rtl/cache/VX_tag_data_access.v @@ -65,7 +65,7 @@ module VX_tag_data_access #( wire use_read_dirty_st1e; wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e; wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e; - wire[`BANK_LINE_WORDS-1:0][3:0] use_write_enable; + wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_write_enable; wire[`BANK_LINE_WIDTH-1:0] use_write_data; wire fill_sent; @@ -138,7 +138,7 @@ module VX_tag_data_access #( wire force_write = real_writefill; wire should_write; - wire [`BANK_LINE_WORDS-1:0][3:0] we; + wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we; wire [`BANK_LINE_WIDTH-1:0] data_write; if (WORD_SIZE == BANK_LINE_SIZE) begin @@ -150,7 +150,7 @@ module VX_tag_data_access #( && !is_snp_st1e; for (i = 0; i < `BANK_LINE_WORDS; i++) begin - assign we[i] = (force_write || (should_write && !real_writefill)) ? 4'b1111 : 4'b0000; + assign we[i] = (force_write || (should_write && !real_writefill)) ? {WORD_SIZE{1'b1}} : {WORD_SIZE{1'b0}}; end assign readword_st1e = use_read_data_st1e; diff --git a/hw/rtl/cache/VX_tag_data_structure.v b/hw/rtl/cache/VX_tag_data_structure.v index 491aa986..21e289a6 100644 --- a/hw/rtl/cache/VX_tag_data_structure.v +++ b/hw/rtl/cache/VX_tag_data_structure.v @@ -21,7 +21,7 @@ module VX_tag_data_structure #( output wire[`BANK_LINE_WIDTH-1:0] read_data, input wire invalidate, - input wire[`BANK_LINE_WORDS-1:0][3:0] write_enable, + input wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] write_enable, input wire write_fill, input wire[`LINE_SELECT_BITS-1:0] write_addr, input wire[`TAG_SELECT_BITS-1:0] tag_index, @@ -29,10 +29,10 @@ module VX_tag_data_structure #( input wire fill_sent ); - reg [`BANK_LINE_WORDS-1:0][3:0][`BYTE_WIDTH-1:0] data [`BANK_LINE_COUNT-1:0]; - reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0]; - reg valid [`BANK_LINE_COUNT-1:0]; - reg dirty [`BANK_LINE_COUNT-1:0]; + reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0]; + reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0]; + reg valid [`BANK_LINE_COUNT-1:0]; + reg dirty [`BANK_LINE_COUNT-1:0]; assign read_valid = valid [read_addr]; assign read_dirty = dirty [read_addr]; @@ -66,10 +66,10 @@ module VX_tag_data_structure #( end for (i = 0; i < `BANK_LINE_WORDS; i++) begin - if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * `BYTE_WIDTH +: `BYTE_WIDTH]; - if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * `BYTE_WIDTH +: `BYTE_WIDTH]; - if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * `BYTE_WIDTH +: `BYTE_WIDTH]; - if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * `BYTE_WIDTH +: `BYTE_WIDTH]; + if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * 8 +: 8]; + if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * 8 +: 8]; + if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * 8 +: 8]; + if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * 8 +: 8]; end end end diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index d00c2924..385d31e1 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -10,7 +10,7 @@ double sc_time_stamp() { Simulator::Simulator() { // force random values for unitialized signals - const char* args[] = {"", "+verilator+rand+reset+1", "+verilator+seed+0"}; + const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"}; Verilated::commandArgs(3, args); ram_ = nullptr;