From 3a0a9edacac6e821ba89461e0e9eda447ea5c0f2 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 28 Jun 2021 11:20:07 -0400 Subject: [PATCH] minor update --- tests/opencl/psort/Makefile | 63 ++ tests/opencl/psort/kernel.cl | 14 + tests/opencl/psort/kernel.pocl | Bin 0 -> 16995 bytes tests/opencl/psort/main.cc | 212 ++++ tests/opencl/psort/psort.dump | 1720 ++++++++++++++++++++++++++++++++ 5 files changed, 2009 insertions(+) create mode 100644 tests/opencl/psort/Makefile create mode 100644 tests/opencl/psort/kernel.cl create mode 100644 tests/opencl/psort/kernel.pocl create mode 100644 tests/opencl/psort/main.cc create mode 100644 tests/opencl/psort/psort.dump diff --git a/tests/opencl/psort/Makefile b/tests/opencl/psort/Makefile new file mode 100644 index 00000000..f1b48924 --- /dev/null +++ b/tests/opencl/psort/Makefile @@ -0,0 +1,63 @@ +LLVM_PREFIX ?= /opt/llvm-riscv +RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain +SYSROOT ?= $(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf +POCL_CC_PATH ?= /opt/pocl/compiler +POCL_RT_PATH ?= /opt/pocl/runtime + +OPTS ?= -n32 + +VORTEX_DRV_PATH ?= $(realpath ../../../driver) +VORTEX_RT_PATH ?= $(realpath ../../../runtime) + +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" + +CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -Wfatal-errors + +CXXFLAGS += -Wno-deprecated-declarations -Wno-unused-parameter + +CXXFLAGS += -I$(POCL_RT_PATH)/include + +LDFLAGS += -L$(POCL_RT_PATH)/lib -L$(VORTEX_DRV_PATH)/stub -lOpenCL -lvortex + +PROJECT = psort + +SRCS = main.cc + +all: $(PROJECT) kernel.pocl + +kernel.pocl: kernel.cl + LLVM_PREFIX=$(LLVM_PREFIX) POCL_DEBUG=all LD_LIBRARY_PATH=$(LLVM_PREFIX)/lib:$(POCL_CC_PATH)/lib $(POCL_CC_PATH)/bin/poclcc -LLCFLAGS $(K_LLCFLAGS) -CFLAGS $(K_CFLAGS) -LDFLAGS $(K_LDFLAGS) -o kernel.pocl kernel.cl + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +run-fpga: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-asesim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-vlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-simx: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +run-rtlsim: $(PROJECT) kernel.pocl + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean: + rm -rf $(PROJECT) *.o .depend + +clean-all: clean + rm -rf *.pocl *.dump + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif diff --git a/tests/opencl/psort/kernel.cl b/tests/opencl/psort/kernel.cl new file mode 100644 index 00000000..bf5c7bb9 --- /dev/null +++ b/tests/opencl/psort/kernel.cl @@ -0,0 +1,14 @@ +__kernel void psort (__global const float *in, __global float *out) +{ + int gid = get_global_id(0); + int n = get_global_size(0); + + float ref = in[gid]; + + int pos = 0; + for (int i = 0; i < n; ++i) { + float cur = in[i]; + pos += (cur < ref) || (cur == ref && i < gid); + } + out[pos] = ref; +} \ No newline at end of file diff --git a/tests/opencl/psort/kernel.pocl b/tests/opencl/psort/kernel.pocl new file mode 100644 index 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zvK+=Xt)Zfi+OK7O`M-(CqUJM1ag~w{XyB`COGDhSopIRPW7uMT!AAri$T3$#xkP#? z5YMau-(#@#HN@LIuc&Say4hh$ORb+LGxyjKYeX%h-hIpkypNGZH$;@>`zS=L0b6Cm z8=lY_-l_~QNu>ZuRUh|BlnXKcocjj=YBN*T=)D(`DgXF_-F9af02LUzs5hS zzr#PPzmI=5{|ERd>6`pB??1~w!T$;VxjxA!KbC(Eew%+1zQ#YnKg2)p|6TsURR6vF z^U;svpI!gk{3C`~|JjT<;FhJKUe2jba5O)# +#include +#include +#include +#include +#include +#include +#include + +#define KERNEL_NAME "psort" + +#define CL_CHECK(_expr) \ + do { \ + cl_int _err = _expr; \ + if (_err == CL_SUCCESS) \ + break; \ + printf("OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + cleanup(); \ + exit(-1); \ + } while (0) + +#define CL_CHECK2(_expr) \ + ({ \ + cl_int _err = CL_INVALID_VALUE; \ + decltype(_expr) _ret = _expr; \ + if (_err != CL_SUCCESS) { \ + printf("OpenCL Error: '%s' returned %d!\n", #_expr, (int)_err); \ + cleanup(); \ + exit(-1); \ + } \ + _ret; \ + }) + +static int read_kernel_file(const char* filename, uint8_t** data, size_t* size) { + if (nullptr == filename || nullptr == data || 0 == size) + return -1; + + FILE* fp = fopen(filename, "r"); + if (NULL == fp) { + fprintf(stderr, "Failed to load kernel."); + return -1; + } + fseek(fp , 0 , SEEK_END); + long fsize = ftell(fp); + rewind(fp); + + *data = (uint8_t*)malloc(fsize); + *size = fread(*data, 1, fsize, fp); + + fclose(fp); + + return 0; +} + +static bool almost_equal(float a, float b, int ulp = 4) { + union fi_t { int i; float f; }; + fi_t fa, fb; + fa.f = a; + fb.f = b; + return std::abs(fa.i - fb.i) <= ulp; +} + +cl_device_id device_id = NULL; +cl_context context = NULL; +cl_command_queue commandQueue = NULL; +cl_program program = NULL; +cl_kernel kernel = NULL; +cl_mem a_memobj = NULL; +cl_mem c_memobj = NULL; +float *h_a = NULL; +float *h_c = NULL; +uint8_t *kernel_bin = NULL; + +static void cleanup() { + if (commandQueue) clReleaseCommandQueue(commandQueue); + if (kernel) clReleaseKernel(kernel); + if (program) clReleaseProgram(program); + if (a_memobj) clReleaseMemObject(a_memobj); + if (c_memobj) clReleaseMemObject(c_memobj); + if (context) clReleaseContext(context); + if (device_id) clReleaseDevice(device_id); + + if (kernel_bin) free(kernel_bin); + if (h_a) free(h_a); + if (h_c) free(h_c); +} + +int size = 64; + +static void show_usage() { + printf("Usage: [-n size] [-h: help]\n"); +} + +static void parse_args(int argc, char **argv) { + int c; + while ((c = getopt(argc, argv, "n:h?")) != -1) { + switch (c) { + case 'n': + size = atoi(optarg); + break; + case 'h': + case '?': { + show_usage(); + exit(0); + } break; + default: + show_usage(); + exit(-1); + } + } + + printf("Workload size=%d\n", size); +} + +int main (int argc, char **argv) { + // parse command arguments + parse_args(argc, argv); + + cl_platform_id platform_id; + size_t kernel_size; + cl_int binary_status; + + // read kernel binary from file + if (0 != read_kernel_file("kernel.pocl", &kernel_bin, &kernel_size)) + return -1; + + // Getting platform and device information + CL_CHECK(clGetPlatformIDs(1, &platform_id, NULL)); + CL_CHECK(clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_DEFAULT, 1, &device_id, NULL)); + + printf("Create context\n"); + context = CL_CHECK2(clCreateContext(NULL, 1, &device_id, NULL, NULL, &_err)); + + printf("Allocate device buffers\n"); + size_t nbytes = size * sizeof(float); + a_memobj = CL_CHECK2(clCreateBuffer(context, CL_MEM_READ_ONLY, nbytes, NULL, &_err)); + c_memobj = CL_CHECK2(clCreateBuffer(context, CL_MEM_WRITE_ONLY, nbytes, NULL, &_err)); + + printf("Create program from kernel source\n"); + program = CL_CHECK2(clCreateProgramWithBinary( + context, 1, &device_id, &kernel_size, (const uint8_t**)&kernel_bin, &binary_status, &_err)); + if (program == NULL) { + cleanup(); + return -1; + } + + // Build program + CL_CHECK(clBuildProgram(program, 1, &device_id, NULL, NULL, NULL)); + + // Create kernel + kernel = CL_CHECK2(clCreateKernel(program, KERNEL_NAME, &_err)); + + // Set kernel arguments + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), (void *)&a_memobj)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), (void *)&c_memobj)); + + // Allocate memories for input arrays and output arrays. + h_a = (float*)malloc(nbytes); + h_c = (float*)malloc(nbytes); + + // Initialize values for array members. + for (int i = 0; i < size; ++i) { + h_a[i] = sinf(i)*sinf(i); + h_c[i] = 0xdeadbeef; + printf("*** [%d]: h_a=%f\n", i, h_a[i]); + } + + // Creating command queue + commandQueue = CL_CHECK2(clCreateCommandQueue(context, device_id, 0, &_err)); + + printf("Upload source buffers\n"); + CL_CHECK(clEnqueueWriteBuffer(commandQueue, a_memobj, CL_TRUE, 0, nbytes, h_a, 0, NULL, NULL)); + + printf("Execute the kernel\n"); + size_t global_work_size[1] = {size}; + size_t local_work_size[1] = {1}; + auto time_start = std::chrono::high_resolution_clock::now(); + CL_CHECK(clEnqueueNDRangeKernel(commandQueue, kernel, 1, NULL, global_work_size, local_work_size, 0, NULL, NULL)); + CL_CHECK(clFinish(commandQueue)); + auto time_end = std::chrono::high_resolution_clock::now(); + double elapsed = std::chrono::duration_cast(time_end - time_start).count(); + printf("Elapsed time: %lg ms\n", elapsed); + + printf("Download destination buffer\n"); + CL_CHECK(clEnqueueReadBuffer(commandQueue, c_memobj, CL_TRUE, 0, nbytes, h_c, 0, NULL, NULL)); + + printf("Verify result\n"); + int errors = 0; + for (int i = 0; i < size; ++i) { + float ref = h_a[i]; + int pos = 0; + for (uint32_t j = 0; j < size; ++j) { + float cur = h_a[j]; + pos += (cur < ref) || (cur == ref && j < i); + } + if (!almost_equal(h_c[pos], ref)) { + if (errors < 100) + printf("*** error: [%d] expected=%f, actual=%f\n", pos, ref, h_c[pos]); + ++errors; + } + } + if (0 == errors) { + printf("PASSED!\n"); + } else { + printf("FAILED! - %d errors\n", errors); + } + + // Clean up + cleanup(); + + return errors; +} diff --git a/tests/opencl/psort/psort.dump b/tests/opencl/psort/psort.dump new file mode 100644 index 00000000..615d983f --- /dev/null +++ b/tests/opencl/psort/psort.dump @@ -0,0 +1,1720 @@ + +/tmp/pocl_vortex_kernel-cd-5f-e9-7a-18.elf: file format ELF32-riscv + + +Disassembly of section .init: + +80000000 _start: +80000000: 97 05 00 00 auipc a1, 0 +80000004: 93 85 85 3d addi a1, a1, 984 +80000008: 73 25 10 fc csrr a0, 4033 +8000000c: 6b 10 b5 00 +80000010: ef 00 80 3c jal 968 +80000014: 13 05 10 00 addi a0, zero, 1 +80000018: 6b 00 05 00 +8000001c: 17 15 00 00 auipc a0, 1 +80000020: 13 05 85 41 addi a0, a0, 1048 +80000024: 17 16 00 00 auipc a2, 1 +80000028: 13 06 06 49 addi a2, a2, 1168 +8000002c: 33 06 a6 40 sub a2, a2, a0 +80000030: 93 05 00 00 mv a1, zero +80000034: ef 00 90 2a jal 2728 +80000038: 17 05 00 00 auipc a0, 0 +8000003c: 13 05 85 47 addi a0, a0, 1144 +80000040: ef 00 50 25 jal 2644 +80000044: ef 00 00 3d jal 976 +80000048: ef 00 00 02 jal 32 +8000004c: 6f 00 d0 25 j 2652 + +Disassembly of section .text: + +80000050 register_fini: +80000050: 93 07 00 00 mv a5, zero +80000054: 63 88 07 00 beqz a5, 16 +80000058: 37 05 00 80 lui a0, 524288 +8000005c: 13 05 05 4b addi a0, a0, 1200 +80000060: 6f 00 50 23 j 2612 +80000064: 67 80 00 00 ret + +80000068 main: +80000068: 13 01 01 ff addi sp, sp, -16 +8000006c: 23 26 11 00 sw ra, 12(sp) +80000070: 37 05 00 80 lui a0, 524288 +80000074: 93 05 45 1b addi a1, a0, 436 +80000078: 37 05 ff 7f lui a0, 524272 +8000007c: 13 06 45 03 addi a2, a0, 52 +80000080: 37 05 ff 7f lui a0, 524272 +80000084: ef 00 00 5d jal 1488 +80000088: 13 05 00 00 mv a0, zero +8000008c: 83 20 c1 00 lw ra, 12(sp) +80000090: 13 01 01 01 addi sp, sp, 16 +80000094: 67 80 00 00 ret + +80000098 _pocl_kernel_psort: +80000098: 13 01 01 ff addi sp, sp, -16 +8000009c: 23 26 11 00 sw ra, 12(sp) +800000a0: 23 24 81 00 sw s0, 8(sp) +800000a4: 23 22 91 00 sw s1, 4(sp) +800000a8: 23 20 21 01 sw s2, 0(sp) +800000ac: 13 04 01 01 addi s0, sp, 16 +800000b0: 13 71 c1 ff andi sp, sp, -4 +800000b4: 13 08 00 00 mv a6, zero +800000b8: 83 2e 86 01 lw t4, 24(a2) +800000bc: 03 23 c6 01 lw t1, 28(a2) +800000c0: 03 27 c6 00 lw a4, 12(a2) +800000c4: 83 27 06 00 lw a5, 0(a2) +800000c8: 83 28 06 02 lw a7, 32(a2) +800000cc: 33 86 de 02 mul a2, t4, a3 +800000d0: 33 0e c7 00 add t3, a4, a2 +800000d4: b3 8f d7 03 mul t6, a5, t4 +800000d8: 13 16 2e 00 slli a2, t3, 2 +800000dc: b3 02 c5 00 add t0, a0, a2 +800000e0: 6f 00 c0 00 j 12 +800000e4: 13 08 18 00 addi a6, a6, 1 +800000e8: 63 78 18 0b bgeu a6, a7, 176 +800000ec: 63 50 f0 09 blez t6, 128 +800000f0: 93 03 00 00 mv t2, zero +800000f4: 6f 00 c0 00 j 12 +800000f8: 93 83 13 00 addi t2, t2, 1 +800000fc: e3 f4 63 fe bgeu t2, t1, -24 +80000100: 13 0f 00 00 mv t5, zero +80000104: 6f 00 80 01 j 24 +80000108: 13 96 27 00 slli a2, a5, 2 +8000010c: 33 86 c5 00 add a2, a1, a2 +80000110: 13 0f 1f 00 addi t5, t5, 1 +80000114: 27 20 06 00 fsw ft0, 0(a2) +80000118: e3 70 df ff bgeu t5, t4, -32 +8000011c: 33 09 ee 01 add s2, t3, t5 +80000120: 13 16 29 00 slli a2, s2, 2 +80000124: 33 06 c5 00 add a2, a0, a2 +80000128: 07 20 06 00 flw ft0, 0(a2) +8000012c: 13 07 00 00 mv a4, zero +80000130: 93 07 00 00 mv a5, zero +80000134: 13 06 05 00 mv a2, a0 +80000138: 6f 00 40 01 j 20 +8000013c: b3 87 97 00 add a5, a5, s1 +80000140: 13 07 17 00 addi a4, a4, 1 +80000144: 13 06 46 00 addi a2, a2, 4 +80000148: e3 80 ef fc beq t6, a4, -64 +8000014c: 87 20 06 00 flw ft1, 0(a2) +80000150: d3 96 00 a0 flt.s a3, ft1, ft0 +80000154: 93 04 10 00 addi s1, zero, 1 +80000158: e3 92 06 fe bnez a3, -28 +8000015c: d3 a6 00 a0 feq.s a3, ft1, ft0 +80000160: b3 24 27 01 slt s1, a4, s2 +80000164: b3 f4 d4 00 and s1, s1, a3 +80000168: 6f f0 5f fd j -44 +8000016c: 13 06 00 00 mv a2, zero +80000170: 93 06 00 00 mv a3, zero +80000174: 13 87 02 00 mv a4, t0 +80000178: 83 27 07 00 lw a5, 0(a4) +8000017c: 23 a0 f5 00 sw a5, 0(a1) +80000180: 93 86 16 00 addi a3, a3, 1 +80000184: 13 07 47 00 addi a4, a4, 4 +80000188: e3 e8 d6 ff bltu a3, t4, -16 +8000018c: 13 06 16 00 addi a2, a2, 1 +80000190: e3 60 66 fe bltu a2, t1, -32 +80000194: 6f f0 1f f5 j -176 +80000198: 13 01 04 ff addi sp, s0, -16 +8000019c: 03 29 01 00 lw s2, 0(sp) +800001a0: 83 24 41 00 lw s1, 4(sp) +800001a4: 03 24 81 00 lw s0, 8(sp) +800001a8: 83 20 c1 00 lw ra, 12(sp) +800001ac: 13 01 01 01 addi sp, sp, 16 +800001b0: 67 80 00 00 ret + +800001b4 _pocl_kernel_psort_workgroup: +800001b4: 13 01 01 ff addi sp, sp, -16 +800001b8: 23 26 81 00 sw s0, 12(sp) +800001bc: 23 24 91 00 sw s1, 8(sp) +800001c0: 83 26 05 00 lw a3, 0(a0) +800001c4: 03 25 45 00 lw a0, 4(a0) +800001c8: 13 08 00 00 mv a6, zero +800001cc: 83 af 06 00 lw t6, 0(a3) +800001d0: 83 2e 05 00 lw t4, 0(a0) +800001d4: 03 af 85 01 lw t5, 24(a1) +800001d8: 03 a3 c5 01 lw t1, 28(a1) +800001dc: 03 a5 c5 00 lw a0, 12(a1) +800001e0: 83 a6 05 00 lw a3, 0(a1) +800001e4: 83 a8 05 02 lw a7, 32(a1) +800001e8: b3 05 cf 02 mul a1, t5, a2 +800001ec: 33 0e b5 00 add t3, a0, a1 +800001f0: b3 85 e6 03 mul a1, a3, t5 +800001f4: 13 15 2e 00 slli a0, t3, 2 +800001f8: b3 82 af 00 add t0, t6, a0 +800001fc: 6f 00 c0 00 j 12 +80000200: 13 08 18 00 addi a6, a6, 1 +80000204: 63 78 18 0b bgeu a6, a7, 176 +80000208: 63 50 b0 08 blez a1, 128 +8000020c: 93 03 00 00 mv t2, zero +80000210: 6f 00 c0 00 j 12 +80000214: 93 83 13 00 addi t2, t2, 1 +80000218: e3 f4 63 fe bgeu t2, t1, -24 +8000021c: 13 05 00 00 mv a0, zero +80000220: 6f 00 80 01 j 24 +80000224: 13 16 27 00 slli a2, a4, 2 +80000228: 33 86 ce 00 add a2, t4, a2 +8000022c: 13 05 15 00 addi a0, a0, 1 +80000230: 27 20 06 00 fsw ft0, 0(a2) +80000234: e3 70 e5 ff bgeu a0, t5, -32 +80000238: 33 06 ae 00 add a2, t3, a0 +8000023c: 93 16 26 00 slli a3, a2, 2 +80000240: b3 86 df 00 add a3, t6, a3 +80000244: 07 a0 06 00 flw ft0, 0(a3) +80000248: 93 07 00 00 mv a5, zero +8000024c: 13 07 00 00 mv a4, zero +80000250: 93 86 0f 00 mv a3, t6 +80000254: 6f 00 40 01 j 20 +80000258: 33 07 87 00 add a4, a4, s0 +8000025c: 93 87 17 00 addi a5, a5, 1 +80000260: 93 86 46 00 addi a3, a3, 4 +80000264: e3 80 f5 fc beq a1, a5, -64 +80000268: 87 a0 06 00 flw ft1, 0(a3) +8000026c: d3 94 00 a0 flt.s s1, ft1, ft0 +80000270: 13 04 10 00 addi s0, zero, 1 +80000274: e3 92 04 fe bnez s1, -28 +80000278: 53 a4 00 a0 feq.s s0, ft1, ft0 +8000027c: b3 a4 c7 00 slt s1, a5, a2 +80000280: 33 f4 84 00 and s0, s1, s0 +80000284: 6f f0 5f fd j -44 +80000288: 13 05 00 00 mv a0, zero +8000028c: 13 06 00 00 mv a2, zero +80000290: 93 86 02 00 mv a3, t0 +80000294: 03 a7 06 00 lw a4, 0(a3) +80000298: 23 a0 ee 00 sw a4, 0(t4) +8000029c: 13 06 16 00 addi a2, a2, 1 +800002a0: 93 86 46 00 addi a3, a3, 4 +800002a4: e3 68 e6 ff bltu a2, t5, -16 +800002a8: 13 05 15 00 addi a0, a0, 1 +800002ac: e3 60 65 fe bltu a0, t1, -32 +800002b0: 6f f0 1f f5 j -176 +800002b4: 83 24 81 00 lw s1, 8(sp) +800002b8: 03 24 c1 00 lw s0, 12(sp) +800002bc: 13 01 01 01 addi sp, sp, 16 +800002c0: 67 80 00 00 ret + +800002c4 _pocl_kernel_psort_workgroup_fast: +800002c4: 13 01 01 ff addi sp, sp, -16 +800002c8: 23 26 81 00 sw s0, 12(sp) +800002cc: 23 24 91 00 sw s1, 8(sp) +800002d0: 13 08 00 00 mv a6, zero +800002d4: 83 2f 05 00 lw t6, 0(a0) +800002d8: 83 2e 45 00 lw t4, 4(a0) +800002dc: 03 af 85 01 lw t5, 24(a1) +800002e0: 03 a3 c5 01 lw t1, 28(a1) +800002e4: 03 a5 c5 00 lw a0, 12(a1) +800002e8: 83 a6 05 00 lw a3, 0(a1) +800002ec: 83 a8 05 02 lw a7, 32(a1) +800002f0: b3 05 cf 02 mul a1, t5, a2 +800002f4: 33 0e b5 00 add t3, a0, a1 +800002f8: b3 85 e6 03 mul a1, a3, t5 +800002fc: 13 15 2e 00 slli a0, t3, 2 +80000300: b3 82 af 00 add t0, t6, a0 +80000304: 6f 00 c0 00 j 12 +80000308: 13 08 18 00 addi a6, a6, 1 +8000030c: 63 78 18 0b bgeu a6, a7, 176 +80000310: 63 50 b0 08 blez a1, 128 +80000314: 93 03 00 00 mv t2, zero +80000318: 6f 00 c0 00 j 12 +8000031c: 93 83 13 00 addi t2, t2, 1 +80000320: e3 f4 63 fe bgeu t2, t1, -24 +80000324: 93 06 00 00 mv a3, zero +80000328: 6f 00 80 01 j 24 +8000032c: 13 15 25 00 slli a0, a0, 2 +80000330: 33 85 ae 00 add a0, t4, a0 +80000334: 93 86 16 00 addi a3, a3, 1 +80000338: 27 20 05 00 fsw ft0, 0(a0) +8000033c: e3 f0 e6 ff bgeu a3, t5, -32 +80000340: 33 06 de 00 add a2, t3, a3 +80000344: 13 15 26 00 slli a0, a2, 2 +80000348: 33 85 af 00 add a0, t6, a0 +8000034c: 07 20 05 00 flw ft0, 0(a0) +80000350: 93 07 00 00 mv a5, zero +80000354: 13 05 00 00 mv a0, zero +80000358: 13 87 0f 00 mv a4, t6 +8000035c: 6f 00 40 01 j 20 +80000360: 33 05 85 00 add a0, a0, s0 +80000364: 93 87 17 00 addi a5, a5, 1 +80000368: 13 07 47 00 addi a4, a4, 4 +8000036c: e3 80 f5 fc beq a1, a5, -64 +80000370: 87 20 07 00 flw ft1, 0(a4) +80000374: d3 94 00 a0 flt.s s1, ft1, ft0 +80000378: 13 04 10 00 addi s0, zero, 1 +8000037c: e3 92 04 fe bnez s1, -28 +80000380: 53 a4 00 a0 feq.s s0, ft1, ft0 +80000384: b3 a4 c7 00 slt s1, a5, a2 +80000388: 33 f4 84 00 and s0, s1, s0 +8000038c: 6f f0 5f fd j -44 +80000390: 13 05 00 00 mv a0, zero +80000394: 13 06 00 00 mv a2, zero +80000398: 93 86 02 00 mv a3, t0 +8000039c: 03 a7 06 00 lw a4, 0(a3) +800003a0: 23 a0 ee 00 sw a4, 0(t4) +800003a4: 13 06 16 00 addi a2, a2, 1 +800003a8: 93 86 46 00 addi a3, a3, 4 +800003ac: e3 68 e6 ff bltu a2, t5, -16 +800003b0: 13 05 15 00 addi a0, a0, 1 +800003b4: e3 60 65 fe bltu a0, t1, -32 +800003b8: 6f f0 1f f5 j -176 +800003bc: 83 24 81 00 lw s1, 8(sp) +800003c0: 03 24 c1 00 lw s0, 12(sp) +800003c4: 13 01 01 01 addi sp, sp, 16 +800003c8: 67 80 00 00 ret + +800003cc _exit: +800003cc: ef 00 40 4b jal 1204 +800003d0: 13 05 00 00 mv a0, zero +800003d4: 6b 00 05 00 + +800003d8 vx_set_sp: +800003d8: 73 25 00 fc csrr a0, 4032 +800003dc: 6b 00 05 00 +800003e0: 97 11 00 00 auipc gp, 1 +800003e4: 93 81 81 42 addi gp, gp, 1064 +800003e8: 17 01 00 7f auipc sp, 520192 +800003ec: 13 01 81 c1 addi sp, sp, -1000 +800003f0: 93 05 00 40 addi a1, zero, 1024 +800003f4: 73 26 10 cc csrr a2, 3265 +800003f8: b3 85 c5 02 mul a1, a1, a2 +800003fc: 33 01 b1 40 sub sp, sp, a1 +80000400: f3 26 30 cc csrr a3, 3267 +80000404: 63 86 06 00 beqz a3, 12 +80000408: 13 05 00 00 mv a0, zero +8000040c: 6b 00 05 00 + +80000410 RETURN: +80000410: 67 80 00 00 ret + +80000414 __libc_init_array: +80000414: 13 01 01 ff addi sp, sp, -16 +80000418: 23 24 81 00 sw s0, 8(sp) +8000041c: 23 20 21 01 sw s2, 0(sp) +80000420: 37 14 00 80 lui s0, 524289 +80000424: 37 19 00 80 lui s2, 524289 +80000428: 93 07 04 00 mv a5, s0 +8000042c: 13 09 09 00 mv s2, s2 +80000430: 33 09 f9 40 sub s2, s2, a5 +80000434: 23 26 11 00 sw ra, 12(sp) +80000438: 23 22 91 00 sw s1, 4(sp) +8000043c: 13 59 29 40 srai s2, s2, 2 +80000440: 63 00 09 02 beqz s2, 32 +80000444: 13 04 04 00 mv s0, s0 +80000448: 93 04 00 00 mv s1, zero +8000044c: 83 27 04 00 lw a5, 0(s0) +80000450: 93 84 14 00 addi s1, s1, 1 +80000454: 13 04 44 00 addi s0, s0, 4 +80000458: e7 80 07 00 jalr a5 +8000045c: e3 18 99 fe bne s2, s1, -16 +80000460: 37 14 00 80 lui s0, 524289 +80000464: 37 19 00 80 lui s2, 524289 +80000468: 93 07 04 00 mv a5, s0 +8000046c: 13 09 49 00 addi s2, s2, 4 +80000470: 33 09 f9 40 sub s2, s2, a5 +80000474: 13 59 29 40 srai s2, s2, 2 +80000478: 63 00 09 02 beqz s2, 32 +8000047c: 13 04 04 00 mv s0, s0 +80000480: 93 04 00 00 mv s1, zero +80000484: 83 27 04 00 lw a5, 0(s0) +80000488: 93 84 14 00 addi s1, s1, 1 +8000048c: 13 04 44 00 addi s0, s0, 4 +80000490: e7 80 07 00 jalr a5 +80000494: e3 18 99 fe bne s2, s1, -16 +80000498: 83 20 c1 00 lw ra, 12(sp) +8000049c: 03 24 81 00 lw s0, 8(sp) +800004a0: 83 24 41 00 lw s1, 4(sp) +800004a4: 03 29 01 00 lw s2, 0(sp) +800004a8: 13 01 01 01 addi sp, sp, 16 +800004ac: 67 80 00 00 ret + +800004b0 __libc_fini_array: +800004b0: 13 01 01 ff addi sp, sp, -16 +800004b4: 23 24 81 00 sw s0, 8(sp) +800004b8: b7 17 00 80 lui a5, 524289 +800004bc: 37 14 00 80 lui s0, 524289 +800004c0: 13 04 44 00 addi s0, s0, 4 +800004c4: 93 87 47 00 addi a5, a5, 4 +800004c8: b3 87 87 40 sub a5, a5, s0 +800004cc: 23 22 91 00 sw s1, 4(sp) +800004d0: 23 26 11 00 sw ra, 12(sp) +800004d4: 93 d4 27 40 srai s1, a5, 2 +800004d8: 63 80 04 02 beqz s1, 32 +800004dc: 93 87 c7 ff addi a5, a5, -4 +800004e0: 33 84 87 00 add s0, a5, s0 +800004e4: 83 27 04 00 lw a5, 0(s0) +800004e8: 93 84 f4 ff addi s1, s1, -1 +800004ec: 13 04 c4 ff addi s0, s0, -4 +800004f0: e7 80 07 00 jalr a5 +800004f4: e3 98 04 fe bnez s1, -16 +800004f8: 83 20 c1 00 lw ra, 12(sp) +800004fc: 03 24 81 00 lw s0, 8(sp) +80000500: 83 24 41 00 lw s1, 4(sp) +80000504: 13 01 01 01 addi sp, sp, 16 +80000508: 67 80 00 00 ret + +8000050c spawn_kernel_callback: +8000050c: 13 01 01 fe addi sp, sp, -32 +80000510: 23 2e 11 00 sw ra, 28(sp) +80000514: 23 2c 81 00 sw s0, 24(sp) +80000518: 23 2a 91 00 sw s1, 20(sp) +8000051c: 23 28 21 01 sw s2, 16(sp) +80000520: 23 26 31 01 sw s3, 12(sp) +80000524: 23 24 41 01 sw s4, 8(sp) +80000528: 23 22 51 01 sw s5, 4(sp) +8000052c: f3 27 00 fc csrr a5, 4032 +80000530: 6b 80 07 00 +80000534: f3 26 50 cc csrr a3, 3269 +80000538: 73 29 30 cc csrr s2, 3267 +8000053c: 73 27 00 cc csrr a4, 3264 +80000540: 73 26 00 fc csrr a2, 4032 +80000544: b7 17 00 80 lui a5, 524289 +80000548: 93 96 26 00 slli a3, a3, 2 +8000054c: 93 87 47 43 addi a5, a5, 1076 +80000550: b3 87 d7 00 add a5, a5, a3 +80000554: 03 a4 07 00 lw s0, 0(a5) +80000558: 83 24 44 01 lw s1, 20(s0) +8000055c: 83 26 04 01 lw a3, 16(s0) +80000560: b3 2a 99 00 slt s5, s2, s1 +80000564: 93 87 04 00 mv a5, s1 +80000568: b3 8a da 00 add s5, s5, a3 +8000056c: b3 84 26 03 mul s1, a3, s2 +80000570: 63 54 f9 00 bge s2, a5, 8 +80000574: 93 07 09 00 mv a5, s2 +80000578: b3 84 f4 00 add s1, s1, a5 +8000057c: 83 25 04 00 lw a1, 0(s0) +80000580: 83 26 c4 00 lw a3, 12(s0) +80000584: 83 a9 05 00 lw s3, 0(a1) +80000588: 03 aa 45 00 lw s4, 4(a1) +8000058c: b3 84 c4 02 mul s1, s1, a2 +80000590: b3 87 ea 02 mul a5, s5, a4 +80000594: b3 84 d4 00 add s1, s1, a3 +80000598: b3 84 f4 00 add s1, s1, a5 +8000059c: b3 8a 9a 00 add s5, s5, s1 +800005a0: 33 8a 49 03 mul s4, s3, s4 +800005a4: 63 c0 54 07 blt s1, s5, 96 +800005a8: 6f 00 00 08 j 128 +800005ac: 03 47 a4 01 lbu a4, 26(s0) +800005b0: 83 46 94 01 lbu a3, 25(s0) +800005b4: 33 d7 e4 40 sra a4, s1, a4 +800005b8: b3 07 47 03 mul a5, a4, s4 +800005bc: b3 87 f4 40 sub a5, s1, a5 +800005c0: 63 80 06 06 beqz a3, 96 +800005c4: 83 46 b4 01 lbu a3, 27(s0) +800005c8: b3 d6 d7 40 sra a3, a5, a3 +800005cc: b3 88 36 03 mul a7, a3, s3 +800005d0: 03 ae 45 01 lw t3, 20(a1) +800005d4: 03 a3 05 01 lw t1, 16(a1) +800005d8: 03 a6 c5 00 lw a2, 12(a1) +800005dc: 03 28 44 00 lw a6, 4(s0) +800005e0: 03 25 84 00 lw a0, 8(s0) +800005e4: 93 84 14 00 addi s1, s1, 1 +800005e8: 33 07 c7 01 add a4, a4, t3 +800005ec: b3 86 66 00 add a3, a3, t1 +800005f0: b3 87 17 41 sub a5, a5, a7 +800005f4: 33 86 c7 00 add a2, a5, a2 +800005f8: e7 00 08 00 jalr a6 +800005fc: 63 86 9a 02 beq s5, s1, 44 +80000600: 83 25 04 00 lw a1, 0(s0) +80000604: 83 47 84 01 lbu a5, 24(s0) +80000608: e3 92 07 fa bnez a5, -92 +8000060c: 33 c7 44 03 div a4, s1, s4 +80000610: 83 46 94 01 lbu a3, 25(s0) +80000614: b3 07 47 03 mul a5, a4, s4 +80000618: b3 87 f4 40 sub a5, s1, a5 +8000061c: e3 94 06 fa bnez a3, -88 +80000620: b3 c6 37 03 div a3, a5, s3 +80000624: 6f f0 9f fa j -88 +80000628: 13 39 19 00 seqz s2, s2 +8000062c: 6b 00 09 00 +80000630: 83 20 c1 01 lw ra, 28(sp) +80000634: 03 24 81 01 lw s0, 24(sp) +80000638: 83 24 41 01 lw s1, 20(sp) +8000063c: 03 29 01 01 lw s2, 16(sp) +80000640: 83 29 c1 00 lw s3, 12(sp) +80000644: 03 2a 81 00 lw s4, 8(sp) +80000648: 83 2a 41 00 lw s5, 4(sp) +8000064c: 13 01 01 02 addi sp, sp, 32 +80000650: 67 80 00 00 ret + +80000654 vx_spawn_kernel: +80000654: 13 01 01 fc addi sp, sp, -64 +80000658: 23 2e 11 02 sw ra, 60(sp) +8000065c: 23 2c 81 02 sw s0, 56(sp) +80000660: 23 2a 91 02 sw s1, 52(sp) +80000664: 23 28 21 03 sw s2, 48(sp) +80000668: 23 26 31 03 sw s3, 44(sp) +8000066c: f3 28 20 fc csrr a7, 4034 +80000670: 73 23 10 fc csrr t1, 4033 +80000674: 73 24 00 fc csrr s0, 4032 +80000678: f3 27 50 cc csrr a5, 3269 +8000067c: 13 07 f0 01 addi a4, zero, 31 +80000680: 63 46 f7 0e blt a4, a5, 236 +80000684: 03 2e 05 00 lw t3, 0(a0) +80000688: 83 26 45 00 lw a3, 4(a0) +8000068c: 03 28 85 00 lw a6, 8(a0) +80000690: b3 0e 83 02 mul t4, t1, s0 +80000694: 13 07 10 00 addi a4, zero, 1 +80000698: b3 06 de 02 mul a3, t3, a3 +8000069c: 33 88 06 03 mul a6, a3, a6 +800006a0: 63 d4 0e 01 bge t4, a6, 8 +800006a4: 33 47 d8 03 div a4, a6, t4 +800006a8: 63 c0 e8 0e blt a7, a4, 224 +800006ac: 63 d0 e7 0c bge a5, a4, 192 +800006b0: 93 88 f8 ff addi a7, a7, -1 +800006b4: b3 4e e8 02 div t4, a6, a4 +800006b8: 93 84 0e 00 mv s1, t4 +800006bc: 63 96 f8 00 bne a7, a5, 12 +800006c0: 33 67 e8 02 rem a4, a6, a4 +800006c4: b3 04 d7 01 add s1, a4, t4 +800006c8: 33 c9 84 02 div s2, s1, s0 +800006cc: b3 e4 84 02 rem s1, s1, s0 +800006d0: 63 42 69 0c blt s2, t1, 196 +800006d4: 93 02 10 00 addi t0, zero, 1 +800006d8: 33 48 69 02 div a6, s2, t1 +800006dc: 63 06 08 00 beqz a6, 12 +800006e0: 93 02 08 00 mv t0, a6 +800006e4: 33 68 69 02 rem a6, s2, t1 +800006e8: d3 f7 06 d0 fcvt.s.w fa5, a3 +800006ec: 93 8f f6 ff addi t6, a3, -1 +800006f0: 13 0f fe ff addi t5, t3, -1 +800006f4: b7 19 00 80 lui s3, 524289 +800006f8: b3 f6 df 00 and a3, t6, a3 +800006fc: 93 89 49 43 addi s3, s3, 1076 +80000700: 93 b6 16 00 seqz a3, a3 +80000704: 23 22 a1 00 sw a0, 4(sp) +80000708: 23 24 b1 00 sw a1, 8(sp) +8000070c: 23 26 c1 00 sw a2, 12(sp) +80000710: 23 2a 51 00 sw t0, 20(sp) +80000714: 23 2c 01 01 sw a6, 24(sp) +80000718: 23 0e d1 00 sb a3, 28(sp) +8000071c: 33 87 fe 02 mul a4, t4, a5 +80000720: d3 8e 07 e0 fmv.x.w t4, fa5 +80000724: d3 77 0e d0 fcvt.s.w fa5, t3 +80000728: 93 97 27 00 slli a5, a5, 2 +8000072c: 33 7e cf 01 and t3, t5, t3 +80000730: d3 88 07 e0 fmv.x.w a7, fa5 +80000734: 93 de 7e 41 srai t4, t4, 23 +80000738: 13 3e 1e 00 seqz t3, t3 +8000073c: 93 d8 78 41 srai a7, a7, 23 +80000740: 93 8e 1e f8 addi t4, t4, -127 +80000744: 93 88 18 f8 addi a7, a7, -127 +80000748: b3 87 f9 00 add a5, s3, a5 +8000074c: 23 28 e1 00 sw a4, 16(sp) +80000750: 13 07 41 00 addi a4, sp, 4 +80000754: a3 0e c1 01 sb t3, 29(sp) +80000758: 23 0f d1 01 sb t4, 30(sp) +8000075c: a3 0f 11 01 sb a7, 31(sp) +80000760: 23 a0 e7 00 sw a4, 0(a5) +80000764: 63 4e 20 03 bgtz s2, 60 +80000768: 63 9c 04 04 bnez s1, 88 +8000076c: 83 20 c1 03 lw ra, 60(sp) +80000770: 03 24 81 03 lw s0, 56(sp) +80000774: 83 24 41 03 lw s1, 52(sp) +80000778: 03 29 01 03 lw s2, 48(sp) +8000077c: 83 29 c1 02 lw s3, 44(sp) +80000780: 13 01 01 04 addi sp, sp, 64 +80000784: 67 80 00 00 ret +80000788: 13 87 08 00 mv a4, a7 +8000078c: e3 c2 e7 f2 blt a5, a4, -220 +80000790: 6f f0 df fd j -36 +80000794: 13 08 00 00 mv a6, zero +80000798: 93 02 10 00 addi t0, zero, 1 +8000079c: 6f f0 df f4 j -180 +800007a0: 13 07 09 00 mv a4, s2 +800007a4: 63 54 23 01 bge t1, s2, 8 +800007a8: 13 07 03 00 mv a4, t1 +800007ac: b7 07 00 80 lui a5, 524288 +800007b0: 93 87 c7 50 addi a5, a5, 1292 +800007b4: 6b 10 f7 00 +800007b8: ef f0 5f d5 jal -684 +800007bc: e3 88 04 fa beqz s1, -80 +800007c0: 33 04 89 02 mul s0, s2, s0 +800007c4: 23 28 81 00 sw s0, 16(sp) +800007c8: 6b 80 04 00 +800007cc: 73 27 50 cc csrr a4, 3269 +800007d0: f3 27 20 cc csrr a5, 3266 +800007d4: 13 17 27 00 slli a4, a4, 2 +800007d8: b3 89 e9 00 add s3, s3, a4 +800007dc: 03 a5 09 00 lw a0, 0(s3) +800007e0: 83 25 05 00 lw a1, 0(a0) +800007e4: 83 26 c5 00 lw a3, 12(a0) +800007e8: 03 47 85 01 lbu a4, 24(a0) +800007ec: 03 a8 05 00 lw a6, 0(a1) +800007f0: 03 a6 45 00 lw a2, 4(a1) +800007f4: b3 87 d7 00 add a5, a5, a3 +800007f8: 33 06 c8 02 mul a2, a6, a2 +800007fc: 63 0e 07 06 beqz a4, 124 +80000800: 03 47 a5 01 lbu a4, 26(a0) +80000804: 33 d7 e7 40 sra a4, a5, a4 +80000808: 83 46 95 01 lbu a3, 25(a0) +8000080c: 33 06 e6 02 mul a2, a2, a4 +80000810: b3 87 c7 40 sub a5, a5, a2 +80000814: 63 8e 06 04 beqz a3, 92 +80000818: 83 48 b5 01 lbu a7, 27(a0) +8000081c: b3 d8 17 41 sra a7, a5, a7 +80000820: 33 08 18 03 mul a6, a6, a7 +80000824: 03 ae 45 01 lw t3, 20(a1) +80000828: 83 a6 05 01 lw a3, 16(a1) +8000082c: 03 a6 c5 00 lw a2, 12(a1) +80000830: 03 23 45 00 lw t1, 4(a0) +80000834: 03 25 85 00 lw a0, 8(a0) +80000838: 33 07 c7 01 add a4, a4, t3 +8000083c: b3 86 d8 00 add a3, a7, a3 +80000840: b3 87 07 41 sub a5, a5, a6 +80000844: 33 86 c7 00 add a2, a5, a2 +80000848: e7 00 03 00 jalr t1 +8000084c: 93 07 10 00 addi a5, zero, 1 +80000850: 6b 80 07 00 +80000854: 83 20 c1 03 lw ra, 60(sp) +80000858: 03 24 81 03 lw s0, 56(sp) +8000085c: 83 24 41 03 lw s1, 52(sp) +80000860: 03 29 01 03 lw s2, 48(sp) +80000864: 83 29 c1 02 lw s3, 44(sp) +80000868: 13 01 01 04 addi sp, sp, 64 +8000086c: 67 80 00 00 ret +80000870: b3 c8 07 03 div a7, a5, a6 +80000874: 6f f0 df fa j -84 +80000878: 33 c7 c7 02 div a4, a5, a2 +8000087c: 6f f0 df f8 j -116 + +80000880 vx_perf_dump: +80000880: f3 27 50 cc csrr a5, 3269 +80000884: 37 07 ff 00 lui a4, 4080 +80000888: b3 87 e7 00 add a5, a5, a4 +8000088c: 93 97 87 00 slli a5, a5, 8 +80000890: 73 27 00 b0 csrr a4, mcycle +80000894: 23 a0 e7 00 sw a4, 0(a5) +80000898: 73 27 10 b0 csrr a4, 2817 +8000089c: 23 a2 e7 00 sw a4, 4(a5) +800008a0: 73 27 20 b0 csrr a4, minstret +800008a4: 23 a4 e7 00 sw a4, 8(a5) +800008a8: 73 27 30 b0 csrr a4, mhpmcounter3 +800008ac: 23 a6 e7 00 sw a4, 12(a5) +800008b0: 73 27 40 b0 csrr a4, mhpmcounter4 +800008b4: 23 a8 e7 00 sw a4, 16(a5) +800008b8: 73 27 50 b0 csrr a4, mhpmcounter5 +800008bc: 23 aa e7 00 sw a4, 20(a5) +800008c0: 73 27 60 b0 csrr a4, mhpmcounter6 +800008c4: 23 ac e7 00 sw a4, 24(a5) +800008c8: 73 27 70 b0 csrr a4, mhpmcounter7 +800008cc: 23 ae e7 00 sw a4, 28(a5) +800008d0: 73 27 80 b0 csrr a4, mhpmcounter8 +800008d4: 23 a0 e7 02 sw a4, 32(a5) +800008d8: 73 27 90 b0 csrr a4, mhpmcounter9 +800008dc: 23 a2 e7 02 sw a4, 36(a5) +800008e0: 73 27 a0 b0 csrr a4, mhpmcounter10 +800008e4: 23 a4 e7 02 sw a4, 40(a5) +800008e8: 73 27 b0 b0 csrr a4, mhpmcounter11 +800008ec: 23 a6 e7 02 sw a4, 44(a5) +800008f0: 73 27 c0 b0 csrr a4, mhpmcounter12 +800008f4: 23 a8 e7 02 sw a4, 48(a5) +800008f8: 73 27 d0 b0 csrr a4, mhpmcounter13 +800008fc: 23 aa e7 02 sw a4, 52(a5) +80000900: 73 27 e0 b0 csrr a4, mhpmcounter14 +80000904: 23 ac e7 02 sw a4, 56(a5) +80000908: 73 27 f0 b0 csrr a4, mhpmcounter15 +8000090c: 23 ae e7 02 sw a4, 60(a5) +80000910: 73 27 00 b1 csrr a4, mhpmcounter16 +80000914: 23 a0 e7 04 sw a4, 64(a5) +80000918: 73 27 10 b1 csrr a4, mhpmcounter17 +8000091c: 23 a2 e7 04 sw a4, 68(a5) +80000920: 73 27 20 b1 csrr a4, mhpmcounter18 +80000924: 23 a4 e7 04 sw a4, 72(a5) +80000928: 73 27 30 b1 csrr a4, mhpmcounter19 +8000092c: 23 a6 e7 04 sw a4, 76(a5) +80000930: 73 27 40 b1 csrr a4, mhpmcounter20 +80000934: 23 a8 e7 04 sw a4, 80(a5) +80000938: 73 27 50 b1 csrr a4, mhpmcounter21 +8000093c: 23 aa e7 04 sw a4, 84(a5) +80000940: 73 27 60 b1 csrr a4, mhpmcounter22 +80000944: 23 ac e7 04 sw a4, 88(a5) +80000948: 73 27 70 b1 csrr a4, mhpmcounter23 +8000094c: 23 ae e7 04 sw a4, 92(a5) +80000950: 73 27 80 b1 csrr a4, mhpmcounter24 +80000954: 23 a0 e7 06 sw a4, 96(a5) +80000958: 73 27 90 b1 csrr a4, mhpmcounter25 +8000095c: 23 a2 e7 06 sw a4, 100(a5) +80000960: 73 27 a0 b1 csrr a4, mhpmcounter26 +80000964: 23 a4 e7 06 sw a4, 104(a5) +80000968: 73 27 b0 b1 csrr a4, mhpmcounter27 +8000096c: 23 a6 e7 06 sw a4, 108(a5) +80000970: 73 27 c0 b1 csrr a4, mhpmcounter28 +80000974: 23 a8 e7 06 sw a4, 112(a5) +80000978: 73 27 d0 b1 csrr a4, mhpmcounter29 +8000097c: 23 aa e7 06 sw a4, 116(a5) +80000980: 73 27 e0 b1 csrr a4, mhpmcounter30 +80000984: 23 ac e7 06 sw a4, 120(a5) +80000988: 73 27 f0 b1 csrr a4, mhpmcounter31 +8000098c: 23 ae e7 06 sw a4, 124(a5) +80000990: 73 27 00 b8 csrr a4, mcycleh +80000994: 23 a0 e7 08 sw a4, 128(a5) +80000998: 73 27 10 b8 csrr a4, 2945 +8000099c: 23 a2 e7 08 sw a4, 132(a5) +800009a0: 73 27 20 b8 csrr a4, minstreth +800009a4: 23 a4 e7 08 sw a4, 136(a5) +800009a8: 73 27 30 b8 csrr a4, mhpmcounter3h +800009ac: 23 a6 e7 08 sw a4, 140(a5) +800009b0: 73 27 40 b8 csrr a4, mhpmcounter4h +800009b4: 23 a8 e7 08 sw a4, 144(a5) +800009b8: 73 27 50 b8 csrr a4, mhpmcounter5h +800009bc: 23 aa e7 08 sw a4, 148(a5) +800009c0: 73 27 60 b8 csrr a4, mhpmcounter6h +800009c4: 23 ac e7 08 sw a4, 152(a5) +800009c8: 73 27 70 b8 csrr a4, mhpmcounter7h +800009cc: 23 ae e7 08 sw a4, 156(a5) +800009d0: 73 27 80 b8 csrr a4, mhpmcounter8h +800009d4: 23 a0 e7 0a sw a4, 160(a5) +800009d8: 73 27 90 b8 csrr a4, mhpmcounter9h +800009dc: 23 a2 e7 0a sw a4, 164(a5) +800009e0: 73 27 a0 b8 csrr a4, mhpmcounter10h +800009e4: 23 a4 e7 0a sw a4, 168(a5) +800009e8: 73 27 b0 b8 csrr a4, mhpmcounter11h +800009ec: 23 a6 e7 0a sw a4, 172(a5) +800009f0: 73 27 c0 b8 csrr a4, mhpmcounter12h +800009f4: 23 a8 e7 0a sw a4, 176(a5) +800009f8: 73 27 d0 b8 csrr a4, mhpmcounter13h +800009fc: 23 aa e7 0a sw a4, 180(a5) +80000a00: 73 27 e0 b8 csrr a4, mhpmcounter14h +80000a04: 23 ac e7 0a sw a4, 184(a5) +80000a08: 73 27 f0 b8 csrr a4, mhpmcounter15h +80000a0c: 23 ae e7 0a sw a4, 188(a5) +80000a10: 73 27 00 b9 csrr a4, mhpmcounter16h +80000a14: 23 a0 e7 0c sw a4, 192(a5) +80000a18: 73 27 10 b9 csrr a4, mhpmcounter17h +80000a1c: 23 a2 e7 0c sw a4, 196(a5) +80000a20: 73 27 20 b9 csrr a4, mhpmcounter18h +80000a24: 23 a4 e7 0c sw a4, 200(a5) +80000a28: 73 27 30 b9 csrr a4, mhpmcounter19h +80000a2c: 23 a6 e7 0c sw a4, 204(a5) +80000a30: 73 27 40 b9 csrr a4, mhpmcounter20h +80000a34: 23 a8 e7 0c sw a4, 208(a5) +80000a38: 73 27 50 b9 csrr a4, mhpmcounter21h +80000a3c: 23 aa e7 0c sw a4, 212(a5) +80000a40: 73 27 60 b9 csrr a4, mhpmcounter22h +80000a44: 23 ac e7 0c sw a4, 216(a5) +80000a48: 73 27 70 b9 csrr a4, mhpmcounter23h +80000a4c: 23 ae e7 0c sw a4, 220(a5) +80000a50: 73 27 80 b9 csrr a4, mhpmcounter24h +80000a54: 23 a0 e7 0e sw a4, 224(a5) +80000a58: 73 27 90 b9 csrr a4, mhpmcounter25h +80000a5c: 23 a2 e7 0e sw a4, 228(a5) +80000a60: 73 27 a0 b9 csrr a4, mhpmcounter26h +80000a64: 23 a4 e7 0e sw a4, 232(a5) +80000a68: 73 27 b0 b9 csrr a4, mhpmcounter27h +80000a6c: 23 a6 e7 0e sw a4, 236(a5) +80000a70: 73 27 c0 b9 csrr a4, mhpmcounter28h +80000a74: 23 a8 e7 0e sw a4, 240(a5) +80000a78: 73 27 d0 b9 csrr a4, mhpmcounter29h +80000a7c: 23 aa e7 0e sw a4, 244(a5) +80000a80: 73 27 e0 b9 csrr a4, mhpmcounter30h +80000a84: 23 ac e7 0e sw a4, 248(a5) +80000a88: 73 27 f0 b9 csrr a4, mhpmcounter31h +80000a8c: 23 ae e7 0e sw a4, 252(a5) +80000a90: 67 80 00 00 ret + +80000a94 atexit: +80000a94: 93 05 05 00 mv a1, a0 +80000a98: 93 06 00 00 mv a3, zero +80000a9c: 13 06 00 00 mv a2, zero +80000aa0: 13 05 00 00 mv a0, zero +80000aa4: 6f 00 40 11 j 276 + +80000aa8 exit: +80000aa8: 13 01 01 ff addi sp, sp, -16 +80000aac: 93 05 00 00 mv a1, zero +80000ab0: 23 24 81 00 sw s0, 8(sp) +80000ab4: 23 26 11 00 sw ra, 12(sp) +80000ab8: 13 04 05 00 mv s0, a0 +80000abc: ef 00 80 19 jal 408 +80000ac0: b7 17 00 80 lui a5, 524289 +80000ac4: 03 a5 07 43 lw a0, 1072(a5) +80000ac8: 83 27 c5 03 lw a5, 60(a0) +80000acc: 63 84 07 00 beqz a5, 8 +80000ad0: e7 80 07 00 jalr a5 +80000ad4: 13 05 04 00 mv a0, s0 +80000ad8: ef f0 5f 8f jal -1804 + +80000adc memset: +80000adc: 13 03 f0 00 addi t1, zero, 15 +80000ae0: 13 07 05 00 mv a4, a0 +80000ae4: 63 7e c3 02 bgeu t1, a2, 60 +80000ae8: 93 77 f7 00 andi a5, a4, 15 +80000aec: 63 90 07 0a bnez a5, 160 +80000af0: 63 92 05 08 bnez a1, 132 +80000af4: 93 76 06 ff andi a3, a2, -16 +80000af8: 13 76 f6 00 andi a2, a2, 15 +80000afc: b3 86 e6 00 add a3, a3, a4 +80000b00: 23 20 b7 00 sw a1, 0(a4) +80000b04: 23 22 b7 00 sw a1, 4(a4) +80000b08: 23 24 b7 00 sw a1, 8(a4) +80000b0c: 23 26 b7 00 sw a1, 12(a4) +80000b10: 13 07 07 01 addi a4, a4, 16 +80000b14: e3 66 d7 fe bltu a4, a3, -20 +80000b18: 63 14 06 00 bnez a2, 8 +80000b1c: 67 80 00 00 ret +80000b20: b3 06 c3 40 sub a3, t1, a2 +80000b24: 93 96 26 00 slli a3, a3, 2 +80000b28: 97 02 00 00 auipc t0, 0 +80000b2c: b3 86 56 00 add a3, a3, t0 +80000b30: 67 80 c6 00 jr 12(a3) +80000b34: 23 07 b7 00 sb a1, 14(a4) +80000b38: a3 06 b7 00 sb a1, 13(a4) +80000b3c: 23 06 b7 00 sb a1, 12(a4) +80000b40: a3 05 b7 00 sb a1, 11(a4) +80000b44: 23 05 b7 00 sb a1, 10(a4) +80000b48: a3 04 b7 00 sb a1, 9(a4) +80000b4c: 23 04 b7 00 sb a1, 8(a4) +80000b50: a3 03 b7 00 sb a1, 7(a4) +80000b54: 23 03 b7 00 sb a1, 6(a4) +80000b58: a3 02 b7 00 sb a1, 5(a4) +80000b5c: 23 02 b7 00 sb a1, 4(a4) +80000b60: a3 01 b7 00 sb a1, 3(a4) +80000b64: 23 01 b7 00 sb a1, 2(a4) +80000b68: a3 00 b7 00 sb a1, 1(a4) +80000b6c: 23 00 b7 00 sb a1, 0(a4) +80000b70: 67 80 00 00 ret +80000b74: 93 f5 f5 0f andi a1, a1, 255 +80000b78: 93 96 85 00 slli a3, a1, 8 +80000b7c: b3 e5 d5 00 or a1, a1, a3 +80000b80: 93 96 05 01 slli a3, a1, 16 +80000b84: b3 e5 d5 00 or a1, a1, a3 +80000b88: 6f f0 df f6 j -148 +80000b8c: 93 96 27 00 slli a3, a5, 2 +80000b90: 97 02 00 00 auipc t0, 0 +80000b94: b3 86 56 00 add a3, a3, t0 +80000b98: 93 82 00 00 mv t0, ra +80000b9c: e7 80 06 fa jalr -96(a3) +80000ba0: 93 80 02 00 mv ra, t0 +80000ba4: 93 87 07 ff addi a5, a5, -16 +80000ba8: 33 07 f7 40 sub a4, a4, a5 +80000bac: 33 06 f6 00 add a2, a2, a5 +80000bb0: e3 78 c3 f6 bgeu t1, a2, -144 +80000bb4: 6f f0 df f3 j -196 + +80000bb8 __register_exitproc: +80000bb8: b7 17 00 80 lui a5, 524289 +80000bbc: 03 a7 07 43 lw a4, 1072(a5) +80000bc0: 83 27 87 14 lw a5, 328(a4) +80000bc4: 63 8c 07 04 beqz a5, 88 +80000bc8: 03 a7 47 00 lw a4, 4(a5) +80000bcc: 13 08 f0 01 addi a6, zero, 31 +80000bd0: 63 4e e8 06 blt a6, a4, 124 +80000bd4: 13 18 27 00 slli a6, a4, 2 +80000bd8: 63 06 05 02 beqz a0, 44 +80000bdc: 33 83 07 01 add t1, a5, a6 +80000be0: 23 24 c3 08 sw a2, 136(t1) +80000be4: 83 a8 87 18 lw a7, 392(a5) +80000be8: 13 06 10 00 addi a2, zero, 1 +80000bec: 33 16 e6 00 sll a2, a2, a4 +80000bf0: b3 e8 c8 00 or a7, a7, a2 +80000bf4: 23 a4 17 19 sw a7, 392(a5) +80000bf8: 23 24 d3 10 sw a3, 264(t1) +80000bfc: 93 06 20 00 addi a3, zero, 2 +80000c00: 63 04 d5 02 beq a0, a3, 40 +80000c04: 13 07 17 00 addi a4, a4, 1 +80000c08: 23 a2 e7 00 sw a4, 4(a5) +80000c0c: b3 87 07 01 add a5, a5, a6 +80000c10: 23 a4 b7 00 sw a1, 8(a5) +80000c14: 13 05 00 00 mv a0, zero +80000c18: 67 80 00 00 ret +80000c1c: 93 07 c7 14 addi a5, a4, 332 +80000c20: 23 24 f7 14 sw a5, 328(a4) +80000c24: 6f f0 5f fa j -92 +80000c28: 83 a6 c7 18 lw a3, 396(a5) +80000c2c: 13 07 17 00 addi a4, a4, 1 +80000c30: 23 a2 e7 00 sw a4, 4(a5) +80000c34: 33 e6 c6 00 or a2, a3, a2 +80000c38: 23 a6 c7 18 sw a2, 396(a5) +80000c3c: b3 87 07 01 add a5, a5, a6 +80000c40: 23 a4 b7 00 sw a1, 8(a5) +80000c44: 13 05 00 00 mv a0, zero +80000c48: 67 80 00 00 ret +80000c4c: 13 05 f0 ff addi a0, zero, -1 +80000c50: 67 80 00 00 ret + +80000c54 __call_exitprocs: +80000c54: 13 01 01 fd addi sp, sp, -48 +80000c58: b7 17 00 80 lui a5, 524289 +80000c5c: 23 2c 41 01 sw s4, 24(sp) +80000c60: 03 aa 07 43 lw s4, 1072(a5) +80000c64: 23 20 21 03 sw s2, 32(sp) +80000c68: 23 26 11 02 sw ra, 44(sp) +80000c6c: 03 29 8a 14 lw s2, 328(s4) +80000c70: 23 24 81 02 sw s0, 40(sp) +80000c74: 23 22 91 02 sw s1, 36(sp) +80000c78: 23 2e 31 01 sw s3, 28(sp) +80000c7c: 23 2a 51 01 sw s5, 20(sp) +80000c80: 23 28 61 01 sw s6, 16(sp) +80000c84: 23 26 71 01 sw s7, 12(sp) +80000c88: 23 24 81 01 sw s8, 8(sp) +80000c8c: 63 00 09 04 beqz s2, 64 +80000c90: 13 0b 05 00 mv s6, a0 +80000c94: 93 8b 05 00 mv s7, a1 +80000c98: 93 0a 10 00 addi s5, zero, 1 +80000c9c: 93 09 f0 ff addi s3, zero, -1 +80000ca0: 83 24 49 00 lw s1, 4(s2) +80000ca4: 13 84 f4 ff addi s0, s1, -1 +80000ca8: 63 42 04 02 bltz s0, 36 +80000cac: 93 94 24 00 slli s1, s1, 2 +80000cb0: b3 04 99 00 add s1, s2, s1 +80000cb4: 63 84 0b 04 beqz s7, 72 +80000cb8: 83 a7 44 10 lw a5, 260(s1) +80000cbc: 63 80 77 05 beq a5, s7, 64 +80000cc0: 13 04 f4 ff addi s0, s0, -1 +80000cc4: 93 84 c4 ff addi s1, s1, -4 +80000cc8: e3 16 34 ff bne s0, s3, -20 +80000ccc: 83 20 c1 02 lw ra, 44(sp) +80000cd0: 03 24 81 02 lw s0, 40(sp) +80000cd4: 83 24 41 02 lw s1, 36(sp) +80000cd8: 03 29 01 02 lw s2, 32(sp) +80000cdc: 83 29 c1 01 lw s3, 28(sp) +80000ce0: 03 2a 81 01 lw s4, 24(sp) +80000ce4: 83 2a 41 01 lw s5, 20(sp) +80000ce8: 03 2b 01 01 lw s6, 16(sp) +80000cec: 83 2b c1 00 lw s7, 12(sp) +80000cf0: 03 2c 81 00 lw s8, 8(sp) +80000cf4: 13 01 01 03 addi sp, sp, 48 +80000cf8: 67 80 00 00 ret +80000cfc: 83 27 49 00 lw a5, 4(s2) +80000d00: 83 a6 44 00 lw a3, 4(s1) +80000d04: 93 87 f7 ff addi a5, a5, -1 +80000d08: 63 8e 87 04 beq a5, s0, 92 +80000d0c: 23 a2 04 00 sw zero, 4(s1) +80000d10: e3 88 06 fa beqz a3, -80 +80000d14: 83 27 89 18 lw a5, 392(s2) +80000d18: 33 97 8a 00 sll a4, s5, s0 +80000d1c: 03 2c 49 00 lw s8, 4(s2) +80000d20: b3 77 f7 00 and a5, a4, a5 +80000d24: 63 92 07 02 bnez a5, 36 +80000d28: e7 80 06 00 jalr a3 +80000d2c: 03 27 49 00 lw a4, 4(s2) +80000d30: 83 27 8a 14 lw a5, 328(s4) +80000d34: 63 14 87 01 bne a4, s8, 8 +80000d38: e3 04 f9 f8 beq s2, a5, -120 +80000d3c: e3 88 07 f8 beqz a5, -112 +80000d40: 13 89 07 00 mv s2, a5 +80000d44: 6f f0 df f5 j -164 +80000d48: 83 27 c9 18 lw a5, 396(s2) +80000d4c: 83 a5 44 08 lw a1, 132(s1) +80000d50: 33 77 f7 00 and a4, a4, a5 +80000d54: 63 1c 07 00 bnez a4, 24 +80000d58: 13 05 0b 00 mv a0, s6 +80000d5c: e7 80 06 00 jalr a3 +80000d60: 6f f0 df fc j -52 +80000d64: 23 22 89 00 sw s0, 4(s2) +80000d68: 6f f0 9f fa j -88 +80000d6c: 13 85 05 00 mv a0, a1 +80000d70: e7 80 06 00 jalr a3 +80000d74: 6f f0 9f fb j -72 + +Disassembly of section .init_array: + +80001000 __preinit_array_start: +80001000: 50 00 +80001002: 00 80 + +Disassembly of section .data: + +80001008 impure_data: +80001008: 00 00 +8000100a: 00 00 +8000100c: f4 12 +8000100e: 00 80 +80001010: 5c 13 +80001012: 00 80 +80001014: c4 13 +80001016: 00 80 + ... +800010b0: 01 00 +800010b2: 00 00 +800010b4: 00 00 +800010b6: 00 00 +800010b8: 0e 33 +800010ba: cd ab +800010bc: 34 12 +800010be: 6d e6 +800010c0: ec de +800010c2: 05 00 +800010c4: 0b 00 00 00 + ... + +Disassembly of section .sdata: + +80001430 _global_impure_ptr: +80001430: 08 10 +80001432: 00 80 + +Disassembly of section .bss: + +80001434 g_wspawn_args: +... + +Disassembly of section .comment: + +00000000 .comment: + 0: 63 6c 61 6e bltu sp, t1, 1784 + 4: 67 20 76 65 + 8: 72 73 + a: 69 6f + c: 6e 20 + e: 31 30 + 10: 2e 30 + 12: 2e 31 + 14: 20 28 + 16: 68 74 + 18: 74 70 + 1a: 73 3a 2f 2f csrrc s4, 754, t5 + 1e: 67 69 74 68 + 22: 75 62 + 24: 2e 63 + 26: 6f 6d 2f 6c jal s10, 1009346 + 2a: 6c 76 + 2c: 6d 2f + 2e: 6c 6c + 30: 76 6d + 32: 2d 70 + 34: 72 6f + 36: 6a 65 + 38: 63 74 2e 67 bgeu t3, s2, 1640 + 3c: 69 74 + 3e: 20 65 + 40: 66 33 + 42: 32 63 + 44: 36 31 + 46: 31 61 + 48: 61 32 + 4a: 31 34 + 4c: 64 65 + 4e: 61 38 + 50: 35 35 + 52: 33 36 34 65 + 56: 66 64 + 58: 37 62 61 34 lui tp, 214550 + 5c: 35 31 + 5e: 65 63 + 60: 35 65 + 62: 63 33 66 37 + 66: 34 29 + 68: 00 47 + 6a: 43 43 3a 20 fmadd.s ft6, fs4, ft3, ft4, rmm + 6e: 28 47 + 70: 4e 55 + 72: 29 20 + 74: 39 2e + 76: 32 2e + 78: 30 00 + +Disassembly of section .riscv.attributes: + +00000000 .riscv.attributes: + 0: 41 25 + 2: 00 00 + 4: 00 72 + 6: 69 73 + 8: 63 76 00 01 bgeu zero, a6, 12 + c: 1b 00 00 00 + 10: 04 10 + 12: 05 72 + 14: 76 33 + 16: 32 69 + 18: 32 70 + 1a: 30 5f + 1c: 6d 32 + 1e: 70 30 + 20: 5f 66 32 70 + 24: 30 00 + +Disassembly of section .symtab: + +00000000 .symtab: + ... + 14: 00 00 + 16: 00 80 + 18: 00 00 + 1a: 00 00 + 1c: 03 00 01 00 lb zero, 0(sp) + 20: 00 00 + 22: 00 00 + 24: 50 00 + 26: 00 80 + 28: 00 00 + 2a: 00 00 + 2c: 03 00 02 00 lb zero, 0(tp) + 30: 00 00 + 32: 00 00 + 34: 00 10 + 36: 00 80 + 38: 00 00 + 3a: 00 00 + 3c: 03 00 03 00 lb zero, 0(t1) + 40: 00 00 + 42: 00 00 + 44: 08 10 + 46: 00 80 + 48: 00 00 + 4a: 00 00 + 4c: 03 00 04 00 lb zero, 0(s0) + 50: 00 00 + 52: 00 00 + 54: 30 14 + 56: 00 80 + 58: 00 00 + 5a: 00 00 + 5c: 03 00 05 00 lb zero, 0(a0) + 60: 00 00 + 62: 00 00 + 64: 34 14 + 66: 00 80 + 68: 00 00 + 6a: 00 00 + 6c: 03 00 06 00 lb zero, 0(a2) + ... + 7c: 03 00 07 00 lb zero, 0(a4) + ... + 8c: 03 00 08 00 lb zero, 0(a6) + 90: 01 00 + ... + 9a: 00 00 + 9c: 04 00 + 9e: f1 ff + a0: 0e 00 + a2: 00 00 + a4: 10 04 + a6: 00 80 + a8: 00 00 + aa: 00 00 + ac: 00 00 + ae: 02 00 + b0: 15 00 + ... + ba: 00 00 + bc: 04 00 + be: f1 ff + c0: 25 00 + c2: 00 00 + c4: 50 00 + c6: 00 80 + c8: 18 00 + ca: 00 00 + cc: 02 00 + ce: 02 00 + d0: 33 00 00 00 add zero, zero, zero + ... + dc: 04 00 + de: f1 ff + e0: 57 00 00 00 + ... + ec: 04 00 + ee: f1 ff + f0: 63 00 00 00 beqz zero, 0 + ... + fc: 04 00 + fe: f1 ff + 100: 71 00 + ... + 10a: 00 00 + 10c: 04 00 + 10e: f1 ff + 110: 7c 00 + 112: 00 00 + 114: 0c 05 + 116: 00 80 + 118: 48 01 + 11a: 00 00 + 11c: 02 00 + 11e: 02 00 + 120: 92 00 + ... + 12a: 00 00 + 12c: 04 00 + 12e: f1 ff + 130: 9e 00 + ... + 13a: 00 00 + 13c: 04 00 + 13e: f1 ff + 140: a0 00 + ... + 14a: 00 00 + 14c: 04 00 + 14e: f1 ff + 150: 9c 00 + ... + 15a: 00 00 + 15c: 04 00 + 15e: f1 ff + 160: a7 00 00 00 + ... + 16c: 04 00 + 16e: f1 ff + 170: b0 00 + 172: 00 00 + 174: 08 10 + 176: 00 80 + 178: 28 04 + 17a: 00 00 + 17c: 01 00 + 17e: 04 00 + ... + 18c: 04 00 + 18e: f1 ff + 190: bc 00 + 192: 00 00 + 194: 04 10 + 196: 00 80 + 198: 00 00 + 19a: 00 00 + 19c: 00 00 + 19e: 03 00 cd 00 lb zero, 12(s10) + 1a2: 00 00 + 1a4: 04 10 + 1a6: 00 80 + 1a8: 00 00 + 1aa: 00 00 + 1ac: 00 00 + 1ae: 03 00 e0 00 lb zero, 14(zero) + 1b2: 00 00 + 1b4: 04 10 + 1b6: 00 80 + 1b8: 00 00 + 1ba: 00 00 + 1bc: 00 00 + 1be: 03 00 f1 00 lb zero, 15(sp) + 1c2: 00 00 + 1c4: 00 10 + 1c6: 00 80 + 1c8: 00 00 + 1ca: 00 00 + 1cc: 00 00 + 1ce: 03 00 05 01 lb zero, 16(a0) + 1d2: 00 00 + 1d4: 00 10 + 1d6: 00 80 + 1d8: 00 00 + 1da: 00 00 + 1dc: 00 00 + 1de: 03 00 18 01 lb zero, 17(a6) + 1e2: 00 00 + 1e4: 00 10 + 1e6: 00 80 + 1e8: 00 00 + 1ea: 00 00 + 1ec: 00 00 + 1ee: 03 00 2e 01 lb zero, 18(t3) + ... + 1fa: 00 00 + 1fc: 10 00 + 1fe: f1 ff + 200: 3c 01 + 202: 00 00 + 204: b4 01 + 206: 00 80 + 208: 10 01 + 20a: 00 00 + 20c: 12 00 + 20e: 02 00 + 210: 59 01 + 212: 00 00 + 214: 00 04 + 216: 00 00 + 218: 00 00 + 21a: 00 00 + 21c: 10 00 + 21e: f1 ff + 220: 66 01 + 222: 00 00 + 224: 34 14 + 226: 00 80 + 228: 80 00 + 22a: 00 00 + 22c: 11 00 + 22e: 06 00 + 230: 74 01 + 232: 00 00 + 234: 30 14 + 236: 00 80 + 238: 00 00 + 23a: 00 00 + 23c: 10 00 + 23e: 05 00 + 240: 84 01 + 242: 00 00 + 244: 08 18 + 246: 00 80 + 248: 00 00 + 24a: 00 00 + 24c: 10 00 + 24e: f1 ff + 250: 95 01 + 252: 00 00 + 254: 30 14 + 256: 00 80 + 258: 04 00 + 25a: 00 00 + 25c: 11 00 + 25e: 05 00 + 260: a8 01 + 262: 00 00 + 264: 14 04 + 266: 00 80 + 268: 9c 00 + 26a: 00 00 + 26c: 12 00 + 26e: 02 00 + 270: ba 01 + 272: 00 00 + 274: b0 04 + 276: 00 80 + 278: 5c 00 + 27a: 00 00 + 27c: 12 00 + 27e: 02 00 + 280: cc 01 + 282: 00 00 + 284: 00 00 + 286: 00 ff + 288: 00 00 + 28a: 00 00 + 28c: 10 00 + 28e: f1 ff + 290: d8 01 + 292: 00 00 + 294: d8 03 + 296: 00 80 + 298: 00 00 + 29a: 00 00 + 29c: 12 00 + 29e: 02 00 + 2a0: e2 01 + 2a2: 00 00 + 2a4: 54 0c + 2a6: 00 80 + 2a8: 24 01 + 2aa: 00 00 + 2ac: 12 00 + 2ae: 02 00 + 2b0: 4d 02 + 2b2: 00 00 + 2b4: 00 00 + 2b6: 00 80 + 2b8: 50 00 + 2ba: 00 00 + 2bc: 12 00 + 2be: 01 00 + 2c0: f3 01 00 00 + 2c4: b8 0b + 2c6: 00 80 + 2c8: 9c 00 + 2ca: 00 00 + 2cc: 12 00 + 2ce: 02 00 + 2d0: 07 02 00 00 + 2d4: 98 00 + 2d6: 00 80 + 2d8: 1c 01 + 2da: 00 00 + 2dc: 12 00 + 2de: 02 00 + 2e0: 1a 02 + 2e2: 00 00 + 2e4: b4 14 + 2e6: 00 80 + 2e8: 00 00 + 2ea: 00 00 + 2ec: 10 00 + 2ee: 06 00 + 2f0: 26 02 + 2f2: 00 00 + 2f4: c4 02 + 2f6: 00 80 + 2f8: 08 01 + 2fa: 00 00 + 2fc: 12 00 + 2fe: 02 00 + 300: 48 02 + 302: 00 00 + 304: 34 14 + 306: 00 80 + 308: 00 00 + 30a: 00 00 + 30c: 10 00 + 30e: 06 00 + 310: 54 02 + 312: 00 00 + 314: dc 0a + 316: 00 80 + 318: dc 00 + 31a: 00 00 + 31c: 12 00 + 31e: 02 00 + 320: 5b 02 00 00 + 324: 68 00 + 326: 00 80 + 328: 30 00 + 32a: 00 00 + 32c: 12 00 + 32e: 02 00 + 330: 60 02 + 332: 00 00 + 334: 94 0a + 336: 00 80 + 338: 14 00 + 33a: 00 00 + 33c: 12 00 + 33e: 02 00 + 340: 67 02 00 00 jalr tp, zero + 344: 08 10 + 346: 00 80 + 348: 00 00 + 34a: 00 00 + 34c: 10 00 + 34e: 04 00 + 350: 76 02 + 352: 00 00 + 354: 34 14 + 356: 00 80 + 358: 00 00 + 35a: 00 00 + 35c: 10 00 + 35e: 05 00 + 360: c8 00 + 362: 00 00 + 364: b4 14 + 366: 00 80 + 368: 00 00 + 36a: 00 00 + 36c: 10 00 + 36e: 06 00 + 370: 8b 02 00 00 + 374: a8 0a + 376: 00 80 + 378: 34 00 + 37a: 00 00 + 37c: 12 00 + 37e: 02 00 + 380: 7d 02 + 382: 00 00 + 384: 80 08 + 386: 00 80 + 388: 14 02 + 38a: 00 00 + 38c: 12 00 + 38e: 02 00 + 390: 8a 02 + 392: 00 00 + 394: cc 03 + 396: 00 80 + 398: 00 00 + 39a: 00 00 + 39c: 12 00 + 39e: 02 00 + 3a0: 90 02 + 3a2: 00 00 + 3a4: 54 06 + 3a6: 00 80 + 3a8: 2c 02 + 3aa: 00 00 + 3ac: 12 00 + 3ae: 02 00 + +Disassembly of section .strtab: + +00000000 .strtab: + 0: 00 76 + 2: 78 5f + 4: 73 74 61 72 csrrci s0, 1830, 2 + 8: 74 2e + a: 53 2e 6f 00 fadd.s ft8, ft10, ft6, rdn + e: 52 45 + 10: 54 55 + 12: 52 4e + 14: 00 5f + 16: 5f 63 61 6c + 1a: 6c 5f + 1c: 61 74 + 1e: 65 78 + 20: 69 74 + 22: 2e 63 + 24: 00 72 + 26: 65 67 + 28: 69 73 + 2a: 74 65 + 2c: 72 5f + 2e: 66 69 + 30: 6e 69 + 32: 00 70 + 34: 6f 63 6c 5f jal t1, 812534 + 38: 76 6f + 3a: 72 74 + 3c: 65 78 + 3e: 5f 6b 65 72 + 42: 6e 65 + 44: 6c 2d + 46: 65 64 + 48: 2d 66 + 4a: 31 2d + 4c: 35 32 + 4e: 2d 64 + 50: 36 2d + 52: 64 33 + 54: 2e 63 + 56: 00 70 + 58: 61 72 + 5a: 61 6c + 5c: 6c 65 + 5e: 6c 5f + 60: 62 63 + 62: 00 76 + 64: 78 5f + 66: 73 79 73 63 csrrci s2, 1591, 6 + 6a: 61 6c + 6c: 6c 73 + 6e: 2e 63 + 70: 00 76 + 72: 78 5f + 74: 73 70 61 77 csrci 1910, 2 + 78: 6e 2e + 7a: 63 00 73 70 beq t1, t2, 1792 + 7e: 61 77 + 80: 6e 5f + 82: 6b 65 72 6e + 86: 65 6c + 88: 5f 63 61 6c + 8c: 6c 62 + 8e: 61 63 + 90: 6b 00 76 78 + 94: 5f 70 65 72 + 98: 66 2e + 9a: 63 00 5f 5f beq t5, s5, 1504 + 9e: 61 74 + a0: 65 78 + a2: 69 74 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