wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

many fixes

Browse Source
This commit is contained in:
Blaise Tine
2021-03-27 20:58:12 -04:00
parent 2d48fe13c8
commit 39a8579c27
34 changed files with 5021 additions and 515 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
hw/rtl/VX_config.vh
View File

@@ -241,17 +241,16 @@
`define NUM_TEX_UNITS 2
`define CSR_TEX_STATES 8
`define CSR_TEX_STATES 7
`define CSR_TEX_BEGIN(x) (12'hFD0 + (x) * `CSR_TEX_STATES)
`define CSR_TEX_ADDR(x) (`CSR_TEX_BEGIN(x) + 12'h00)
`define CSR_TEX_FORMAT(x) (`CSR_TEX_BEGIN(x) + 12'h01)
`define CSR_TEX_WIDTH(x) (`CSR_TEX_BEGIN(x) + 12'h02)
`define CSR_TEX_HEIGHT(x) (`CSR_TEX_BEGIN(x) + 12'h03)
`define CSR_TEX_STRIDE(x) (`CSR_TEX_BEGIN(x) + 12'h04)
`define CSR_TEX_WRAP_U(x) (`CSR_TEX_BEGIN(x) + 12'h05)
`define CSR_TEX_WRAP_V(x) (`CSR_TEX_BEGIN(x) + 12'h06)
`define CSR_TEX_FILTER(x) (`CSR_TEX_BEGIN(x) + 12'h07)
`define CSR_TEX_WRAP(x) (`CSR_TEX_BEGIN(x) + 12'h02)
`define CSR_TEX_FILTER(x) (`CSR_TEX_BEGIN(x) + 12'h03)
`define CSR_TEX_MIPOFF(x) (`CSR_TEX_BEGIN(x) + 12'h04)
`define CSR_TEX_WIDTH(x) (`CSR_TEX_BEGIN(x) + 12'h05)
`define CSR_TEX_HEIGHT(x) (`CSR_TEX_BEGIN(x) + 12'h06)
// Pipeline Queues ////////////////////////////////////////////////////////////

5
hw/rtl/VX_csr_data.v
View File

@@ -203,8 +203,9 @@ module VX_csr_data #(
`CSR_MARCHID : read_data_r = `ARCHITECTURE_ID;
`CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID;
default: begin
assert(~read_enable) else $error("%t: invalid CSR read address: %0h", $time, read_addr);
default: begin
assert (~read_enable || read_addr >= `CSR_TEX_BEGIN(0) && read_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES))
else $error("%t: invalid CSR read address: %0h", $time, read_addr);
end
endcase
end

3
hw/rtl/VX_decode.v
View File

@@ -31,6 +31,7 @@ module VX_decode #(
wire [6:0] opcode = instr[6:0];
wire [2:0] func3 = instr[14:12];
wire [6:0] func7 = instr[31:25];
wire [1:0] func2 = instr[26:25];
wire [11:0] u_12 = instr[31:20];
wire [4:0] rd = instr[11:7];
@@ -361,7 +362,7 @@ module VX_decode #(
`ifdef EXT_TEX_ENABLE
3'h5: begin
op_type = `OP_BITS'(`GPU_TEX);
op_mod = `MOD_BITS'(instr[26:25]);
op_mod = `MOD_BITS'(func2);
use_rd = 1;
use_rs1 = 1;
use_rs2 = 1;

44
hw/rtl/tex_unit/VX_tex_addr.v
View File

@@ -19,18 +19,19 @@ module VX_tex_addr #(
input wire [31:0] req_PC,
input wire [REQ_INFO_WIDTH-1:0] req_info,
input wire [`TEX_FORMAT_BITS-1:0] format,
input wire [`TEX_FILTER_BITS-1:0] filter,
input wire [`TEX_WRAP_BITS-1:0] wrap_u,
input wire [`TEX_WRAP_BITS-1:0] wrap_v,
input wire [`TEX_ADDR_BITS-1:0] base_addr,
input wire [`TEX_STRIDE_BITS-1:0] log_stride,
input wire [`TEX_WIDTH_BITS-1:0] log_width,
input wire [`TEX_HEIGHT_BITS-1:0] log_height,
input wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] mip_offsets,
input wire [`NUM_THREADS-1:0][`TEX_WIDTH_BITS-1:0] log_widths,
input wire [`NUM_THREADS-1:0][`TEX_HEIGHT_BITS-1:0] log_heights,
input wire [`NUM_THREADS-1:0][31:0] coord_u,
input wire [`NUM_THREADS-1:0][31:0] coord_v,
input wire [`NUM_THREADS-1:0][31:0] lod,
// outputs
@@ -48,10 +49,19 @@ module VX_tex_addr #(
);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (lod)
wire [1:0][`NUM_THREADS-1:0][`FIXED_FRAC-1:0] u;
wire [1:0][`NUM_THREADS-1:0][`FIXED_FRAC-1:0] v;
wire [`TEX_STRIDE_BITS-1:0] log_stride;
// stride
VX_tex_stride #(
.CORE_ID (CORE_ID)
) tex_stride (
.format (format),
.log_stride (log_stride)
);
// addressing mode
@@ -60,10 +70,10 @@ module VX_tex_addr #(
wire [31:0] fu[1:0];
wire [31:0] fv[1:0];
assign fu[0] = coord_u[i] - (filter ? (`FIXED_HALF >> log_width) : 0);
assign fv[0] = coord_v[i] - (filter ? (`FIXED_HALF >> log_height) : 0);
assign fu[1] = coord_u[i] + (filter ? (`FIXED_HALF >> log_width) : 0);
assign fv[1] = coord_v[i] + (filter ? (`FIXED_HALF >> log_height) : 0);
assign fu[0] = coord_u[i] - (filter ? (`FIXED_HALF >> log_widths[i]) : 0);
assign fv[0] = coord_v[i] - (filter ? (`FIXED_HALF >> log_heights[i]) : 0);
assign fu[1] = coord_u[i] + (filter ? (`FIXED_HALF >> log_widths[i]) : 0);
assign fv[1] = coord_v[i] + (filter ? (`FIXED_HALF >> log_heights[i]) : 0);
VX_tex_wrap #(
.CORE_ID (CORE_ID)
@@ -107,15 +117,15 @@ module VX_tex_addr #(
wire [`FIXED_FRAC-1:0] x [1:0];
wire [`FIXED_FRAC-1:0] y [1:0];
assign x[0] = u[0][i] >> ((`FIXED_FRAC) - log_width);
assign x[1] = u[1][i] >> ((`FIXED_FRAC) - log_width);
assign y[0] = v[0][i] >> ((`FIXED_FRAC) - log_height);
assign y[1] = v[1][i] >> ((`FIXED_FRAC) - log_height);
assign x[0] = u[0][i] >> ((`FIXED_FRAC) - log_widths[i]);
assign x[1] = u[1][i] >> ((`FIXED_FRAC) - log_widths[i]);
assign y[0] = v[0][i] >> ((`FIXED_FRAC) - log_heights[i]);
assign y[1] = v[1][i] >> ((`FIXED_FRAC) - log_heights[i]);
assign addr[i][0] = base_addr + (32'(x[0]) + (32'(y[0]) << log_width)) << log_stride;
assign addr[i][1] = base_addr + (32'(x[1]) + (32'(y[0]) << log_width)) << log_stride;
assign addr[i][2] = base_addr + (32'(x[0]) + (32'(y[1]) << log_width)) << log_stride;
assign addr[i][3] = base_addr + (32'(x[1]) + (32'(y[1]) << log_width)) << log_stride;
assign addr[i][0] = base_addr + 32'(mip_offsets[i]) + (32'(x[0]) + (32'(y[0]) << log_widths[i])) << log_stride;
assign addr[i][1] = base_addr + 32'(mip_offsets[i]) + (32'(x[1]) + (32'(y[0]) << log_widths[i])) << log_stride;
assign addr[i][2] = base_addr + 32'(mip_offsets[i]) + (32'(x[0]) + (32'(y[1]) << log_widths[i])) << log_stride;
assign addr[i][3] = base_addr + 32'(mip_offsets[i]) + (32'(x[1]) + (32'(y[1]) << log_widths[i])) << log_stride;
end
wire stall_out = mem_req_valid && ~mem_req_ready;

40
hw/rtl/tex_unit/VX_tex_define.vh
View File

@@ -15,25 +15,33 @@
`define LERP_64(x1,x2,frac) ((x2 + (((x1 - x2) * frac) >> `BLEND_FRAC_64)) & 64'h00ff00ff00ff00ff)
`define TEX_ADDR_BITS 32
`define TEX_FORMAT_BITS 3
`define TEX_WRAP_BITS 2
`define TEX_WIDTH_BITS 4
`define TEX_HEIGHT_BITS 4
`define TEX_STRIDE_BITS 2
`define TEX_FILTER_BITS 1
`define TEX_ADDR_BITS 32
`define TEX_FORMAT_BITS 3
`define TEX_WRAP_BITS 2
`define TEX_WIDTH_BITS 4
`define TEX_HEIGHT_BITS 4
`define TEX_FILTER_BITS 1
`define TEX_WRAP_REPEAT 0
`define TEX_WRAP_CLAMP 1
`define TEX_WRAP_MIRROR 2
`define TEX_MIPOFF_BITS (2*12+1)
`define TEX_STRIDE_BITS 2
`define MAX_COLOR_WIDTH 8
`define NUM_COLOR_CHANNEL 4
`define TEX_LOD_BITS 4
`define TEX_MIP_BITS (`NTEX_BITS + `TEX_LOD_BITS)
`define TEX_COLOR_BITS 8
`define TEX_WRAP_REPEAT 0
`define TEX_WRAP_CLAMP 1
`define TEX_WRAP_MIRROR 2
`define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1)
`define TEX_FORMAT_R8G8B8 `TEX_FORMAT_BITS'(2)
`define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(3)
`define MAX_COLOR_WIDTH 8
`define NUM_COLOR_CHANNEL 4
`define TEX_COLOR_BITS 8
`define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(0)
`define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1)
`define TEX_FORMAT_R4G4B4A4 `TEX_FORMAT_BITS'(2)
`define TEX_FORMAT_L8A8 `TEX_FORMAT_BITS'(3)
`define TEX_FORMAT_L8 `TEX_FORMAT_BITS'(4)
`define TEX_FORMAT_A8 `TEX_FORMAT_BITS'(5)
`endif

36
hw/rtl/tex_unit/VX_tex_format.v
View File

@@ -1,7 +1,7 @@
`include "VX_tex_define.vh"
module VX_tex_format #(
parameter CORE_ID = 0,
parameter CORE_ID = 0,
parameter NUM_TEXELS = 4 //BILINEAR
) (
input wire [NUM_TEXELS-1:0][31:0] texel_data,
@@ -13,32 +13,32 @@ module VX_tex_format #(
`UNUSED_PARAM (CORE_ID)
reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
always @(*) begin
for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
case (format)
`TEX_FORMAT_R5G6B5: begin
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
formatted_texel_r[i][7:0] = {`TEX_COLOR_BITS{1'b0}};
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][4:0]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][10:5]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:11]);
formatted_texel_r[i][55:48] = {`TEX_COLOR_BITS{1'b0}};
if (i == 0)
color_enable_r = 4'b1110;
color_enable_r = 4'b0111;
end
`TEX_FORMAT_R8G8B8: begin
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
formatted_texel_r[i][7:0] = {`TEX_COLOR_BITS{1'b0}};
`TEX_FORMAT_R4G4B4A4: begin
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][3:0]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][7:4]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][11:8]);
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:12]);
if (i == 0)
color_enable_r = 4'b1110;
color_enable_r = 4'b0111;
end
default: begin // `TEX_FORMAT_R8G8B8A8:
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
formatted_texel_r[i][7:0] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][23:16]);
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][31:24]);
if (i == 0)
color_enable_r = 4'b1111;
end
@@ -46,9 +46,9 @@ module VX_tex_format #(
end
end
assign color_enable = color_enable_r;
assign color_enable = color_enable_r;
for (genvar i = 0;i<NUM_TEXELS ;i++ ) begin
for (genvar i = 0; i < NUM_TEXELS; i++) begin
assign formatted_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
end

4
hw/rtl/tex_unit/VX_tex_sampler.v
View File

@@ -33,8 +33,8 @@ module VX_tex_sampler #(
`UNUSED_PARAM (CORE_ID)
wire [`NUM_THREADS-1:0][31:0] req_data ;
wire [`NUM_THREADS-1:0][31:0] req_data_bilerp ;
wire [`NUM_THREADS-1:0][31:0] req_data;
wire [`NUM_THREADS-1:0][31:0] req_data_bilerp;
wire stall_out;

27
hw/rtl/tex_unit/VX_tex_stride.v Normal file
View File

@@ -0,0 +1,27 @@
`include "VX_tex_define.vh"
module VX_tex_stride #(
parameter CORE_ID = 0
) (
input wire [`TEX_FORMAT_BITS-1:0] format,
output wire [`TEX_STRIDE_BITS-1:0] log_stride
);
`UNUSED_PARAM (CORE_ID)
reg [`TEX_STRIDE_BITS-1:0] log_stride_r;
always @(*) begin
case (format)
`TEX_FORMAT_A8: log_stride_r = 0;
`TEX_FORMAT_L8: log_stride_r = 0;
`TEX_FORMAT_L8A8: log_stride_r = 1;
`TEX_FORMAT_R5G6B5: log_stride_r = 1;
`TEX_FORMAT_R4G4B4A4: log_stride_r = 1;
// `TEX_FORMAT_R8G8B8A8
default: log_stride_r = 2;
endcase
end
assign log_stride = log_stride_r;
endmodule

73
hw/rtl/tex_unit/VX_tex_unit.v
View File

@@ -24,25 +24,24 @@ module VX_tex_unit #(
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (reset)
reg [`TEX_ADDR_BITS-1:0] tex_addr [`NUM_TEX_UNITS-1: 0];
reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
reg [`TEX_WIDTH_BITS-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
reg [`TEX_HEIGHT_BITS-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
reg [`TEX_STRIDE_BITS-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
reg [`TEX_WRAP_BITS-1:0] tex_wrap_u [`NUM_TEX_UNITS-1: 0];
reg [`TEX_WRAP_BITS-1:0] tex_wrap_v [`NUM_TEX_UNITS-1: 0];
reg [`TEX_FILTER_BITS-1:0] tex_filter [`NUM_TEX_UNITS-1: 0];
reg [`TEX_MIPOFF_BITS-1:0] tex_mipoff [(1 << `TEX_MIP_BITS)-1:0];
reg [`TEX_WIDTH_BITS-1:0] tex_width [(1 << `TEX_MIP_BITS)-1:0];
reg [`TEX_HEIGHT_BITS-1:0] tex_height [(1 << `TEX_MIP_BITS)-1:0];
// CSRs programming
reg [`TEX_ADDR_BITS-1:0] tex_addr [`NUM_TEX_UNITS-1:0];
reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1:0];
reg [`TEX_WRAP_BITS-1:0] tex_wrap_u [`NUM_TEX_UNITS-1:0];
reg [`TEX_WRAP_BITS-1:0] tex_wrap_v [`NUM_TEX_UNITS-1:0];
reg [`TEX_FILTER_BITS-1:0] tex_filter [`NUM_TEX_UNITS-1:0];
// CSRs programming
for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
wire [`TEX_MIP_BITS-1:0] mip_waddr = tex_csr_if.write_data[24 +: `TEX_MIP_BITS];
always @(posedge clk ) begin
if (reset) begin
if (reset) begin
tex_addr[i] <= 0;
tex_format[i] <= 0;
tex_width[i] <= 0;
tex_height[i] <= 0;
tex_stride[i] <= 0;
tex_wrap_u[i] <= 0;
tex_wrap_v[i] <= 0;
tex_filter[i] <= 0;
@@ -51,12 +50,20 @@ module VX_tex_unit #(
case (tex_csr_if.write_addr)
`CSR_TEX_ADDR(i) : tex_addr[i] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0];
`CSR_TEX_FORMAT(i) : tex_format[i] <= tex_csr_if.write_data[`TEX_FORMAT_BITS-1:0];
`CSR_TEX_WIDTH(i) : tex_width[i] <= tex_csr_if.write_data[`TEX_WIDTH_BITS-1:0];
`CSR_TEX_HEIGHT(i) : tex_height[i] <= tex_csr_if.write_data[`TEX_HEIGHT_BITS-1:0];
`CSR_TEX_STRIDE(i) : tex_stride[i] <= tex_csr_if.write_data[`TEX_STRIDE_BITS-1:0];
`CSR_TEX_WRAP_U(i) : tex_wrap_u[i] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0];
`CSR_TEX_WRAP_V(i) : tex_wrap_v[i] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0];
`CSR_TEX_FILTER(i) : tex_filter[i] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0];
`CSR_TEX_WRAP(i) : begin
tex_wrap_u[i] <= tex_csr_if.write_data[0 +: `TEX_WRAP_BITS];
tex_wrap_v[i] <= tex_csr_if.write_data[`TEX_WRAP_BITS +: `TEX_WRAP_BITS];
end
`CSR_TEX_FILTER(i) : tex_filter[i] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0];
`CSR_TEX_MIPOFF(i) : begin
tex_mipoff[mip_waddr] <= tex_csr_if.write_data[`TEX_MIPOFF_BITS-1:0];
end
`CSR_TEX_WIDTH(i) : begin
tex_width[mip_waddr] <= tex_csr_if.write_data[`TEX_WIDTH_BITS-1:0];
end
`CSR_TEX_HEIGHT(i) : begin
tex_height[mip_waddr] <= tex_csr_if.write_data[`TEX_HEIGHT_BITS-1:0];
end
default:
assert(tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0)
&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES));
@@ -66,6 +73,19 @@ module VX_tex_unit #(
end
end
// mipmap attributes
wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] tex_mipoffs;
wire [`NUM_THREADS-1:0][`TEX_WIDTH_BITS-1:0] tex_widths;
wire [`NUM_THREADS-1:0][`TEX_HEIGHT_BITS-1:0] tex_heights;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
wire [`TEX_MIP_BITS-1:0] mip_raddr = {tex_req_if.unit[`NTEX_BITS-1:0], tex_req_if.lod[i][`TEX_LOD_BITS-1:0]};
assign tex_mipoffs[i] = tex_mipoff[mip_raddr];
assign tex_widths[i] = tex_width[mip_raddr];
assign tex_heights[i] = tex_height[mip_raddr];
end
// address generation
wire mem_req_valid;
@@ -87,7 +107,7 @@ module VX_tex_unit #(
wire [`TEX_FILTER_BITS-1:0] mem_rsp_filter;
wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
wire [REQ_INFO_WIDTH_M-1:0] mem_rsp_info;
wire mem_rsp_ready;
wire mem_rsp_ready;
VX_tex_addr #(
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A)
@@ -103,18 +123,18 @@ module VX_tex_unit #(
.req_PC (tex_req_if.PC),
.req_info ({tex_format[tex_req_if.unit], tex_req_if.rd, tex_req_if.wb}),
.format (tex_format[tex_req_if.unit]),
.filter (tex_filter[tex_req_if.unit]),
.wrap_u (tex_wrap_u[tex_req_if.unit]),
.wrap_v (tex_wrap_v[tex_req_if.unit]),
.base_addr (tex_addr[tex_req_if.unit]),
.log_stride (tex_stride[tex_req_if.unit]),
.log_width (tex_width[tex_req_if.unit]),
.log_height (tex_height[tex_req_if.unit]),
.base_addr (tex_addr[tex_req_if.unit]),
.mip_offsets (tex_mipoffs),
.log_widths (tex_widths),
.log_heights (tex_heights),
.coord_u (tex_req_if.u),
.coord_v (tex_req_if.v),
.lod (tex_req_if.lod),
.mem_req_valid (mem_req_valid),
.mem_req_wid (mem_req_wid),
@@ -211,10 +231,9 @@ module VX_tex_unit #(
&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(i)
&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(i+1))) begin
$display("%t: core%0d-tex_csr: csr_tex%d_addr, csr_data=%0h", $time, CORE_ID, i, tex_addr[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_format, csr_data=%0h", $time, CORE_ID, i, tex_format[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_width, csr_data=%0h", $time, CORE_ID, i, tex_width[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_height, csr_data=%0h", $time, CORE_ID, i, tex_height[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_stride, csr_data=%0h", $time, CORE_ID, i, tex_stride[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_format, csr_data=%0h", $time, CORE_ID, i, tex_format[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_wrap_u, csr_data=%0h", $time, CORE_ID, i, tex_wrap_u[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_wrap_v, csr_data=%0h", $time, CORE_ID, i, tex_wrap_v[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_filter, csr_data=%0h", $time, CORE_ID, i, tex_filter[i]);