synthesis fixes
This commit is contained in:
Blaise Tine
@@ -1,60 +1,57 @@
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PROJECT = Vortex
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TOP_LEVEL_ENTITY = Vortex
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SRC_FILE = Vortex.v
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SRC_FILE = ../Vortex.v
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PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
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QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
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# Part, Family
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FAMILY = "Arria 10"
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DEVICE = 10AX115N4F45I3SG
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DEVICE = 10AX115N3F40E2SG
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# Executable Configuration
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SYN_ARGS = --read_settings_files=on
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SYN_ARGS = --parallel --read_settings_files=on
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FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
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ASM_ARGS =
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STA_ARGS = --do_report_timing
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# Build targets
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all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt
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all: $(PROJECT).sta.rpt
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syn: smart.log $(PROJECT).syn.rpt
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syn: $(PROJECT).syn.rpt
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fit: smart.log $(PROJECT).fit.rpt
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fit: $(PROJECT).fit.rpt
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asm: smart.log $(PROJECT).asm.rpt
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asm: $(PROJECT).asm.rpt
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sta: smart.log $(PROJECT).sta.rpt
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sta: $(PROJECT).sta.rpt
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smart: smart.log
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# Target implementations
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STAMP = echo done >
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$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES)
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$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl
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$(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
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# $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl
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$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
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quartus_syn $(PROJECT) $(SYN_ARGS)
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$(STAMP) fit.chg
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$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt
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$(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
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$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
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quartus_fit $(PROJECT) $(FIT_ARGS)
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$(STAMP) asm.chg
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$(STAMP) sta.chg
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$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
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$(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
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$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
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quartus_asm $(PROJECT) $(ASM_ARGS)
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$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
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$(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
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$(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl
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$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
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quartus_sta $(PROJECT) $(STA_ARGS)
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smart.log: $(PROJECT_FILES)
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$(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
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quartus_sh --determine_smart_action $(PROJECT) > smart.log
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# Project initialization
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$(PROJECT_FILES):
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$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc
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quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat"
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syn.chg:
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$(STAMP) syn.chg
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@@ -72,4 +69,4 @@ program: $(PROJECT).sof
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quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
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clean:
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rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox bin/
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rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
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@@ -1,30 +0,0 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
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# Date created = 00:18:19 September 11, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "18.0"
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DATE = "00:18:19 September 11, 2019"
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# Revisions
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PROJECT_REVISION = "VX_gpr_syn"
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File diff suppressed because it is too large
Load Diff
@@ -1 +0,0 @@
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done
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@@ -1,29 +0,0 @@
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load_package flow
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package require cmdline
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project_open Vortex
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proc make_all_pins_virtual { args } {
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remove_all_instance_assignments -name VIRTUAL_PIN
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execute_module -tool map
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set name_ids [get_names -filter * -node_type pin]
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foreach_in_collection name_id $name_ids {
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set pin_name [get_name_info -info full_path $name_id]
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if { -1 == [lsearch -exact { clk, reset } $pin_name] } {
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post_message "Making VIRTUAL_PIN assignment to $pin_name"
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set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
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} else {
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post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
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}
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}
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export_assignments
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}
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make_all_pins_virtual
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@@ -1 +1 @@
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Wed Sep 11 00:18:22 2019
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Thu Mar 05 06:08:03 2020
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@@ -1,3 +1,4 @@
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load_package flow
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package require cmdline
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set options { \
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@@ -7,6 +8,7 @@ set options { \
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{ "top.arg" "" "Top level module" } \
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{ "sdc.arg" "" "Timing Design Constraints file" } \
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{ "src.arg" "" "Verilog source file" } \
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{ "inc.arg" "." "Include path" } \
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}
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array set opts [::cmdline::getoptions quartus(args) $options]
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@@ -16,103 +18,24 @@ project_new $opts(project) -overwrite
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set_global_assignment -name FAMILY $opts(family)
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set_global_assignment -name DEVICE $opts(device)
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set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
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set_global_assignment -name SEARCH_PATH ../
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set_global_assignment -name VERILOG_FILE ../VX_define.v
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set_global_assignment -name VERILOG_FILE ../cache/cache_set.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_dram_req_rsp_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_wstall_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_join_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_data_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_exec_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpu_inst_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_lsu_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_exec_unit_req_inter.v
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set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
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set_global_assignment -name VERILOG_FILE ../cache/VX_generic_pe.v
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set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data_per_index.v
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set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data.v
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set_global_assignment -name VERILOG_FILE ../cache/VX_cache_bank_valid.v
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set_global_assignment -name VERILOG_FILE ../cache/VX_Cache_Bank.v
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set_global_assignment -name VERILOG_FILE ../cache/VX_d_cache.v
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set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block.v
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set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v
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set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v
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set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v
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set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v
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set_global_assignment -name VERILOG_FILE ../compat/VX_mult.v
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set_global_assignment -name VERILOG_FILE ../VX_alu.v
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set_global_assignment -name VERILOG_FILE ../VX_back_end.v
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set_global_assignment -name VERILOG_FILE ../VX_context.v
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set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
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set_global_assignment -name VERILOG_FILE ../VX_decode.v
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set_global_assignment -name VERILOG_FILE ../VX_execute.v
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set_global_assignment -name VERILOG_FILE ../VX_fetch.v
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set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
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set_global_assignment -name VERILOG_FILE ../VX_front_end.v
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set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr_stage.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
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set_global_assignment -name VERILOG_FILE ../VX_inst_multiplex.v
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set_global_assignment -name VERILOG_FILE ../VX_memory.v
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set_global_assignment -name VERILOG_FILE ../VX_register_file.v
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set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
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set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
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set_global_assignment -name VERILOG_FILE ../VX_warp.v
|
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set_global_assignment -name VERILOG_FILE ../VX_writeback.v
|
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set_global_assignment -name VERILOG_FILE ../VX_csr_wrapper.v
|
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set_global_assignment -name VERILOG_FILE ../VX_gpgpu_inst.v
|
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set_global_assignment -name VERILOG_FILE ../VX_execute_unit.v
|
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set_global_assignment -name VERILOG_FILE ../VX_lsu.v
|
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set_global_assignment -name VERILOG_FILE ../VX_scheduler.v
|
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set_global_assignment -name VERILOG_FILE ../VX_dmem_controller.v
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set_global_assignment -name VERILOG_FILE ../Vortex.v
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set_global_assignment -name SDC_FILE vortex.sdc
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
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set_global_assignment -name VERILOG_FILE $opts(src)
|
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set_global_assignment -name SEARCH_PATH $opts(inc)
|
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set_global_assignment -name SDC_FILE $opts(sdc)
|
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
|
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
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|
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proc make_all_pins_virtual {} {
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execute_module -tool map
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set name_ids [get_names -filter * -node_type pin]
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foreach_in_collection name_id $name_ids {
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set pin_name [get_name_info -info full_path $name_id]
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post_message "Making VIRTUAL_PIN assignment to $pin_name"
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set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
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}
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export_assignments
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}
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# set where [file dirname [info script]]
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# source [file join $where make_pins_virtual.tcl]
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project_close
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# set_global_assignment -name VERILOG_FILE $opts(src)
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make_all_pins_virtual
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|
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project_close
|
||||
@@ -1,4 +1,3 @@
|
||||
Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Shell
|
||||
Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
|
||||
@@ -15,13 +14,13 @@ Info: Running Quartus Prime Shell
|
||||
Info: the sole purpose of programming logic devices manufactured by
|
||||
Info: Intel and sold by Intel or its authorized distributors. Please
|
||||
Info: refer to the applicable agreement for further details.
|
||||
Info: Processing started: Wed Sep 11 00:18:22 2019
|
||||
Info: Command: quartus_sh --determine_smart_action VX_gpr_syn
|
||||
Info: Quartus(args): VX_gpr_syn
|
||||
Info: Processing started: Thu Mar 5 06:08:03 2020
|
||||
Info: Command: quartus_sh --determine_smart_action Vortex
|
||||
Info: Quartus(args): Vortex
|
||||
Info: SMART_ACTION = SOURCE
|
||||
Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful
|
||||
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 687 megabytes
|
||||
Info: Processing ended: Wed Sep 11 00:18:22 2019
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
Info: Peak virtual memory: 689 megabytes
|
||||
Info: Processing ended: Thu Mar 5 06:08:04 2020
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
load_package flow
|
||||
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
|
||||
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
|
||||
set_global_assignment -name SDC_FILE vortex.sdc
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
||||
# pins configuration
|
||||
package require cmdline
|
||||
|
||||
proc make_all_pins_virtual { args } {
|
||||
|
||||
set options {\
|
||||
{ "exclude.arg" "" "List of signals to exclude" } \
|
||||
}
|
||||
array set opts [::cmdline::getoptions quartus(args) $options]
|
||||
|
||||
remove_all_instance_assignments -name VIRTUAL_PIN
|
||||
execute_module -tool map
|
||||
set name_ids [get_names -filter * -node_type pin]
|
||||
|
||||
foreach_in_collection name_id $name_ids {
|
||||
set pin_name [get_name_info -info full_path $name_id]
|
||||
|
||||
if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
|
||||
post_message "Making VIRTUAL_PIN assignment to $pin_name"
|
||||
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
|
||||
} else {
|
||||
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
|
||||
}
|
||||
}
|
||||
export_assignments
|
||||
}
|
||||
|
||||
|
||||
make_all_pins_virtual -exclude { clk, reset }
|
||||
@@ -1,6 +1,6 @@
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
|
||||
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
|
||||
|
||||
derive_pll_clocks -create_base_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
Reference in New Issue
Block a user