synthesis fixes
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2
rtl/cache/VX_Cache_Bank.v
vendored
2
rtl/cache/VX_Cache_Bank.v
vendored
@@ -3,8 +3,6 @@
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// Also make sure all possible output states are transmitted back to the bank correctly
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`include "VX_define.v"
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// `include "VX_cache_data.v"
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module VX_Cache_Bank
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#(
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