synthesis fixes
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@@ -1,4 +1,3 @@
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`include "VX_define.v"
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module VX_dmem_controller (
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@@ -16,23 +15,19 @@ module VX_dmem_controller (
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VX_gpu_dcache_res_inter VX_dcache_rsp
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);
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wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF;
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wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}};
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wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}};
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wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read;
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wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write;
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wire[`NT_M1:0][31:0] cache_driver_out_data;
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wire[`NT_M1:0][31:0] sm_driver_out_data;
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wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
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wire sm_delay;
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// I_Cache Signals
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wire[31:0] icache_instruction_out;
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@@ -169,7 +164,7 @@ module VX_dmem_controller (
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// );
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VX_d_cache#(
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VX_d_cache #(
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.CACHE_SIZE (`ICACHE_SIZE),
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.CACHE_WAYS (`ICACHE_WAYS),
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.CACHE_BLOCK (`ICACHE_BLOCK),
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