buffering core reset signal

2021-01-01 11:46:30 -08:00
parent 138db29310
commit 36602cfa6a
2 changed files with 37 additions and 12 deletions
--- a/hw/rtl/VX_cluster.v
+++ b/hw/rtl/VX_cluster.v
@@ -68,13 +68,19 @@ module VX_cluster #(
    wire [`NUM_CORES-1:0]                        per_core_ebreak;

    for (genvar i = 0; i < `NUM_CORES; i++) begin    
+    
+        reg core_reset;
+        always @(posedge clk) begin
+            core_reset <= reset;
+        end
+
        VX_core #(
            .CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
        ) core (
            `SCOPE_BIND_VX_cluster_core(i)

            .clk            (clk),
-            .reset          (reset),
+            .reset          (core_reset),

            .dram_req_valid (per_core_dram_req_valid[i]),
            .dram_req_rw    (per_core_dram_req_rw   [i]),