diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v
index f06fa702..274bc8e3 100644
--- a/hw/rtl/VX_cluster.v
+++ b/hw/rtl/VX_cluster.v
@@ -68,13 +68,19 @@ module VX_cluster #(
     wire [`NUM_CORES-1:0]                        per_core_ebreak;
 
     for (genvar i = 0; i < `NUM_CORES; i++) begin    
+    
+        reg core_reset;
+        always @(posedge clk) begin
+            core_reset <= reset;
+        end
+
         VX_core #(
             .CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
         ) core (
             `SCOPE_BIND_VX_cluster_core(i)
 
             .clk            (clk),
-            .reset          (reset),
+            .reset          (core_reset),
 
             .dram_req_valid (per_core_dram_req_valid[i]),
             .dram_req_rw    (per_core_dram_req_rw   [i]),                
diff --git a/hw/rtl/libs/VX_pipe_register.v b/hw/rtl/libs/VX_pipe_register.v
index 60a52d7c..d1f12d1f 100644
--- a/hw/rtl/libs/VX_pipe_register.v
+++ b/hw/rtl/libs/VX_pipe_register.v
@@ -18,24 +18,43 @@ module VX_pipe_register #(
         `UNUSED_VAR (enable)
         assign data_out = data_in;  
     end else if (DEPTH == 1) begin   
-        reg [DATAW-1:0] value;
-        if (RESETW != 0) begin
-            always @(posedge clk) begin
-                if (reset) begin
-                    value[DATAW-1:DATAW-RESETW] <= RESETW'(0);
-                end else if (enable) begin
-                    value <= data_in;
-                end
-            end
-        end else begin
+        if (RESETW == 0) begin
             `UNUSED_VAR (reset)
+            reg [DATAW-1:0] value;
+
             always @(posedge clk) begin
                 if (enable) begin
                     value <= data_in;
                 end
             end
+            assign data_out = value;
+        end else if (RESETW == DATAW) begin
+            reg [DATAW-1:0] value;
+
+            always @(posedge clk) begin
+                if (reset) begin
+                    value <= RESETW'(0);
+                end else if (enable) begin
+                    value <= data_in;
+                end
+            end
+            assign data_out = value;
+        end else begin            
+            reg [DATAW-RESETW-1:0] value_d;
+            reg [RESETW-1:0]       value_r;
+
+            always @(posedge clk) begin
+                if (reset) begin
+                    value_r <= RESETW'(0);
+                end else if (enable) begin
+                    value_r <= data_in[DATAW-1:DATAW-RESETW];
+                end
+                if (enable) begin
+                    value_d <= data_in[DATAW-RESETW-1:0];
+                end
+            end        
+            assign data_out = {value_r, value_d};
         end
-        assign data_out = value;
     end else begin
         VX_shift_register #(
             .DATAW  (DATAW),