diff --git a/syn/dc_1GHz.log b/syn/dc_1GHz.log new file mode 100644 index 00000000..a2deb6df --- /dev/null +++ b/syn/dc_1GHz.log @@ -0,0 +1,726463 @@ + + Design Compiler Graphical + DC Ultra (TM) + DFTMAX (TM) + Power Compiler (TM) + DesignWare (R) + DC Expert (TM) + Design Vision (TM) + HDL Compiler (TM) + VHDL Compiler (TM) + DFT Compiler + Design Compiler(R) + + Version O-2018.06-SP3 for linux64 - Oct 18, 2018 + + Copyright (c) 1988 - 2018 Synopsys, Inc. + This software and the associated documentation are proprietary to Synopsys, + Inc. This software may only be used in accordance with the terms and conditions + of a written license agreement with Synopsys, Inc. All other use, reproduction, + or distribution of this software is strictly prohibited. +Initializing... +set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db] +/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db +set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb] +* sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb +set symbol_library {} +set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db] +sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v ] +VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v +# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v # ] +set top_level Vortex +Vortex +analyze -format sverilog $verilog_files +Running PRESTO HDLC +Compiling source file ../rtl/VX_countones.v +Compiling source file ../rtl/VX_priority_encoder_w_mask.v +Compiling source file ../rtl/interfaces/VX_dram_req_rsp_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_dram_req_rsp_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/cache/VX_Cache_Bank.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/cache/VX_cache_data.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/cache/VX_d_cache.v +Opening include file ../rtl/interfaces/../VX_define.v +Warning: ../rtl/cache/VX_d_cache.v:50: Parameter keyword used in local parameter declaration. (VER-329) +Compiling source file ../rtl/shared_memory/VX_bank_valids.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/shared_memory/VX_priority_encoder_sm.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/shared_memory/VX_shared_memory.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/shared_memory/VX_shared_memory_block.v +Compiling source file ../rtl/VX_dmem_controller.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_generic_priority_encoder.v +Compiling source file ../rtl/VX_generic_stack.v +Compiling source file ../rtl/interfaces/VX_join_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_join_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_csr_wrapper.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_csr_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_csr_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_csr_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_csr_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_gpgpu_inst.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_gpu_inst_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpu_inst_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_wstall_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_wstall_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_inst_exec_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_inst_exec_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_lsu.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_execute_unit.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_lsu_addr_gen.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_inst_multiplex.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_exec_unit_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_exec_unit_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_lsu_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_lsu_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_alu.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_back_end.v +Compiling source file ../rtl/VX_gpr_stage.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_gpr_data_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_data_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/VX_csr_handler.v +Compiling source file ../rtl/VX_decode.v +Opening include file ../rtl//VX_define.v +Warning: ../rtl/VX_csr_handler.v:34: The statements in initial blocks are ignored. (VER-281) +Compiling source file ../rtl/VX_define.v +Compiling source file ../rtl/VX_scheduler.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_fetch.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_front_end.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_generic_register.v +Compiling source file ../rtl/VX_gpr.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_gpr_wrapper.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_priority_encoder.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_warp_scheduler.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/VX_writeback.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/byte_enabled_simple_dual_port_ram.v +Opening include file ../rtl//VX_define.v +Compiling source file ../rtl/interfaces/VX_branch_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_branch_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_dcache_request_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_dcache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_dcache_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_dcache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_frE_to_bckE_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_frE_to_bckE_req_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_clone_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_clone_inter.v:9: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_jal_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_jal_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_read_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_read_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_gpr_wspawn_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_gpr_wspawn_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_icache_request_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_icache_request_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_icache_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_icache_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_inst_mem_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_inst_mem_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_inst_meta_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_inst_meta_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_jal_response_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_jal_response_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_mem_req_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_mem_req_inter.v:7: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_mw_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_mw_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_warp_ctl_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_warp_ctl_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/interfaces/VX_wb_inter.v +Opening include file ../rtl/interfaces/../VX_define.v +Information: ../rtl/interfaces/VX_wb_inter.v:8: List () of one, unnamed, port is ignored. (VER-988) +Compiling source file ../rtl/pipe_regs/VX_d_e_reg.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/pipe_regs/VX_f_d_reg.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/Vortex.v +Opening include file ../rtl/interfaces/../VX_define.v +Compiling source file ../rtl/cache/VX_cache_bank_valid.v +Opening include file ../rtl/interfaces/../VX_define.v +Presto compilation completed successfully. +Loading db file '/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb' +1 +elaborate Vortex +Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/gtech.db' +Loading db file '/tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/standard.sldb' + Loading link library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c' + Loading link library 'USERLIB_ss_0p81v_0p81v_m40c' + Loading link library 'USERLIB_ss_0p81v_0p81v_m40c' + Loading link library 'USERLIB_ss_0p81v_0p81v_m40c' + Loading link library 'USERLIB_ss_0p81v_0p81v_m40c' + Loading link library 'gtech' +Running PRESTO HDLC +Presto compilation completed successfully. +Elaborated 1 design. +Current design is now 'Vortex'. +Information: Building the design 'VX_front_end' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%schedule_delay%)(N%icache_response_fe%I%WORK/VX_icache_response_inter%%)(N%icache_request_fe%I%WORK/VX_icache_request_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%fetch_ebreak%))". (HDL-193) +Presto compilation completed successfully. +Warning: Filename too long >255 chars. Renaming file: +'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__.mr' +to +'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FRONT_END_I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_ICACHE_RESPONSE_FE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_FE_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_35FE527370C98E3C09E2E6E2555D7EE6F02ECB4FA9775364_000.mr' +Information: Building the design 'VX_scheduler' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%memory_delay%)(N%gpr_stage_delay%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%schedule_delay%))". (HDL-193) + +Inferred memory devices in process + in routine VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__ line 46 in file + '../rtl/VX_scheduler.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| rename_table_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +================================================================================================================================ +| block name/line | Inputs | Outputs | # sel inputs | +================================================================================================================================ +| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/28 | 32 | 1 | 5 | +| VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__/29 | 32 | 1 | 5 | +================================================================================================================================ +Presto compilation completed successfully. +Information: Building the design 'VX_back_end' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_mem_delay%)(N%gpr_stage_delay%))". (HDL-193) +Presto compilation completed successfully. +Warning: Filename too long >255 chars. Renaming file: +'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I_VX_DCACHE_RSP_VX_DCACHE_RESPONSE_INTER__I_VX_DCACHE_REQ_VX_DCACHE_REQUEST_INTER__.mr' +to +'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_BACK_END_I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_VX_BCKE_REQ_VX_FRE_TO_BCKE_REQ_INTER__I_VX_WRITEBACK_INTER_VX_WB_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__I__B458045CB598257C352A6473E41AFB0017DAE536C3121AF6_000.mr' +Information: Building the design 'VX_dmem_controller' instantiated from design 'Vortex' with + the parameters "|((N%clk%)(N%reset%)(N%VX_dram_req_rsp%I%WORK/VX_dram_req_rsp_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_fetch' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%)(N%schedule_delay%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%icache_response%I%WORK/VX_icache_response_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%)(N%icache_request%I%WORK/VX_icache_request_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%)(N%out_ebreak%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%))". (HDL-193) +Presto compilation completed successfully. +Warning: Filename too long >255 chars. Renaming file: +'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RSP_VX_BRANCH_RESPONSE_INTER__I_FE_INST_META_FD_VX_INST_META_INTER__I_VX_WARP_CTL_VX_WARP_CTL_INTER__.mr' +to +'/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/VX_FETCH_I_VX_WSTALL_VX_WSTALL_INTER__I_VX_JOIN_VX_JOIN_INTER__I_ICACHE_RESPONSE_VX_ICACHE_RESPONSE_INTER__I_ICACHE_REQUEST_VX_ICACHE_REQUEST_INTER__I_VX_JAL_RSP_VX_JAL_RESPONSE_INTER__I_VX_BRANCH_RS_86A42238AAF2AFE24C53E826055B694A355B7E541802DCF6_000.mr' +Information: Building the design 'VX_f_d_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%in_freeze%)(N%fe_inst_meta_fd%I%WORK/VX_inst_meta_inter%%)(N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_decode' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%fd_inst_meta_de%I%WORK/VX_inst_meta_inter%%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_wstall%I%WORK/VX_wstall_inter%%)(N%VX_join%I%WORK/VX_join_inter%%))". (HDL-193) +Warning: ../rtl/VX_decode.v:152: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_decode.v:300: DEFAULT branch of CASE statement cannot be reached. (ELAB-311) +Warning: ../rtl/VX_decode.v:315: DEFAULT branch of CASE statement cannot be reached. (ELAB-311) + +Statistics for case statements in always block at line 159 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 160 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 190 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 191 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 244 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 245 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 258 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 259 | auto/auto | +| 264 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 298 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 300 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 313 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 315 | auto/auto | +=============================================== + +Statistics for case statements in always block at line 330 in file + '../rtl/VX_decode.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 331 | auto/auto | +=============================================== +Presto compilation completed successfully. +Information: Building the design 'VX_d_e_reg' instantiated from design 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%in_branch_stall%)(N%in_freeze%)(N%VX_frE_to_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_mw_wb_inter'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_mem_req_inter'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_gpr_stage' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%schedule_delay%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%memory_delay%)(N%gpr_stage_delay%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_lsu' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_dcache_rsp%I%WORK/VX_dcache_response_inter%%)(N%VX_dcache_req%I%WORK/VX_dcache_request_inter%%)(N%out_delay%)(N%no_slot_mem%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_execute_unit' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_jal_rsp%I%WORK/VX_jal_response_inter%%)(N%VX_branch_rsp%I%WORK/VX_branch_response_inter%%))". (HDL-193) +Warning: ../rtl/VX_execute_unit.v:107: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_execute_unit.v:114: signed to unsigned assignment occurs. (VER-318) + +Statistics for case statements in always block at line 74 in file + '../rtl/VX_execute_unit.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 76 | auto/auto | +=============================================== +Statistics for MUX_OPs +=========================================================================================================================================================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | +=========================================================================================================================================================================================================================== +| VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__/71 | 4 | 32 | 2 | +=========================================================================================================================================================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_gpgpu_inst' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_warp_ctl%I%WORK/VX_warp_ctl_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_csr_wrapper' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_csr_req%I%WORK/VX_csr_req_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_writeback' instantiated from design 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' with + the parameters "|((N%VX_mem_wb%I%WORK/VX_inst_mem_wb_inter%%)(N%VX_inst_exec_wb%I%WORK/VX_inst_exec_wb_inter%%)(N%VX_csr_wb%I%WORK/VX_csr_wb_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%no_slot_mem%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_shared_memory' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with + the parameters "NB=7,BITS_PER_BANK=3". (HDL-193) + +Inferred memory devices in process + in routine VX_shared_memory_NB7_BITS_PER_BANK3 line 86 in file + '../rtl/shared_memory/VX_shared_memory.v'. +=========================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=========================================================================== +| temp_out_data_reg | Latch | 128 | Y | N | N | N | - | - | - | +| shm_write_reg | Latch | 1 | N | N | N | N | - | - | - | +| temp_out_valid_reg | Latch | 4 | Y | N | N | N | - | - | - | +=========================================================================== +Statistics for MUX_OPs +============================================================================= +| block name/line | Inputs | Outputs | # sel inputs | +============================================================================= +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +| VX_shared_memory_NB7_BITS_PER_BANK3/122 | 4 | 32 | 2 | +============================================================================= +Presto compilation completed successfully. +Information: Building the design 'VX_d_cache' instantiated from design 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' with + the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_REQ=4". (HDL-193) +Warning: ../rtl/cache/VX_d_cache.v:208: signed to unsigned assignment occurs. (VER-318) + +Inferred memory devices in process + in routine VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4 line 219 in file + '../rtl/cache/VX_d_cache.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| evict_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +| final_data_read_reg | Flip-flop | 128 | Y | N | Y | N | N | N | N | +| state_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| stored_valid_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +| miss_addr_reg | Flip-flop | 29 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +==================================================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | +==================================================================================================================== +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/240 | 8 | 2 | 3 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/240 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/241 | 8 | 29 | 3 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/253 | 4 | 29 | 2 | +| VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4/275 | 4 | 32 | 2 | +==================================================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_warp_scheduler'. (HDL-193) + +Inferred memory devices in process + in routine VX_warp_scheduler line 113 in file + '../rtl/VX_warp_scheduler.v'. +================================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +================================================================================== +| thread_masks_reg | Flip-flop | 24 | Y | N | Y | N | N | N | N | +| thread_masks_reg | Flip-flop | 8 | Y | N | N | Y | N | N | N | +| warp_stalled_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| barrier_stall_mask_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| use_wsapwn_pc_reg | Flip-flop | 32 | Y | N | Y | N | N | N | N | +| use_wsapwn_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 227 | Y | N | Y | N | N | N | N | +| warp_pcs_reg | Flip-flop | 29 | Y | N | N | Y | N | N | N | +| warp_active_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N | +| warp_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N | +| visible_active_reg | Flip-flop | 7 | Y | N | Y | N | N | N | N | +| visible_active_reg | Flip-flop | 1 | N | N | N | Y | N | N | N | +================================================================================== +Statistics for MUX_OPs +=========================================================== +| block name/line | Inputs | Outputs | # sel inputs | +=========================================================== +| VX_warp_scheduler/215 | 4 | 8 | 2 | +| VX_warp_scheduler/233 | 8 | 4 | 3 | +| VX_warp_scheduler/237 | 8 | 37 | 3 | +| VX_warp_scheduler/266 | 8 | 3 | 3 | +| VX_warp_scheduler/273 | 8 | 32 | 3 | +| VX_warp_scheduler/274 | 8 | 4 | 3 | +=========================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' with + the parameters "N=71". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N71 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 71 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' with + the parameters "N=240". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N240 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 240 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_gpr_wrapper' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_gpr_jal%I%WORK/VX_gpr_jal_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193) +Statistics for MUX_OPs +========================================================================================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | +========================================================================================================================================================== +| VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__/25 | 8 | 256 | 3 | +========================================================================================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_inst_multiplex' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "|((N%VX_bckE_req%I%WORK/VX_frE_to_bckE_req_inter%%)(N%VX_gpr_data%I%WORK/VX_gpr_data_inter%%)(N%VX_exec_unit_req%I%WORK/VX_exec_unit_req_inter%%)(N%VX_lsu_req%I%WORK/VX_lsu_req_inter%%)(N%VX_gpu_inst_req%I%WORK/VX_gpu_inst_req_inter%%)(N%VX_csr_req%I%WORK/VX_csr_req_inter%%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=308". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N308 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 308 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=487". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N487 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 487 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=203". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N203 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 203 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_register' instantiated from design 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' with + the parameters "N=60". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_register_N60 line 21 in file + '../rtl/VX_generic_register.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| value_reg | Flip-flop | 60 | Y | N | Y | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_lsu_addr_gen'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_alu'. (HDL-193) +Warning: ../rtl/VX_alu.v:40: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:49: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:50: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:56: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:61: signed to unsigned assignment occurs. (VER-318) +Warning: ../rtl/VX_alu.v:66: signed to unsigned conversion occurs. (VER-318) +Warning: ../rtl/VX_alu.v:68: signed to unsigned conversion occurs. (VER-318) + +Statistics for case statements in always block at line 47 in file + '../rtl/VX_alu.v' +=============================================== +| Line | full/ parallel | +=============================================== +| 48 | auto/auto | +=============================================== +Presto compilation completed successfully. +Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' with + the parameters "N=4". (HDL-193) +Warning: ../rtl/VX_generic_priority_encoder.v:17: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_countones' instantiated from design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' with + the parameters "N=4". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_priority_encoder_sm' instantiated from design 'VX_shared_memory_NB7_BITS_PER_BANK3' with + the parameters "NB=7,BITS_PER_BANK=3". (HDL-193) + +Inferred memory devices in process + in routine VX_priority_encoder_sm_NB7_BITS_PER_BANK3 line 104 in file + '../rtl/shared_memory/VX_priority_encoder_sm.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| left_requests_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | +=============================================================================== +Statistics for MUX_OPs +================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | +================================================================================== +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +| VX_priority_encoder_sm_NB7_BITS_PER_BANK3/81 | 4 | 64 | 2 | +================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_shared_memory_block'. (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_cache_bank_valid' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with + the parameters "NUMBER_BANKS=8". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_priority_encoder_w_mask' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with + the parameters "N=4". (HDL-193) +Warning: ../rtl/VX_priority_encoder_w_mask.v:19: signed to unsigned part selection occurs. (VER-318) +Warning: ../rtl/VX_priority_encoder_w_mask.v:27: signed to unsigned assignment occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_generic_priority_encoder' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with + the parameters "N=8". (HDL-193) +Warning: ../rtl/VX_generic_priority_encoder.v:17: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_Cache_Bank' instantiated from design 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' with + the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8". (HDL-193) +Statistics for MUX_OPs +============================================================================================================== +| block name/line | Inputs | Outputs | # sel inputs | +============================================================================================================== +| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 32 | 2 | +| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 24 | 2 | +| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 16 | 2 | +| VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8/130 | 4 | 8 | 2 | +============================================================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_countones' instantiated from design 'VX_warp_scheduler' with + the parameters "N=8". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_generic_stack' instantiated from design 'VX_warp_scheduler' with + the parameters "WIDTH=37,DEPTH=2". (HDL-193) + +Inferred memory devices in process + in routine VX_generic_stack_WIDTH37_DEPTH2 line 21 in file + '../rtl/VX_generic_stack.v'. +=============================================================================== +| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | +=============================================================================== +| stack_reg | Flip-flop | 111 | Y | N | N | N | N | N | N | +| ptr_reg | Flip-flop | 2 | Y | N | N | N | N | N | N | +=============================================================================== +Presto compilation completed successfully. +Information: Building the design 'VX_priority_encoder'. (HDL-193) +Warning: ../rtl/VX_priority_encoder.v:15: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_gpr' instantiated from design 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' with + the parameters "|((N%clk%)(N%reset%)(N%valid_write_request%)(N%VX_gpr_read%I%WORK/VX_gpr_read_inter%%)(N%VX_writeback_inter%I%WORK/VX_wb_inter%%)(N%out_a_reg_data%)(N%out_b_reg_data%))". (HDL-193) +Presto compilation completed successfully. +Information: Building the design 'VX_bank_valids' instantiated from design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' with + the parameters "NB=7,BITS_PER_BANK=3". (HDL-193) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Warning: ../rtl/shared_memory/VX_bank_valids.v:21: signed to unsigned part selection occurs. (VER-318) +Presto compilation completed successfully. +Information: Building the design 'VX_cache_data' instantiated from design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8' with + the parameters "CACHE_SIZE=4096,CACHE_WAYS=1,CACHE_BLOCK=128,CACHE_BANKS=8,NUM_WORDS_PER_BLOCK=4". (HDL-193) +Presto compilation completed successfully. +1 +link + + Linking design 'Vortex' + Using the following designs and libraries: + -------------------------------------------------------------------------- + * (44 designs) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/Vortex.db, etc + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (library) /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db + USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db + USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db + USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db + USERLIB_ss_0p81v_0p81v_m40c (library) /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db + dw_foundation.sldb (library) /tools/synopsys/synthesis/syn/O-2018.06-SP3/libraries/syn/dw_foundation.sldb + +1 +set clk_freq 1000 +1000 +set clk_period [expr 1000.0 / $clk_freq / 1.0] +1.0 +create_clock [get_ports clk] -period $clk_period +1 +set_max_fanout 20 [get_ports clk] +1 +set_ideal_network [get_ports clk] +1 +set_max_fanout 20 [get_ports reset] +1 +set_false_path -from [get_ports reset] +1 +# set_register_merging Vortex FALSE +# set compile_seqmap_propagate_constants false +# set compile_seqmap_propagate_high_effort false +compile_ultra -no_autoungroup +Information: Performing power optimization. (PWR-850) +Alib files are up-to-date. +Information: Evaluating DesignWare library utilization. (UISN-27) + +============================================================================ +| DesignWare Building Block Library | Version | Available | +============================================================================ +| Basic DW Building Blocks | O-2018.06-DWBB_201806.3 | * | +| Licensed DW Building Blocks | O-2018.06-DWBB_201806.3 | * | +============================================================================ + +Information: Sequential output inversion is enabled. SVF file must be used for formal verification. (OPT-1208) + +Information: There are 8963 potential problems in your design. Please run 'check_design' for more information. (LINT-99) + +Information: Uniquified 4 instances of design 'VX_alu'. (OPT-1056) +Information: Uniquified 9 instances of design 'VX_generic_priority_encoder_N4'. (OPT-1056) +Information: Uniquified 9 instances of design 'VX_countones_N4'. (OPT-1056) +Information: Uniquified 8 instances of design 'VX_shared_memory_block'. (OPT-1056) +Information: Uniquified 8 instances of design 'VX_priority_encoder_w_mask_N4'. (OPT-1056) +Information: Uniquified 8 instances of design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8'. (OPT-1056) +Information: Uniquified 2 instances of design 'VX_countones_N8'. (OPT-1056) +Information: Uniquified 8 instances of design 'VX_generic_stack_WIDTH37_DEPTH2'. (OPT-1056) +Information: Uniquified 8 instances of design 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__'. (OPT-1056) +Information: Uniquified 8 instances of design 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4'. (OPT-1056) + Simplifying Design 'Vortex' + +Loaded alib file './alib-52/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db.alib' +Information: State dependent leakage is now switched from on to off. + + Beginning Pass 1 Mapping + ------------------------ + Processing 'VX_shared_memory_NB7_BITS_PER_BANK3' + Processing 'VX_d_cache_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_REQ4' +Information: The register 'state_reg[2]' is a constant and will be removed. (OPT-1206) +Information: The register 'state_reg[3]' is a constant and will be removed. (OPT-1206) +Information: The register 'evict_addr_reg[0]' is a constant and will be removed. (OPT-1206) +Information: The register 'evict_addr_reg[1]' is a constant and will be removed. (OPT-1206) +Information: The register 'evict_addr_reg[5]' is a constant and will be removed. (OPT-1206) +Information: The register 'evict_addr_reg[6]' is a constant and will be removed. (OPT-1206) + Processing 'VX_warp_scheduler' +Information: Added key list 'DesignWare' to design 'VX_warp_scheduler'. (DDB-72) +Information: The register 'use_wsapwn_reg[0]' is a constant and will be removed. (OPT-1206) + Implement Synthetic for 'VX_warp_scheduler'. + Processing 'Vortex' + Processing 'VX_generic_register_N487' + Processing 'VX_gpr_wrapper_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_gpr_jal_VX_gpr_jal_inter__' + Processing 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__' + Implement Synthetic for 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__'. + Processing 'VX_gpr_I_VX_gpr_read_VX_gpr_read_inter__I_VX_writeback_inter_VX_wb_inter___0' + Processing 'VX_writeback_I_VX_mem_wb_VX_inst_mem_wb_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_csr_wb_VX_csr_wb_inter__I_VX_writeback_inter_VX_wb_inter__' + Processing 'VX_fetch_I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__I_icache_response_VX_icache_response_inter__I_icache_request_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_fe_inst_meta_fd_VX_inst_meta_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' + Processing 'VX_alu_0' + Implement Synthetic for 'VX_alu_0'. + Processing 'VX_alu_0_DW_div_uns_J8_0' + Processing 'VX_alu_0_DW_div_tc_J8_0' + Processing 'VX_alu_0_DW01_absval_J8_0' + Processing 'VX_alu_0_DW01_inc_J8_0' + Processing 'VX_alu_0_DW_div_uns_J8_1' + Processing 'VX_alu_0_DW_div_tc_J8_1' + Processing 'VX_alu_0_DW01_absval_J8_1' + Processing 'VX_alu_0_DW01_inc_J8_1' +Information: Added key list 'DesignWare' to design 'VX_alu_0'. (DDB-72) + Processing 'VX_generic_register_N71' + Processing 'VX_bank_valids_NB7_BITS_PER_BANK3' + Processing 'VX_generic_register_N308' + Processing 'VX_lsu_addr_gen' + Implement Synthetic for 'VX_lsu_addr_gen'. + Processing 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3' +Information: Added key list 'DesignWare' to design 'VX_priority_encoder_sm_NB7_BITS_PER_BANK3'. (DDB-72) + Processing 'VX_priority_encoder_w_mask_N4_0' +Information: Added key list 'DesignWare' to design 'VX_priority_encoder_w_mask_N4_0'. (DDB-72) + Processing 'VX_dmem_controller_I_VX_dram_req_rsp_VX_dram_req_rsp_inter__I_VX_dcache_req_VX_dcache_request_inter__I_VX_dcache_rsp_VX_dcache_response_inter__' + Processing 'VX_shared_memory_block_0' + Processing 'VX_priority_encoder' + Processing 'VX_generic_priority_encoder_N4_8' + Processing 'VX_generic_register_N203' + Processing 'VX_scheduler_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__' + Processing 'VX_d_e_reg_I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' + Processing 'VX_countones_N4_0' +Information: Added key list 'DesignWare' to design 'VX_countones_N4_0'. (DDB-72) + Processing 'VX_gpr_stage_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' + Processing 'VX_cache_bank_valid_NUMBER_BANKS8' + Processing 'VX_generic_stack_WIDTH37_DEPTH2_0' +Information: Added key list 'DesignWare' to design 'VX_generic_stack_WIDTH37_DEPTH2_0'. (DDB-72) + Processing 'VX_front_end_I_VX_warp_ctl_VX_warp_ctl_inter__I_icache_response_fe_VX_icache_response_inter__I_icache_request_fe_VX_icache_request_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__' + Processing 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__' +Information: Added key list 'DesignWare' to design 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. (DDB-72) + Implement Synthetic for 'VX_gpgpu_inst_I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_warp_ctl_VX_warp_ctl_inter__'. + Processing 'VX_inst_multiplex_I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_gpr_data_VX_gpr_data_inter__I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_lsu_req_VX_lsu_req_inter__I_VX_gpu_inst_req_VX_gpu_inst_req_inter__I_VX_csr_req_VX_csr_req_inter__' + Processing 'VX_generic_priority_encoder_N4_0' + Processing 'VX_generic_register_N240' +Information: The register 'value_reg[192]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[193]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[194]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[195]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[196]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[197]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[198]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[199]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[200]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[201]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[202]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[203]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[204]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[205]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[206]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[207]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[208]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[209]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[210]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[211]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[212]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[213]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[214]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[215]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[216]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[217]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[218]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[219]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[220]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[221]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[222]' is a constant and will be removed. (OPT-1206) +Information: The register 'value_reg[223]' is a constant and will be removed. (OPT-1206) + Processing 'VX_cache_data_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_NUM_WORDS_PER_BLOCK4_0' + Processing 'VX_generic_priority_encoder_N8' + Processing 'VX_csr_wrapper_I_VX_csr_req_VX_csr_req_inter__I_VX_csr_wb_VX_csr_wb_inter__' + Processing 'VX_back_end_I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__I_VX_bckE_req_VX_frE_to_bckE_req_inter__I_VX_writeback_inter_VX_wb_inter__I_VX_warp_ctl_VX_warp_ctl_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' + Processing 'VX_lsu_I_VX_lsu_req_VX_lsu_req_inter__I_VX_mem_wb_VX_inst_mem_wb_inter__I_VX_dcache_rsp_VX_dcache_response_inter__I_VX_dcache_req_VX_dcache_request_inter__' + Processing 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_0' +Information: Added key list 'DesignWare' to design 'VX_Cache_Bank_CACHE_SIZE4096_CACHE_WAYS1_CACHE_BLOCK128_CACHE_BANKS8_0'. (DDB-72) + Processing 'VX_decode_I_fd_inst_meta_de_VX_inst_meta_inter__I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__' +Information: Added key list 'DesignWare' to design 'VX_decode_I_fd_inst_meta_de_VX_inst_meta_inter__I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__'. (DDB-72) + Implement Synthetic for 'VX_decode_I_fd_inst_meta_de_VX_inst_meta_inter__I_VX_frE_to_bckE_req_VX_frE_to_bckE_req_inter__I_VX_wstall_VX_wstall_inter__I_VX_join_VX_join_inter__'. + Processing 'VX_generic_register_N60' + Processing 'VX_f_d_reg_I_fe_inst_meta_fd_VX_inst_meta_inter__I_fd_inst_meta_de_VX_inst_meta_inter__' + Processing 'VX_countones_N8_0' + Implement Synthetic for 'VX_countones_N8_0'. +Information: Added key list 'DesignWare' to design 'VX_countones_N8_0'. (DDB-72) + + Updating timing information +Information: Updating design information... (UID-85) +Information: The library cell 'TIELO_X1M_A12TUL_C35' in the library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c' is not characterized for internal power. (PWR-536) +Information: The library cell 'TIEHI_X1M_A12TUL_C35' in the library 'sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c' is not characterized for internal power. (PWR-536) +Information: The target library(s) contains cell(s), other than black boxes, that are not characterized for internal power. (PWR-24) +Information: The register 'schedule/rename_table_reg[0]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[0]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[1]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[2]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[3]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/csr_reg/value_reg[31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[0].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[7].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[6].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[4].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[5].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[3].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[2].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_front_end/vx_fetch/warp_scheduler/genblk1[1].ipdom_stack/stack_reg[0][4]' is a constant and will be removed. (OPT-1206) + + Beginning Mapping Optimizations (Ultra High effort) + ------------------------------- + Structuring 'VX_alu_3_DW_div_uns_0' + Mapping 'VX_alu_3_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_0' + Mapping 'VX_alu_3_DW01_add_1' + Mapping 'VX_alu_3_DW01_add_2' + Mapping 'VX_alu_3_DW01_add_3' + Mapping 'VX_alu_3_DW01_add_4' + Mapping 'VX_alu_3_DW01_add_5' + Mapping 'VX_alu_3_DW01_add_6' + Mapping 'VX_alu_3_DW01_add_7' + Mapping 'VX_alu_3_DW01_add_8' + Mapping 'VX_alu_3_DW01_add_9' + Mapping 'VX_alu_3_DW01_add_10' + Mapping 'VX_alu_3_DW01_add_11' + Mapping 'VX_alu_3_DW01_add_12' + Mapping 'VX_alu_3_DW01_add_13' + Mapping 'VX_alu_3_DW01_add_14' + Mapping 'VX_alu_3_DW01_add_15' + Mapping 'VX_alu_3_DW01_add_16' + Mapping 'VX_alu_3_DW01_add_17' + Mapping 'VX_alu_3_DW01_add_18' + Mapping 'VX_alu_3_DW01_add_19' + Mapping 'VX_alu_3_DW01_add_20' + Mapping 'VX_alu_3_DW01_add_21' + Mapping 'VX_alu_3_DW01_add_22' + Mapping 'VX_alu_3_DW01_add_23' + Mapping 'VX_alu_3_DW01_add_24' + Mapping 'VX_alu_3_DW01_add_25' + Mapping 'VX_alu_3_DW01_add_26' + Structuring 'VX_alu_3_DW_div_uns_1' + Mapping 'VX_alu_3_DW_div_uns_1' + Mapping 'VX_alu_3_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_28' + Mapping 'VX_alu_3_DW01_add_29' + Mapping 'VX_alu_3_DW01_add_30' + Mapping 'VX_alu_3_DW01_add_31' + Mapping 'VX_alu_3_DW01_add_32' + Mapping 'VX_alu_3_DW01_add_33' + Mapping 'VX_alu_3_DW01_add_34' + Mapping 'VX_alu_3_DW01_add_35' + Mapping 'VX_alu_3_DW01_add_36' + Mapping 'VX_alu_3_DW01_add_37' + Mapping 'VX_alu_3_DW01_add_38' + Mapping 'VX_alu_3_DW01_add_39' + Mapping 'VX_alu_3_DW01_add_40' + Mapping 'VX_alu_3_DW01_add_41' + Mapping 'VX_alu_3_DW01_add_42' + Mapping 'VX_alu_3_DW01_add_43' + Mapping 'VX_alu_3_DW01_add_44' + Mapping 'VX_alu_3_DW01_add_45' + Mapping 'VX_alu_3_DW01_add_46' + Mapping 'VX_alu_3_DW01_add_47' + Mapping 'VX_alu_3_DW01_add_48' + Mapping 'VX_alu_3_DW01_add_49' + Mapping 'VX_alu_3_DW01_add_50' + Mapping 'VX_alu_3_DW01_add_51' + Mapping 'VX_alu_3_DW01_add_52' + Mapping 'VX_alu_3_DW01_add_53' + Mapping 'VX_alu_3_DW01_add_54' + Mapping 'VX_alu_3_DW01_add_55' + Mapping 'VX_alu_3_DW01_add_56' + Mapping 'VX_alu_3_DW01_add_57' + Mapping 'VX_alu_3_DW01_add_58' + Mapping 'VX_alu_3_DW01_add_59' + Mapping 'VX_alu_3_DW01_add_60' + Mapping 'VX_alu_3_DW01_add_61' + Mapping 'VX_alu_3_DW01_add_62' + Mapping 'VX_alu_3_DW01_add_63' + Mapping 'VX_alu_3_DW01_add_64' + Mapping 'VX_alu_3_DW01_add_65' + Mapping 'VX_alu_3_DW01_add_66' + Structuring 'VX_alu_3_DW_div_uns_2' + Mapping 'VX_alu_3_DW_div_uns_2' + Mapping 'VX_alu_3_DW01_add_67' + Mapping 'VX_alu_3_DW01_add_68' + Mapping 'VX_alu_3_DW01_add_69' + Mapping 'VX_alu_3_DW01_sub_0' + Mapping 'VX_alu_3_DW01_add_70' + Mapping 'VX_alu_3_DW01_add_71' + Mapping 'VX_alu_3_DW01_add_72' + Mapping 'VX_alu_3_DW01_add_77' + Mapping 'VX_alu_3_DW01_add_78' + Mapping 'VX_alu_3_DW01_add_79' + Mapping 'VX_alu_3_DW01_add_80' + Mapping 'VX_alu_3_DW01_add_81' + Mapping 'VX_alu_3_DW01_add_82' + Mapping 'VX_alu_3_DW01_add_83' + Mapping 'VX_alu_3_DW01_add_84' + Mapping 'VX_alu_3_DW01_add_85' + Mapping 'VX_alu_3_DW01_add_86' + Mapping 'VX_alu_3_DW01_add_87' + Mapping 'VX_alu_3_DW01_add_88' + Mapping 'VX_alu_3_DW01_add_89' + Mapping 'VX_alu_3_DW01_add_90' + Mapping 'VX_alu_3_DW01_add_91' + Mapping 'VX_alu_3_DW01_add_92' + Mapping 'VX_alu_3_DW01_add_93' + Mapping 'VX_alu_3_DW01_add_94' + Mapping 'VX_alu_3_DW01_add_95' + Mapping 'VX_alu_3_DW01_add_96' + Mapping 'VX_alu_3_DW01_add_97' + Mapping 'VX_alu_3_DW01_add_98' + Mapping 'VX_alu_3_DW01_add_99' + Mapping 'VX_alu_3_DW01_add_100' + Mapping 'VX_alu_3_DW01_add_101' + Mapping 'VX_alu_3_DW01_add_102' + Mapping 'VX_alu_3_DW01_add_103' + Mapping 'VX_alu_3_DW01_add_104' + Mapping 'VX_alu_3_DW01_add_105' + Mapping 'VX_alu_3_DW01_add_106' + Mapping 'VX_alu_3_DW01_add_107' + Mapping 'VX_alu_3_DW01_add_108' + Mapping 'VX_alu_3_DW01_add_109' + Mapping 'VX_alu_3_DW01_add_110' + Mapping 'VX_alu_3_DW01_add_111' + Mapping 'VX_alu_3_DW01_add_112' + Mapping 'VX_alu_3_DW01_add_113' + Mapping 'VX_alu_3_DW01_add_114' + Mapping 'VX_alu_3_DW01_add_115' + Mapping 'VX_alu_3_DW01_add_116' + Mapping 'VX_alu_3_DW01_add_117' + Mapping 'VX_alu_3_DW01_add_118' + Mapping 'VX_alu_3_DW01_add_119' + Mapping 'VX_alu_3_DW01_add_120' + Mapping 'VX_alu_3_DW01_add_121' + Mapping 'VX_alu_3_DW01_add_122' + Mapping 'VX_alu_3_DW01_add_123' + Mapping 'VX_alu_3_DW01_add_124' + Mapping 'VX_alu_3_DW01_add_125' + Mapping 'VX_alu_3_DW01_add_126' + Mapping 'VX_alu_3_DW01_add_127' + Mapping 'VX_alu_3_DW01_add_128' + Mapping 'VX_alu_3_DW01_add_129' + Mapping 'VX_alu_3_DW01_add_130' + Mapping 'VX_alu_3_DW01_add_131' + Mapping 'VX_alu_3_DW01_add_132' + Mapping 'VX_alu_3_DW01_add_133' + Mapping 'VX_alu_3_DW01_add_134' + Mapping 'VX_alu_3_DW01_add_135' + Mapping 'VX_alu_3_DW01_add_136' + Mapping 'VX_alu_3_DW01_add_137' + Mapping 'VX_alu_3_DW01_add_138' + Mapping 'VX_alu_3_DW01_add_139' + Mapping 'VX_alu_3_DW01_add_140' + Mapping 'VX_alu_3_DW01_add_141' + Mapping 'VX_alu_3_DW01_add_142' + Mapping 'VX_alu_3_DW01_add_143' + Mapping 'VX_alu_3_DW01_add_144' + Mapping 'VX_alu_3_DW01_add_145' + Mapping 'VX_alu_3_DW01_add_146' + Structuring 'VX_alu_3_DW_div_tc_0' + Mapping 'VX_alu_3_DW_div_tc_0' + Structuring 'VX_alu_3_DW01_absval_0' + Mapping 'VX_alu_3_DW01_absval_0' + Structuring 'VX_alu_3_DW01_inc_0' + Mapping 'VX_alu_3_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_147' + Mapping 'VX_alu_3_DW01_add_148' + Mapping 'VX_alu_3_DW01_add_149' + Mapping 'VX_alu_3_DW01_add_150' + Mapping 'VX_alu_3_DW01_add_151' + Mapping 'VX_alu_3_DW01_add_152' + Mapping 'VX_alu_3_DW01_add_153' + Mapping 'VX_alu_3_DW01_add_154' + Mapping 'VX_alu_3_DW01_add_155' + Mapping 'VX_alu_3_DW01_add_156' + Mapping 'VX_alu_3_DW01_add_157' + Mapping 'VX_alu_3_DW01_add_158' + Mapping 'VX_alu_3_DW01_add_159' + Mapping 'VX_alu_3_DW01_add_160' + Mapping 'VX_alu_3_DW01_add_161' + Mapping 'VX_alu_3_DW01_add_162' + Mapping 'VX_alu_3_DW01_add_163' + Mapping 'VX_alu_3_DW01_add_164' + Mapping 'VX_alu_3_DW01_add_165' + Mapping 'VX_alu_3_DW01_add_166' + Mapping 'VX_alu_3_DW01_add_167' + Mapping 'VX_alu_3_DW01_add_168' + Mapping 'VX_alu_3_DW01_add_169' + Mapping 'VX_alu_3_DW01_add_170' + Mapping 'VX_alu_3_DW01_add_171' + Mapping 'VX_alu_3_DW01_add_172' + Mapping 'VX_alu_3_DW01_add_173' + Mapping 'VX_alu_3_DW_inc_1' + Structuring 'VX_alu_3_DW_div_tc_1' + Mapping 'VX_alu_3_DW_div_tc_1' + Structuring 'VX_alu_3_DW01_absval_1' + Mapping 'VX_alu_3_DW01_absval_1' + Structuring 'VX_alu_3_DW01_inc_1' + Mapping 'VX_alu_3_DW01_inc_1' + Mapping 'VX_alu_3_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_175' + Mapping 'VX_alu_3_DW01_add_176' + Mapping 'VX_alu_3_DW01_add_177' + Mapping 'VX_alu_3_DW01_add_178' + Mapping 'VX_alu_3_DW01_add_179' + Mapping 'VX_alu_3_DW01_add_180' + Mapping 'VX_alu_3_DW01_add_181' + Mapping 'VX_alu_3_DW01_add_182' + Mapping 'VX_alu_3_DW01_add_183' + Mapping 'VX_alu_3_DW01_add_184' + Mapping 'VX_alu_3_DW01_add_185' + Mapping 'VX_alu_3_DW01_add_186' + Mapping 'VX_alu_3_DW01_add_187' + Mapping 'VX_alu_3_DW01_add_188' + Mapping 'VX_alu_3_DW01_add_189' + Mapping 'VX_alu_3_DW01_add_190' + Mapping 'VX_alu_3_DW01_add_191' + Mapping 'VX_alu_3_DW01_add_192' + Mapping 'VX_alu_3_DW01_add_193' + Mapping 'VX_alu_3_DW01_add_194' + Mapping 'VX_alu_3_DW01_add_195' + Mapping 'VX_alu_3_DW01_add_196' + Mapping 'VX_alu_3_DW01_add_197' + Mapping 'VX_alu_3_DW01_add_198' + Mapping 'VX_alu_3_DW01_add_199' + Mapping 'VX_alu_3_DW01_add_200' + Mapping 'VX_alu_3_DW01_add_201' + Mapping 'VX_alu_3_DW01_add_202' + Mapping 'VX_alu_3_DW01_add_203' + Mapping 'VX_alu_3_DW01_add_204' + Mapping 'VX_alu_3_DW01_add_205' + Mapping 'VX_alu_3_DW01_add_206' + Mapping 'VX_alu_3_DW01_add_207' + Mapping 'VX_alu_3_DW01_add_208' + Mapping 'VX_alu_3_DW01_add_209' + Mapping 'VX_alu_3_DW01_add_210' + Mapping 'VX_alu_3_DW01_add_211' + Mapping 'VX_alu_3_DW01_add_212' + Mapping 'VX_alu_3_DW01_add_213' + Mapping 'VX_alu_3_DW_inc_3' + Structuring 'VX_alu_3_DW_div_tc_2' + Mapping 'VX_alu_3_DW_div_tc_2' + Structuring 'VX_alu_3_DW01_absval_2' + Mapping 'VX_alu_3_DW01_absval_2' + Structuring 'VX_alu_3_DW01_inc_2' + Mapping 'VX_alu_3_DW01_inc_2' + Mapping 'VX_alu_3_DW01_add_214' + Mapping 'VX_alu_3_DW01_add_215' + Mapping 'VX_alu_3_DW01_add_216' + Mapping 'VX_alu_3_DW01_sub_1' + Mapping 'VX_alu_3_DW01_add_217' + Mapping 'VX_alu_3_DW01_add_218' + Mapping 'VX_alu_3_DW01_add_219' + Mapping 'VX_alu_3_DW01_add_224' + Mapping 'VX_alu_3_DW01_add_225' + Mapping 'VX_alu_3_DW01_add_226' + Mapping 'VX_alu_3_DW01_add_227' + Mapping 'VX_alu_3_DW01_add_228' + Mapping 'VX_alu_3_DW01_add_229' + Mapping 'VX_alu_3_DW01_add_230' + Mapping 'VX_alu_3_DW01_add_231' + Mapping 'VX_alu_3_DW01_add_232' + Mapping 'VX_alu_3_DW01_add_233' + Mapping 'VX_alu_3_DW01_add_234' + Mapping 'VX_alu_3_DW01_add_235' + Mapping 'VX_alu_3_DW01_add_236' + Mapping 'VX_alu_3_DW01_add_237' + Mapping 'VX_alu_3_DW01_add_238' + Mapping 'VX_alu_3_DW01_add_239' + Mapping 'VX_alu_3_DW01_add_240' + Mapping 'VX_alu_3_DW01_add_241' + Mapping 'VX_alu_3_DW01_add_242' + Mapping 'VX_alu_3_DW01_add_243' + Mapping 'VX_alu_3_DW01_add_244' + Mapping 'VX_alu_3_DW01_add_245' + Mapping 'VX_alu_3_DW01_add_246' + Mapping 'VX_alu_3_DW01_add_247' + Mapping 'VX_alu_3_DW01_add_248' + Mapping 'VX_alu_3_DW01_add_249' + Mapping 'VX_alu_3_DW01_add_250' + Mapping 'VX_alu_3_DW01_add_251' + Mapping 'VX_alu_3_DW01_add_252' + Mapping 'VX_alu_3_DW01_add_253' + Mapping 'VX_alu_3_DW01_add_254' + Mapping 'VX_alu_3_DW01_add_255' + Mapping 'VX_alu_3_DW01_add_256' + Mapping 'VX_alu_3_DW01_add_257' + Mapping 'VX_alu_3_DW01_add_258' + Mapping 'VX_alu_3_DW01_add_259' + Mapping 'VX_alu_3_DW01_add_260' + Mapping 'VX_alu_3_DW01_add_261' + Mapping 'VX_alu_3_DW01_add_262' + Mapping 'VX_alu_3_DW01_add_263' + Mapping 'VX_alu_3_DW01_add_264' + Mapping 'VX_alu_3_DW01_add_265' + Mapping 'VX_alu_3_DW01_add_266' + Mapping 'VX_alu_3_DW01_add_267' + Mapping 'VX_alu_3_DW01_add_268' + Mapping 'VX_alu_3_DW01_add_269' + Mapping 'VX_alu_3_DW01_add_270' + Mapping 'VX_alu_3_DW01_add_271' + Mapping 'VX_alu_3_DW01_add_272' + Mapping 'VX_alu_3_DW01_add_273' + Mapping 'VX_alu_3_DW01_add_274' + Mapping 'VX_alu_3_DW01_add_275' + Mapping 'VX_alu_3_DW01_add_276' + Mapping 'VX_alu_3_DW01_add_277' + Mapping 'VX_alu_3_DW01_add_278' + Mapping 'VX_alu_3_DW01_add_279' + Mapping 'VX_alu_3_DW01_add_280' + Mapping 'VX_alu_3_DW01_add_281' + Mapping 'VX_alu_3_DW01_add_282' + Mapping 'VX_alu_3_DW01_add_283' + Mapping 'VX_alu_3_DW01_add_284' + Mapping 'VX_alu_3_DW01_add_285' + Mapping 'VX_alu_3_DW01_add_286' + Mapping 'VX_alu_3_DW01_add_287' + Mapping 'VX_alu_3_DW01_add_288' + Mapping 'VX_alu_3_DW01_add_289' + Mapping 'VX_alu_3_DW01_add_290' + Mapping 'VX_alu_3_DW01_add_291' + Mapping 'VX_alu_3_DW01_add_292' + Mapping 'VX_alu_3_DW01_add_293' + Mapping 'VX_alu_3_DW_inc_5' + Structuring 'VX_alu_3_DW_div_tc_3' + Mapping 'VX_alu_3_DW_div_tc_3' + Structuring 'VX_alu_3_DW01_absval_3' + Mapping 'VX_alu_3_DW01_absval_3' + Structuring 'VX_alu_3_DW01_inc_3' + Mapping 'VX_alu_3_DW01_inc_3' + Mapping 'VX_alu_3_DW01_add_294' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_295' + Mapping 'VX_alu_3_DW01_add_296' + Mapping 'VX_alu_3_DW01_add_297' + Mapping 'VX_alu_3_DW01_add_298' + Mapping 'VX_alu_3_DW01_add_299' + Mapping 'VX_alu_3_DW01_add_300' + Mapping 'VX_alu_3_DW01_add_301' + Mapping 'VX_alu_3_DW01_add_302' + Mapping 'VX_alu_3_DW01_add_303' + Mapping 'VX_alu_3_DW01_add_304' + Mapping 'VX_alu_3_DW01_add_305' + Mapping 'VX_alu_3_DW01_add_306' + Mapping 'VX_alu_3_DW01_add_307' + Mapping 'VX_alu_3_DW01_add_308' + Mapping 'VX_alu_3_DW01_add_309' + Mapping 'VX_alu_3_DW01_add_310' + Mapping 'VX_alu_3_DW01_add_311' + Mapping 'VX_alu_3_DW01_add_312' + Mapping 'VX_alu_3_DW01_add_313' + Mapping 'VX_alu_3_DW01_add_314' + Mapping 'VX_alu_3_DW01_add_315' + Mapping 'VX_alu_3_DW01_add_316' + Mapping 'VX_alu_3_DW01_add_317' + Mapping 'VX_alu_3_DW01_add_318' + Mapping 'VX_alu_3_DW01_add_319' + Mapping 'VX_alu_3_DW01_add_320' + Mapping 'VX_alu_3_DW01_add_321' + Mapping 'VX_alu_3_DW01_add_322' + Mapping 'VX_alu_3_DW01_add_323' + Mapping 'VX_alu_3_DW01_add_324' + Mapping 'VX_alu_3_DW01_add_325' + Mapping 'VX_alu_3_DW01_add_326' + Mapping 'VX_alu_3_DW01_add_327' + Mapping 'VX_alu_3_DW01_add_328' + Mapping 'VX_alu_3_DW01_add_329' + Mapping 'VX_alu_3_DW01_add_330' + Mapping 'VX_alu_3_DW01_add_331' + Mapping 'VX_alu_3_DW01_add_332' + Mapping 'VX_alu_3_DW01_add_333' + Mapping 'VX_alu_3_DW_inc_7' + Mapping 'VX_alu_3_DW_div_tc_3' + Structuring 'VX_alu_3_DW_div_uns_3' + Mapping 'VX_alu_3_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_334' + Mapping 'VX_alu_3_DW01_add_335' + Mapping 'VX_alu_3_DW01_add_336' + Mapping 'VX_alu_3_DW01_add_337' + Mapping 'VX_alu_3_DW01_add_338' + Mapping 'VX_alu_3_DW01_add_339' + Mapping 'VX_alu_3_DW01_add_340' + Mapping 'VX_alu_3_DW01_add_341' + Mapping 'VX_alu_3_DW01_add_342' + Mapping 'VX_alu_3_DW01_add_343' + Mapping 'VX_alu_3_DW01_add_344' + Mapping 'VX_alu_3_DW01_add_345' + Mapping 'VX_alu_3_DW01_add_346' + Mapping 'VX_alu_3_DW01_add_347' + Mapping 'VX_alu_3_DW01_add_348' + Mapping 'VX_alu_3_DW01_add_349' + Mapping 'VX_alu_3_DW01_add_350' + Mapping 'VX_alu_3_DW01_add_351' + Mapping 'VX_alu_3_DW01_add_352' + Mapping 'VX_alu_3_DW01_add_353' + Mapping 'VX_alu_3_DW01_add_354' + Mapping 'VX_alu_3_DW01_add_355' + Mapping 'VX_alu_3_DW01_add_356' + Mapping 'VX_alu_3_DW01_add_357' + Mapping 'VX_alu_3_DW01_add_358' + Mapping 'VX_alu_3_DW01_add_359' + Mapping 'VX_alu_3_DW01_add_360' + Structuring 'VX_alu_3_DW_div_uns_4' + Mapping 'VX_alu_3_DW_div_uns_4' + Mapping 'VX_alu_3_DW01_add_361' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_362' + Mapping 'VX_alu_3_DW01_add_363' + Mapping 'VX_alu_3_DW01_add_364' + Mapping 'VX_alu_3_DW01_add_365' + Mapping 'VX_alu_3_DW01_add_366' + Mapping 'VX_alu_3_DW01_add_367' + Mapping 'VX_alu_3_DW01_add_368' + Mapping 'VX_alu_3_DW01_add_369' + Mapping 'VX_alu_3_DW01_add_370' + Mapping 'VX_alu_3_DW01_add_371' + Mapping 'VX_alu_3_DW01_add_372' + Mapping 'VX_alu_3_DW01_add_373' + Mapping 'VX_alu_3_DW01_add_374' + Mapping 'VX_alu_3_DW01_add_375' + Mapping 'VX_alu_3_DW01_add_376' + Mapping 'VX_alu_3_DW01_add_377' + Mapping 'VX_alu_3_DW01_add_378' + Mapping 'VX_alu_3_DW01_add_379' + Mapping 'VX_alu_3_DW01_add_380' + Mapping 'VX_alu_3_DW01_add_381' + Mapping 'VX_alu_3_DW01_add_382' + Mapping 'VX_alu_3_DW01_add_383' + Mapping 'VX_alu_3_DW01_add_384' + Mapping 'VX_alu_3_DW01_add_385' + Mapping 'VX_alu_3_DW01_add_386' + Mapping 'VX_alu_3_DW01_add_387' + Mapping 'VX_alu_3_DW01_add_388' + Mapping 'VX_alu_3_DW01_add_389' + Mapping 'VX_alu_3_DW01_add_390' + Mapping 'VX_alu_3_DW01_add_391' + Mapping 'VX_alu_3_DW01_add_392' + Mapping 'VX_alu_3_DW01_add_393' + Mapping 'VX_alu_3_DW01_add_394' + Mapping 'VX_alu_3_DW01_add_395' + Mapping 'VX_alu_3_DW01_add_396' + Mapping 'VX_alu_3_DW01_add_397' + Mapping 'VX_alu_3_DW01_add_398' + Mapping 'VX_alu_3_DW01_add_399' + Mapping 'VX_alu_3_DW01_add_400' + Structuring 'VX_alu_3_DW_div_uns_5' + Mapping 'VX_alu_3_DW_div_uns_5' + Mapping 'VX_alu_3_DW01_add_401' + Mapping 'VX_alu_3_DW01_add_402' + Mapping 'VX_alu_3_DW01_add_403' + Mapping 'VX_alu_3_DW01_sub_2' + Mapping 'VX_alu_3_DW01_add_404' + Mapping 'VX_alu_3_DW01_add_405' + Mapping 'VX_alu_3_DW01_add_406' + Mapping 'VX_alu_3_DW01_add_411' + Mapping 'VX_alu_3_DW01_add_412' + Mapping 'VX_alu_3_DW01_add_413' + Mapping 'VX_alu_3_DW01_add_414' + Mapping 'VX_alu_3_DW01_add_415' + Mapping 'VX_alu_3_DW01_add_416' + Mapping 'VX_alu_3_DW01_add_417' + Mapping 'VX_alu_3_DW01_add_418' + Mapping 'VX_alu_3_DW01_add_419' + Mapping 'VX_alu_3_DW01_add_420' + Mapping 'VX_alu_3_DW01_add_421' + Mapping 'VX_alu_3_DW01_add_422' + Mapping 'VX_alu_3_DW01_add_423' + Mapping 'VX_alu_3_DW01_add_424' + Mapping 'VX_alu_3_DW01_add_425' + Mapping 'VX_alu_3_DW01_add_426' + Mapping 'VX_alu_3_DW01_add_427' + Mapping 'VX_alu_3_DW01_add_428' + Mapping 'VX_alu_3_DW01_add_429' + Mapping 'VX_alu_3_DW01_add_430' + Mapping 'VX_alu_3_DW01_add_431' + Mapping 'VX_alu_3_DW01_add_432' + Mapping 'VX_alu_3_DW01_add_433' + Mapping 'VX_alu_3_DW01_add_434' + Mapping 'VX_alu_3_DW01_add_435' + Mapping 'VX_alu_3_DW01_add_436' + Mapping 'VX_alu_3_DW01_add_437' + Mapping 'VX_alu_3_DW01_add_438' + Mapping 'VX_alu_3_DW01_add_439' + Mapping 'VX_alu_3_DW01_add_440' + Mapping 'VX_alu_3_DW01_add_441' + Mapping 'VX_alu_3_DW01_add_442' + Mapping 'VX_alu_3_DW01_add_443' + Mapping 'VX_alu_3_DW01_add_444' + Mapping 'VX_alu_3_DW01_add_445' + Mapping 'VX_alu_3_DW01_add_446' + Mapping 'VX_alu_3_DW01_add_447' + Mapping 'VX_alu_3_DW01_add_448' + Mapping 'VX_alu_3_DW01_add_449' + Mapping 'VX_alu_3_DW01_add_450' + Mapping 'VX_alu_3_DW01_add_451' + Mapping 'VX_alu_3_DW01_add_452' + Mapping 'VX_alu_3_DW01_add_453' + Mapping 'VX_alu_3_DW01_add_454' + Mapping 'VX_alu_3_DW01_add_455' + Mapping 'VX_alu_3_DW01_add_456' + Mapping 'VX_alu_3_DW01_add_457' + Mapping 'VX_alu_3_DW01_add_458' + Mapping 'VX_alu_3_DW01_add_459' + Mapping 'VX_alu_3_DW01_add_460' + Mapping 'VX_alu_3_DW01_add_461' + Mapping 'VX_alu_3_DW01_add_462' + Mapping 'VX_alu_3_DW01_add_463' + Mapping 'VX_alu_3_DW01_add_464' + Mapping 'VX_alu_3_DW01_add_465' + Mapping 'VX_alu_3_DW01_add_466' + Mapping 'VX_alu_3_DW01_add_467' + Mapping 'VX_alu_3_DW01_add_468' + Mapping 'VX_alu_3_DW01_add_469' + Mapping 'VX_alu_3_DW01_add_470' + Mapping 'VX_alu_3_DW01_add_471' + Mapping 'VX_alu_3_DW01_add_472' + Mapping 'VX_alu_3_DW01_add_473' + Mapping 'VX_alu_3_DW01_add_474' + Mapping 'VX_alu_3_DW01_add_475' + Mapping 'VX_alu_3_DW01_add_476' + Mapping 'VX_alu_3_DW01_add_477' + Mapping 'VX_alu_3_DW01_add_478' + Mapping 'VX_alu_3_DW01_add_479' + Mapping 'VX_alu_3_DW01_add_480' + Structuring 'VX_alu_3_DW_div_uns_6' + Mapping 'VX_alu_3_DW_div_uns_6' + Mapping 'VX_alu_3_DW01_add_481' + Mapping 'VX_alu_3_DW01_add_482' + Mapping 'VX_alu_3_DW01_add_483' + Mapping 'VX_alu_3_DW01_sub_3' + Mapping 'VX_alu_3_DW01_add_484' + Mapping 'VX_alu_3_DW01_add_485' + Mapping 'VX_alu_3_DW01_add_486' + Mapping 'VX_alu_3_DW01_add_491' + Mapping 'VX_alu_3_DW01_add_492' + Mapping 'VX_alu_3_DW01_add_493' + Mapping 'VX_alu_3_DW01_add_494' + Mapping 'VX_alu_3_DW01_add_495' + Mapping 'VX_alu_3_DW01_add_496' + Mapping 'VX_alu_3_DW01_add_497' + Mapping 'VX_alu_3_DW01_add_498' + Mapping 'VX_alu_3_DW01_add_499' + Mapping 'VX_alu_3_DW01_add_500' + Mapping 'VX_alu_3_DW01_add_501' + Mapping 'VX_alu_3_DW01_add_502' + Mapping 'VX_alu_3_DW01_add_503' + Mapping 'VX_alu_3_DW01_add_504' + Mapping 'VX_alu_3_DW01_add_505' + Mapping 'VX_alu_3_DW01_add_506' + Mapping 'VX_alu_3_DW01_add_507' + Mapping 'VX_alu_3_DW01_add_508' + Mapping 'VX_alu_3_DW01_add_509' + Mapping 'VX_alu_3_DW01_add_510' + Mapping 'VX_alu_3_DW01_add_511' + Mapping 'VX_alu_3_DW01_add_512' + Mapping 'VX_alu_3_DW01_add_513' + Mapping 'VX_alu_3_DW01_add_514' + Mapping 'VX_alu_3_DW01_add_515' + Mapping 'VX_alu_3_DW01_add_516' + Mapping 'VX_alu_3_DW01_add_517' + Mapping 'VX_alu_3_DW01_add_518' + Mapping 'VX_alu_3_DW01_add_519' + Mapping 'VX_alu_3_DW01_add_520' + Mapping 'VX_alu_3_DW01_add_521' + Mapping 'VX_alu_3_DW01_add_522' + Mapping 'VX_alu_3_DW01_add_523' + Mapping 'VX_alu_3_DW01_add_524' + Mapping 'VX_alu_3_DW01_add_525' + Mapping 'VX_alu_3_DW01_add_526' + Mapping 'VX_alu_3_DW01_add_527' + Mapping 'VX_alu_3_DW01_add_528' + Mapping 'VX_alu_3_DW01_add_529' + Mapping 'VX_alu_3_DW01_add_530' + Mapping 'VX_alu_3_DW01_add_531' + Mapping 'VX_alu_3_DW01_add_532' + Mapping 'VX_alu_3_DW01_add_533' + Mapping 'VX_alu_3_DW01_add_534' + Mapping 'VX_alu_3_DW01_add_535' + Mapping 'VX_alu_3_DW01_add_536' + Mapping 'VX_alu_3_DW01_add_537' + Mapping 'VX_alu_3_DW01_add_538' + Mapping 'VX_alu_3_DW01_add_539' + Mapping 'VX_alu_3_DW01_add_540' + Mapping 'VX_alu_3_DW01_add_541' + Mapping 'VX_alu_3_DW01_add_542' + Mapping 'VX_alu_3_DW01_add_543' + Mapping 'VX_alu_3_DW01_add_544' + Mapping 'VX_alu_3_DW01_add_545' + Mapping 'VX_alu_3_DW01_add_546' + Mapping 'VX_alu_3_DW01_add_547' + Mapping 'VX_alu_3_DW01_add_548' + Mapping 'VX_alu_3_DW01_add_549' + Mapping 'VX_alu_3_DW01_add_550' + Mapping 'VX_alu_3_DW01_add_551' + Mapping 'VX_alu_3_DW01_add_552' + Mapping 'VX_alu_3_DW01_add_553' + Mapping 'VX_alu_3_DW01_add_554' + Mapping 'VX_alu_3_DW01_add_555' + Mapping 'VX_alu_3_DW01_add_556' + Mapping 'VX_alu_3_DW01_add_557' + Mapping 'VX_alu_3_DW01_add_558' + Mapping 'VX_alu_3_DW01_add_559' + Mapping 'VX_alu_3_DW01_add_560' + Mapping 'VX_alu_3_DW_div_uns_6' + Structuring 'VX_alu_3_DW_div_tc_4' + Mapping 'VX_alu_3_DW_div_tc_4' + Structuring 'VX_alu_3_DW01_absval_4' + Mapping 'VX_alu_3_DW01_absval_4' + Structuring 'VX_alu_3_DW01_inc_4' + Mapping 'VX_alu_3_DW01_inc_4' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_561' + Mapping 'VX_alu_3_DW01_add_562' + Mapping 'VX_alu_3_DW01_add_563' + Mapping 'VX_alu_3_DW01_add_564' + Mapping 'VX_alu_3_DW01_add_565' + Mapping 'VX_alu_3_DW01_add_566' + Mapping 'VX_alu_3_DW01_add_567' + Mapping 'VX_alu_3_DW01_add_568' + Mapping 'VX_alu_3_DW01_add_569' + Mapping 'VX_alu_3_DW01_add_570' + Mapping 'VX_alu_3_DW01_add_571' + Mapping 'VX_alu_3_DW01_add_572' + Mapping 'VX_alu_3_DW01_add_573' + Mapping 'VX_alu_3_DW01_add_574' + Mapping 'VX_alu_3_DW01_add_575' + Mapping 'VX_alu_3_DW01_add_576' + Mapping 'VX_alu_3_DW01_add_577' + Mapping 'VX_alu_3_DW01_add_578' + Mapping 'VX_alu_3_DW01_add_579' + Mapping 'VX_alu_3_DW01_add_580' + Mapping 'VX_alu_3_DW01_add_581' + Mapping 'VX_alu_3_DW01_add_582' + Mapping 'VX_alu_3_DW01_add_583' + Mapping 'VX_alu_3_DW01_add_584' + Mapping 'VX_alu_3_DW01_add_585' + Mapping 'VX_alu_3_DW01_add_586' + Mapping 'VX_alu_3_DW01_add_587' + Mapping 'VX_alu_3_DW_inc_8' + Structuring 'VX_alu_3_DW_div_tc_5' + Mapping 'VX_alu_3_DW_div_tc_5' + Structuring 'VX_alu_3_DW01_absval_5' + Mapping 'VX_alu_3_DW01_absval_5' + Structuring 'VX_alu_3_DW01_inc_5' + Mapping 'VX_alu_3_DW01_inc_5' + Mapping 'VX_alu_3_DW01_add_588' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_589' + Mapping 'VX_alu_3_DW01_add_590' + Mapping 'VX_alu_3_DW01_add_591' + Mapping 'VX_alu_3_DW01_add_592' + Mapping 'VX_alu_3_DW01_add_593' + Mapping 'VX_alu_3_DW01_add_594' + Mapping 'VX_alu_3_DW01_add_595' + Mapping 'VX_alu_3_DW01_add_596' + Mapping 'VX_alu_3_DW01_add_597' + Mapping 'VX_alu_3_DW01_add_598' + Mapping 'VX_alu_3_DW01_add_599' + Mapping 'VX_alu_3_DW01_add_600' + Mapping 'VX_alu_3_DW01_add_601' + Mapping 'VX_alu_3_DW01_add_602' + Mapping 'VX_alu_3_DW01_add_603' + Mapping 'VX_alu_3_DW01_add_604' + Mapping 'VX_alu_3_DW01_add_605' + Mapping 'VX_alu_3_DW01_add_606' + Mapping 'VX_alu_3_DW01_add_607' + Mapping 'VX_alu_3_DW01_add_608' + Mapping 'VX_alu_3_DW01_add_609' + Mapping 'VX_alu_3_DW01_add_610' + Mapping 'VX_alu_3_DW01_add_611' + Mapping 'VX_alu_3_DW01_add_612' + Mapping 'VX_alu_3_DW01_add_613' + Mapping 'VX_alu_3_DW01_add_614' + Mapping 'VX_alu_3_DW01_add_615' + Mapping 'VX_alu_3_DW01_add_616' + Mapping 'VX_alu_3_DW01_add_617' + Mapping 'VX_alu_3_DW01_add_618' + Mapping 'VX_alu_3_DW01_add_619' + Mapping 'VX_alu_3_DW01_add_620' + Mapping 'VX_alu_3_DW01_add_621' + Mapping 'VX_alu_3_DW01_add_622' + Mapping 'VX_alu_3_DW01_add_623' + Mapping 'VX_alu_3_DW01_add_624' + Mapping 'VX_alu_3_DW01_add_625' + Mapping 'VX_alu_3_DW01_add_626' + Mapping 'VX_alu_3_DW01_add_627' + Mapping 'VX_alu_3_DW_inc_10' + Structuring 'VX_alu_3_DW_div_tc_6' + Mapping 'VX_alu_3_DW_div_tc_6' + Structuring 'VX_alu_3_DW01_absval_6' + Mapping 'VX_alu_3_DW01_absval_6' + Structuring 'VX_alu_3_DW01_inc_6' + Mapping 'VX_alu_3_DW01_inc_6' + Mapping 'VX_alu_3_DW01_add_628' + Mapping 'VX_alu_3_DW01_add_629' + Mapping 'VX_alu_3_DW01_add_630' + Mapping 'VX_alu_3_DW01_sub_4' + Mapping 'VX_alu_3_DW01_add_631' + Mapping 'VX_alu_3_DW01_add_632' + Mapping 'VX_alu_3_DW01_add_633' + Mapping 'VX_alu_3_DW01_add_638' + Mapping 'VX_alu_3_DW01_add_639' + Mapping 'VX_alu_3_DW01_add_640' + Mapping 'VX_alu_3_DW01_add_641' + Mapping 'VX_alu_3_DW01_add_642' + Mapping 'VX_alu_3_DW01_add_643' + Mapping 'VX_alu_3_DW01_add_644' + Mapping 'VX_alu_3_DW01_add_645' + Mapping 'VX_alu_3_DW01_add_646' + Mapping 'VX_alu_3_DW01_add_647' + Mapping 'VX_alu_3_DW01_add_648' + Mapping 'VX_alu_3_DW01_add_649' + Mapping 'VX_alu_3_DW01_add_650' + Mapping 'VX_alu_3_DW01_add_651' + Mapping 'VX_alu_3_DW01_add_652' + Mapping 'VX_alu_3_DW01_add_653' + Mapping 'VX_alu_3_DW01_add_654' + Mapping 'VX_alu_3_DW01_add_655' + Mapping 'VX_alu_3_DW01_add_656' + Mapping 'VX_alu_3_DW01_add_657' + Mapping 'VX_alu_3_DW01_add_658' + Mapping 'VX_alu_3_DW01_add_659' + Mapping 'VX_alu_3_DW01_add_660' + Mapping 'VX_alu_3_DW01_add_661' + Mapping 'VX_alu_3_DW01_add_662' + Mapping 'VX_alu_3_DW01_add_663' + Mapping 'VX_alu_3_DW01_add_664' + Mapping 'VX_alu_3_DW01_add_665' + Mapping 'VX_alu_3_DW01_add_666' + Mapping 'VX_alu_3_DW01_add_667' + Mapping 'VX_alu_3_DW01_add_668' + Mapping 'VX_alu_3_DW01_add_669' + Mapping 'VX_alu_3_DW01_add_670' + Mapping 'VX_alu_3_DW01_add_671' + Mapping 'VX_alu_3_DW01_add_672' + Mapping 'VX_alu_3_DW01_add_673' + Mapping 'VX_alu_3_DW01_add_674' + Mapping 'VX_alu_3_DW01_add_675' + Mapping 'VX_alu_3_DW01_add_676' + Mapping 'VX_alu_3_DW01_add_677' + Mapping 'VX_alu_3_DW01_add_678' + Mapping 'VX_alu_3_DW01_add_679' + Mapping 'VX_alu_3_DW01_add_680' + Mapping 'VX_alu_3_DW01_add_681' + Mapping 'VX_alu_3_DW01_add_682' + Mapping 'VX_alu_3_DW01_add_683' + Mapping 'VX_alu_3_DW01_add_684' + Mapping 'VX_alu_3_DW01_add_685' + Mapping 'VX_alu_3_DW01_add_686' + Mapping 'VX_alu_3_DW01_add_687' + Mapping 'VX_alu_3_DW01_add_688' + Mapping 'VX_alu_3_DW01_add_689' + Mapping 'VX_alu_3_DW01_add_690' + Mapping 'VX_alu_3_DW01_add_691' + Mapping 'VX_alu_3_DW01_add_692' + Mapping 'VX_alu_3_DW01_add_693' + Mapping 'VX_alu_3_DW01_add_694' + Mapping 'VX_alu_3_DW01_add_695' + Mapping 'VX_alu_3_DW01_add_696' + Mapping 'VX_alu_3_DW01_add_697' + Mapping 'VX_alu_3_DW01_add_698' + Mapping 'VX_alu_3_DW01_add_699' + Mapping 'VX_alu_3_DW01_add_700' + Mapping 'VX_alu_3_DW01_add_701' + Mapping 'VX_alu_3_DW01_add_702' + Mapping 'VX_alu_3_DW01_add_703' + Mapping 'VX_alu_3_DW01_add_704' + Mapping 'VX_alu_3_DW01_add_705' + Mapping 'VX_alu_3_DW01_add_706' + Mapping 'VX_alu_3_DW01_add_707' + Mapping 'VX_alu_3_DW_inc_12' + Structuring 'VX_alu_3_DW_div_tc_7' + Mapping 'VX_alu_3_DW_div_tc_7' + Structuring 'VX_alu_3_DW01_absval_7' + Mapping 'VX_alu_3_DW01_absval_7' + Structuring 'VX_alu_3_DW01_inc_7' + Mapping 'VX_alu_3_DW01_inc_7' + Mapping 'VX_alu_3_DW01_add_708' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_3_DW01_add_709' + Mapping 'VX_alu_3_DW01_add_710' + Mapping 'VX_alu_3_DW01_add_711' + Mapping 'VX_alu_3_DW01_add_712' + Mapping 'VX_alu_3_DW01_add_713' + Mapping 'VX_alu_3_DW01_add_714' + Mapping 'VX_alu_3_DW01_add_715' + Mapping 'VX_alu_3_DW01_add_716' + Mapping 'VX_alu_3_DW01_add_717' + Mapping 'VX_alu_3_DW01_add_718' + Mapping 'VX_alu_3_DW01_add_719' + Mapping 'VX_alu_3_DW01_add_720' + Mapping 'VX_alu_3_DW01_add_721' + Mapping 'VX_alu_3_DW01_add_722' + Mapping 'VX_alu_3_DW01_add_723' + Mapping 'VX_alu_3_DW01_add_724' + Mapping 'VX_alu_3_DW01_add_725' + Mapping 'VX_alu_3_DW01_add_726' + Mapping 'VX_alu_3_DW01_add_727' + Mapping 'VX_alu_3_DW01_add_728' + Mapping 'VX_alu_3_DW01_add_729' + Mapping 'VX_alu_3_DW01_add_730' + Mapping 'VX_alu_3_DW01_add_731' + Mapping 'VX_alu_3_DW01_add_732' + Mapping 'VX_alu_3_DW01_add_733' + Mapping 'VX_alu_3_DW01_add_734' + Mapping 'VX_alu_3_DW01_add_735' + Mapping 'VX_alu_3_DW01_add_736' + Mapping 'VX_alu_3_DW01_add_737' + Mapping 'VX_alu_3_DW01_add_738' + Mapping 'VX_alu_3_DW01_add_739' + Mapping 'VX_alu_3_DW01_add_740' + Mapping 'VX_alu_3_DW01_add_741' + Mapping 'VX_alu_3_DW01_add_742' + Mapping 'VX_alu_3_DW01_add_743' + Mapping 'VX_alu_3_DW01_add_744' + Mapping 'VX_alu_3_DW01_add_745' + Mapping 'VX_alu_3_DW01_add_746' + Mapping 'VX_alu_3_DW01_add_747' + Mapping 'VX_alu_3_DW_inc_14' + Mapping 'VX_alu_3_DW_div_tc_7' + Structuring 'VX_alu_0_DW_div_uns_0' + Mapping 'VX_alu_0_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_0' + Mapping 'VX_alu_0_DW01_add_1' + Mapping 'VX_alu_0_DW01_add_2' + Mapping 'VX_alu_0_DW01_add_3' + Mapping 'VX_alu_0_DW01_add_4' + Mapping 'VX_alu_0_DW01_add_5' + Mapping 'VX_alu_0_DW01_add_6' + Mapping 'VX_alu_0_DW01_add_7' + Mapping 'VX_alu_0_DW01_add_8' + Mapping 'VX_alu_0_DW01_add_9' + Mapping 'VX_alu_0_DW01_add_10' + Mapping 'VX_alu_0_DW01_add_11' + Mapping 'VX_alu_0_DW01_add_12' + Mapping 'VX_alu_0_DW01_add_13' + Mapping 'VX_alu_0_DW01_add_14' + Mapping 'VX_alu_0_DW01_add_15' + Mapping 'VX_alu_0_DW01_add_16' + Mapping 'VX_alu_0_DW01_add_17' + Mapping 'VX_alu_0_DW01_add_18' + Mapping 'VX_alu_0_DW01_add_19' + Mapping 'VX_alu_0_DW01_add_20' + Mapping 'VX_alu_0_DW01_add_21' + Mapping 'VX_alu_0_DW01_add_22' + Mapping 'VX_alu_0_DW01_add_23' + Mapping 'VX_alu_0_DW01_add_24' + Mapping 'VX_alu_0_DW01_add_25' + Mapping 'VX_alu_0_DW01_add_26' + Structuring 'VX_alu_0_DW_div_uns_1' + Mapping 'VX_alu_0_DW_div_uns_1' + Mapping 'VX_alu_0_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_28' + Mapping 'VX_alu_0_DW01_add_29' + Mapping 'VX_alu_0_DW01_add_30' + Mapping 'VX_alu_0_DW01_add_31' + Mapping 'VX_alu_0_DW01_add_32' + Mapping 'VX_alu_0_DW01_add_33' + Mapping 'VX_alu_0_DW01_add_34' + Mapping 'VX_alu_0_DW01_add_35' + Mapping 'VX_alu_0_DW01_add_36' + Mapping 'VX_alu_0_DW01_add_37' + Mapping 'VX_alu_0_DW01_add_38' + Mapping 'VX_alu_0_DW01_add_39' + Mapping 'VX_alu_0_DW01_add_40' + Mapping 'VX_alu_0_DW01_add_41' + Mapping 'VX_alu_0_DW01_add_42' + Mapping 'VX_alu_0_DW01_add_43' + Mapping 'VX_alu_0_DW01_add_44' + Mapping 'VX_alu_0_DW01_add_45' + Mapping 'VX_alu_0_DW01_add_46' + Mapping 'VX_alu_0_DW01_add_47' + Mapping 'VX_alu_0_DW01_add_48' + Mapping 'VX_alu_0_DW01_add_49' + Mapping 'VX_alu_0_DW01_add_50' + Mapping 'VX_alu_0_DW01_add_51' + Mapping 'VX_alu_0_DW01_add_52' + Mapping 'VX_alu_0_DW01_add_53' + Mapping 'VX_alu_0_DW01_add_54' + Mapping 'VX_alu_0_DW01_add_55' + Mapping 'VX_alu_0_DW01_add_56' + Mapping 'VX_alu_0_DW01_add_57' + Mapping 'VX_alu_0_DW01_add_58' + Mapping 'VX_alu_0_DW01_add_59' + Mapping 'VX_alu_0_DW01_add_60' + Mapping 'VX_alu_0_DW01_add_61' + Mapping 'VX_alu_0_DW01_add_62' + Mapping 'VX_alu_0_DW01_add_63' + Mapping 'VX_alu_0_DW01_add_64' + Mapping 'VX_alu_0_DW01_add_65' + Mapping 'VX_alu_0_DW01_add_66' + Structuring 'VX_alu_0_DW_div_uns_2' + Mapping 'VX_alu_0_DW_div_uns_2' + Mapping 'VX_alu_0_DW01_add_67' + Mapping 'VX_alu_0_DW01_add_68' + Mapping 'VX_alu_0_DW01_add_69' + Mapping 'VX_alu_0_DW01_sub_0' + Mapping 'VX_alu_0_DW01_add_70' + Mapping 'VX_alu_0_DW01_add_71' + Mapping 'VX_alu_0_DW01_add_72' + Mapping 'VX_alu_0_DW01_add_77' + Mapping 'VX_alu_0_DW01_add_78' + Mapping 'VX_alu_0_DW01_add_79' + Mapping 'VX_alu_0_DW01_add_80' + Mapping 'VX_alu_0_DW01_add_81' + Mapping 'VX_alu_0_DW01_add_82' + Mapping 'VX_alu_0_DW01_add_83' + Mapping 'VX_alu_0_DW01_add_84' + Mapping 'VX_alu_0_DW01_add_85' + Mapping 'VX_alu_0_DW01_add_86' + Mapping 'VX_alu_0_DW01_add_87' + Mapping 'VX_alu_0_DW01_add_88' + Mapping 'VX_alu_0_DW01_add_89' + Mapping 'VX_alu_0_DW01_add_90' + Mapping 'VX_alu_0_DW01_add_91' + Mapping 'VX_alu_0_DW01_add_92' + Mapping 'VX_alu_0_DW01_add_93' + Mapping 'VX_alu_0_DW01_add_94' + Mapping 'VX_alu_0_DW01_add_95' + Mapping 'VX_alu_0_DW01_add_96' + Mapping 'VX_alu_0_DW01_add_97' + Mapping 'VX_alu_0_DW01_add_98' + Mapping 'VX_alu_0_DW01_add_99' + Mapping 'VX_alu_0_DW01_add_100' + Mapping 'VX_alu_0_DW01_add_101' + Mapping 'VX_alu_0_DW01_add_102' + Mapping 'VX_alu_0_DW01_add_103' + Mapping 'VX_alu_0_DW01_add_104' + Mapping 'VX_alu_0_DW01_add_105' + Mapping 'VX_alu_0_DW01_add_106' + Mapping 'VX_alu_0_DW01_add_107' + Mapping 'VX_alu_0_DW01_add_108' + Mapping 'VX_alu_0_DW01_add_109' + Mapping 'VX_alu_0_DW01_add_110' + Mapping 'VX_alu_0_DW01_add_111' + Mapping 'VX_alu_0_DW01_add_112' + Mapping 'VX_alu_0_DW01_add_113' + Mapping 'VX_alu_0_DW01_add_114' + Mapping 'VX_alu_0_DW01_add_115' + Mapping 'VX_alu_0_DW01_add_116' + Mapping 'VX_alu_0_DW01_add_117' + Mapping 'VX_alu_0_DW01_add_118' + Mapping 'VX_alu_0_DW01_add_119' + Mapping 'VX_alu_0_DW01_add_120' + Mapping 'VX_alu_0_DW01_add_121' + Mapping 'VX_alu_0_DW01_add_122' + Mapping 'VX_alu_0_DW01_add_123' + Mapping 'VX_alu_0_DW01_add_124' + Mapping 'VX_alu_0_DW01_add_125' + Mapping 'VX_alu_0_DW01_add_126' + Mapping 'VX_alu_0_DW01_add_127' + Mapping 'VX_alu_0_DW01_add_128' + Mapping 'VX_alu_0_DW01_add_129' + Mapping 'VX_alu_0_DW01_add_130' + Mapping 'VX_alu_0_DW01_add_131' + Mapping 'VX_alu_0_DW01_add_132' + Mapping 'VX_alu_0_DW01_add_133' + Mapping 'VX_alu_0_DW01_add_134' + Mapping 'VX_alu_0_DW01_add_135' + Mapping 'VX_alu_0_DW01_add_136' + Mapping 'VX_alu_0_DW01_add_137' + Mapping 'VX_alu_0_DW01_add_138' + Mapping 'VX_alu_0_DW01_add_139' + Mapping 'VX_alu_0_DW01_add_140' + Mapping 'VX_alu_0_DW01_add_141' + Mapping 'VX_alu_0_DW01_add_142' + Mapping 'VX_alu_0_DW01_add_143' + Mapping 'VX_alu_0_DW01_add_144' + Mapping 'VX_alu_0_DW01_add_145' + Mapping 'VX_alu_0_DW01_add_146' + Structuring 'VX_alu_1_DW_div_uns_0' + Mapping 'VX_alu_1_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_0' + Mapping 'VX_alu_1_DW01_add_1' + Mapping 'VX_alu_1_DW01_add_2' + Mapping 'VX_alu_1_DW01_add_3' + Mapping 'VX_alu_1_DW01_add_4' + Mapping 'VX_alu_1_DW01_add_5' + Mapping 'VX_alu_1_DW01_add_6' + Mapping 'VX_alu_1_DW01_add_7' + Mapping 'VX_alu_1_DW01_add_8' + Mapping 'VX_alu_1_DW01_add_9' + Mapping 'VX_alu_1_DW01_add_10' + Mapping 'VX_alu_1_DW01_add_11' + Mapping 'VX_alu_1_DW01_add_12' + Mapping 'VX_alu_1_DW01_add_13' + Mapping 'VX_alu_1_DW01_add_14' + Mapping 'VX_alu_1_DW01_add_15' + Mapping 'VX_alu_1_DW01_add_16' + Mapping 'VX_alu_1_DW01_add_17' + Mapping 'VX_alu_1_DW01_add_18' + Mapping 'VX_alu_1_DW01_add_19' + Mapping 'VX_alu_1_DW01_add_20' + Mapping 'VX_alu_1_DW01_add_21' + Mapping 'VX_alu_1_DW01_add_22' + Mapping 'VX_alu_1_DW01_add_23' + Mapping 'VX_alu_1_DW01_add_24' + Mapping 'VX_alu_1_DW01_add_25' + Mapping 'VX_alu_1_DW01_add_26' + Structuring 'VX_alu_1_DW_div_uns_1' + Mapping 'VX_alu_1_DW_div_uns_1' + Mapping 'VX_alu_1_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_28' + Mapping 'VX_alu_1_DW01_add_29' + Mapping 'VX_alu_1_DW01_add_30' + Mapping 'VX_alu_1_DW01_add_31' + Mapping 'VX_alu_1_DW01_add_32' + Mapping 'VX_alu_1_DW01_add_33' + Mapping 'VX_alu_1_DW01_add_34' + Mapping 'VX_alu_1_DW01_add_35' + Mapping 'VX_alu_1_DW01_add_36' + Mapping 'VX_alu_1_DW01_add_37' + Mapping 'VX_alu_1_DW01_add_38' + Mapping 'VX_alu_1_DW01_add_39' + Mapping 'VX_alu_1_DW01_add_40' + Mapping 'VX_alu_1_DW01_add_41' + Mapping 'VX_alu_1_DW01_add_42' + Mapping 'VX_alu_1_DW01_add_43' + Mapping 'VX_alu_1_DW01_add_44' + Mapping 'VX_alu_1_DW01_add_45' + Mapping 'VX_alu_1_DW01_add_46' + Mapping 'VX_alu_1_DW01_add_47' + Mapping 'VX_alu_1_DW01_add_48' + Mapping 'VX_alu_1_DW01_add_49' + Mapping 'VX_alu_1_DW01_add_50' + Mapping 'VX_alu_1_DW01_add_51' + Mapping 'VX_alu_1_DW01_add_52' + Mapping 'VX_alu_1_DW01_add_53' + Mapping 'VX_alu_1_DW01_add_54' + Mapping 'VX_alu_1_DW01_add_55' + Mapping 'VX_alu_1_DW01_add_56' + Mapping 'VX_alu_1_DW01_add_57' + Mapping 'VX_alu_1_DW01_add_58' + Mapping 'VX_alu_1_DW01_add_59' + Mapping 'VX_alu_1_DW01_add_60' + Mapping 'VX_alu_1_DW01_add_61' + Mapping 'VX_alu_1_DW01_add_62' + Mapping 'VX_alu_1_DW01_add_63' + Mapping 'VX_alu_1_DW01_add_64' + Mapping 'VX_alu_1_DW01_add_65' + Mapping 'VX_alu_1_DW01_add_66' + Structuring 'VX_alu_1_DW_div_uns_2' + Mapping 'VX_alu_1_DW_div_uns_2' + Mapping 'VX_alu_1_DW01_add_67' + Mapping 'VX_alu_1_DW01_add_68' + Mapping 'VX_alu_1_DW01_add_69' + Mapping 'VX_alu_1_DW01_sub_0' + Mapping 'VX_alu_1_DW01_add_70' + Mapping 'VX_alu_1_DW01_add_71' + Mapping 'VX_alu_1_DW01_add_72' + Mapping 'VX_alu_1_DW01_add_77' + Mapping 'VX_alu_1_DW01_add_78' + Mapping 'VX_alu_1_DW01_add_79' + Mapping 'VX_alu_1_DW01_add_80' + Mapping 'VX_alu_1_DW01_add_81' + Mapping 'VX_alu_1_DW01_add_82' + Mapping 'VX_alu_1_DW01_add_83' + Mapping 'VX_alu_1_DW01_add_84' + Mapping 'VX_alu_1_DW01_add_85' + Mapping 'VX_alu_1_DW01_add_86' + Mapping 'VX_alu_1_DW01_add_87' + Mapping 'VX_alu_1_DW01_add_88' + Mapping 'VX_alu_1_DW01_add_89' + Mapping 'VX_alu_1_DW01_add_90' + Mapping 'VX_alu_1_DW01_add_91' + Mapping 'VX_alu_1_DW01_add_92' + Mapping 'VX_alu_1_DW01_add_93' + Mapping 'VX_alu_1_DW01_add_94' + Mapping 'VX_alu_1_DW01_add_95' + Mapping 'VX_alu_1_DW01_add_96' + Mapping 'VX_alu_1_DW01_add_97' + Mapping 'VX_alu_1_DW01_add_98' + Mapping 'VX_alu_1_DW01_add_99' + Mapping 'VX_alu_1_DW01_add_100' + Mapping 'VX_alu_1_DW01_add_101' + Mapping 'VX_alu_1_DW01_add_102' + Mapping 'VX_alu_1_DW01_add_103' + Mapping 'VX_alu_1_DW01_add_104' + Mapping 'VX_alu_1_DW01_add_105' + Mapping 'VX_alu_1_DW01_add_106' + Mapping 'VX_alu_1_DW01_add_107' + Mapping 'VX_alu_1_DW01_add_108' + Mapping 'VX_alu_1_DW01_add_109' + Mapping 'VX_alu_1_DW01_add_110' + Mapping 'VX_alu_1_DW01_add_111' + Mapping 'VX_alu_1_DW01_add_112' + Mapping 'VX_alu_1_DW01_add_113' + Mapping 'VX_alu_1_DW01_add_114' + Mapping 'VX_alu_1_DW01_add_115' + Mapping 'VX_alu_1_DW01_add_116' + Mapping 'VX_alu_1_DW01_add_117' + Mapping 'VX_alu_1_DW01_add_118' + Mapping 'VX_alu_1_DW01_add_119' + Mapping 'VX_alu_1_DW01_add_120' + Mapping 'VX_alu_1_DW01_add_121' + Mapping 'VX_alu_1_DW01_add_122' + Mapping 'VX_alu_1_DW01_add_123' + Mapping 'VX_alu_1_DW01_add_124' + Mapping 'VX_alu_1_DW01_add_125' + Mapping 'VX_alu_1_DW01_add_126' + Mapping 'VX_alu_1_DW01_add_127' + Mapping 'VX_alu_1_DW01_add_128' + Mapping 'VX_alu_1_DW01_add_129' + Mapping 'VX_alu_1_DW01_add_130' + Mapping 'VX_alu_1_DW01_add_131' + Mapping 'VX_alu_1_DW01_add_132' + Mapping 'VX_alu_1_DW01_add_133' + Mapping 'VX_alu_1_DW01_add_134' + Mapping 'VX_alu_1_DW01_add_135' + Mapping 'VX_alu_1_DW01_add_136' + Mapping 'VX_alu_1_DW01_add_137' + Mapping 'VX_alu_1_DW01_add_138' + Mapping 'VX_alu_1_DW01_add_139' + Mapping 'VX_alu_1_DW01_add_140' + Mapping 'VX_alu_1_DW01_add_141' + Mapping 'VX_alu_1_DW01_add_142' + Mapping 'VX_alu_1_DW01_add_143' + Mapping 'VX_alu_1_DW01_add_144' + Mapping 'VX_alu_1_DW01_add_145' + Mapping 'VX_alu_1_DW01_add_146' + Structuring 'VX_alu_2_DW_div_uns_0' + Mapping 'VX_alu_2_DW_div_uns_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_0' + Mapping 'VX_alu_2_DW01_add_1' + Mapping 'VX_alu_2_DW01_add_2' + Mapping 'VX_alu_2_DW01_add_3' + Mapping 'VX_alu_2_DW01_add_4' + Mapping 'VX_alu_2_DW01_add_5' + Mapping 'VX_alu_2_DW01_add_6' + Mapping 'VX_alu_2_DW01_add_7' + Mapping 'VX_alu_2_DW01_add_8' + Mapping 'VX_alu_2_DW01_add_9' + Mapping 'VX_alu_2_DW01_add_10' + Mapping 'VX_alu_2_DW01_add_11' + Mapping 'VX_alu_2_DW01_add_12' + Mapping 'VX_alu_2_DW01_add_13' + Mapping 'VX_alu_2_DW01_add_14' + Mapping 'VX_alu_2_DW01_add_15' + Mapping 'VX_alu_2_DW01_add_16' + Mapping 'VX_alu_2_DW01_add_17' + Mapping 'VX_alu_2_DW01_add_18' + Mapping 'VX_alu_2_DW01_add_19' + Mapping 'VX_alu_2_DW01_add_20' + Mapping 'VX_alu_2_DW01_add_21' + Mapping 'VX_alu_2_DW01_add_22' + Mapping 'VX_alu_2_DW01_add_23' + Mapping 'VX_alu_2_DW01_add_24' + Mapping 'VX_alu_2_DW01_add_25' + Mapping 'VX_alu_2_DW01_add_26' + Structuring 'VX_alu_2_DW_div_uns_1' + Mapping 'VX_alu_2_DW_div_uns_1' + Mapping 'VX_alu_2_DW01_add_27' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_28' + Mapping 'VX_alu_2_DW01_add_29' + Mapping 'VX_alu_2_DW01_add_30' + Mapping 'VX_alu_2_DW01_add_31' + Mapping 'VX_alu_2_DW01_add_32' + Mapping 'VX_alu_2_DW01_add_33' + Mapping 'VX_alu_2_DW01_add_34' + Mapping 'VX_alu_2_DW01_add_35' + Mapping 'VX_alu_2_DW01_add_36' + Mapping 'VX_alu_2_DW01_add_37' + Mapping 'VX_alu_2_DW01_add_38' + Mapping 'VX_alu_2_DW01_add_39' + Mapping 'VX_alu_2_DW01_add_40' + Mapping 'VX_alu_2_DW01_add_41' + Mapping 'VX_alu_2_DW01_add_42' + Mapping 'VX_alu_2_DW01_add_43' + Mapping 'VX_alu_2_DW01_add_44' + Mapping 'VX_alu_2_DW01_add_45' + Mapping 'VX_alu_2_DW01_add_46' + Mapping 'VX_alu_2_DW01_add_47' + Mapping 'VX_alu_2_DW01_add_48' + Mapping 'VX_alu_2_DW01_add_49' + Mapping 'VX_alu_2_DW01_add_50' + Mapping 'VX_alu_2_DW01_add_51' + Mapping 'VX_alu_2_DW01_add_52' + Mapping 'VX_alu_2_DW01_add_53' + Mapping 'VX_alu_2_DW01_add_54' + Mapping 'VX_alu_2_DW01_add_55' + Mapping 'VX_alu_2_DW01_add_56' + Mapping 'VX_alu_2_DW01_add_57' + Mapping 'VX_alu_2_DW01_add_58' + Mapping 'VX_alu_2_DW01_add_59' + Mapping 'VX_alu_2_DW01_add_60' + Mapping 'VX_alu_2_DW01_add_61' + Mapping 'VX_alu_2_DW01_add_62' + Mapping 'VX_alu_2_DW01_add_63' + Mapping 'VX_alu_2_DW01_add_64' + Mapping 'VX_alu_2_DW01_add_65' + Mapping 'VX_alu_2_DW01_add_66' + Structuring 'VX_alu_2_DW_div_uns_2' + Mapping 'VX_alu_2_DW_div_uns_2' + Mapping 'VX_alu_2_DW01_add_67' + Mapping 'VX_alu_2_DW01_add_68' + Mapping 'VX_alu_2_DW01_add_69' + Mapping 'VX_alu_2_DW01_sub_0' + Mapping 'VX_alu_2_DW01_add_70' + Mapping 'VX_alu_2_DW01_add_71' + Mapping 'VX_alu_2_DW01_add_72' + Mapping 'VX_alu_2_DW01_add_77' + Mapping 'VX_alu_2_DW01_add_78' + Mapping 'VX_alu_2_DW01_add_79' + Mapping 'VX_alu_2_DW01_add_80' + Mapping 'VX_alu_2_DW01_add_81' + Mapping 'VX_alu_2_DW01_add_82' + Mapping 'VX_alu_2_DW01_add_83' + Mapping 'VX_alu_2_DW01_add_84' + Mapping 'VX_alu_2_DW01_add_85' + Mapping 'VX_alu_2_DW01_add_86' + Mapping 'VX_alu_2_DW01_add_87' + Mapping 'VX_alu_2_DW01_add_88' + Mapping 'VX_alu_2_DW01_add_89' + Mapping 'VX_alu_2_DW01_add_90' + Mapping 'VX_alu_2_DW01_add_91' + Mapping 'VX_alu_2_DW01_add_92' + Mapping 'VX_alu_2_DW01_add_93' + Mapping 'VX_alu_2_DW01_add_94' + Mapping 'VX_alu_2_DW01_add_95' + Mapping 'VX_alu_2_DW01_add_96' + Mapping 'VX_alu_2_DW01_add_97' + Mapping 'VX_alu_2_DW01_add_98' + Mapping 'VX_alu_2_DW01_add_99' + Mapping 'VX_alu_2_DW01_add_100' + Mapping 'VX_alu_2_DW01_add_101' + Mapping 'VX_alu_2_DW01_add_102' + Mapping 'VX_alu_2_DW01_add_103' + Mapping 'VX_alu_2_DW01_add_104' + Mapping 'VX_alu_2_DW01_add_105' + Mapping 'VX_alu_2_DW01_add_106' + Mapping 'VX_alu_2_DW01_add_107' + Mapping 'VX_alu_2_DW01_add_108' + Mapping 'VX_alu_2_DW01_add_109' + Mapping 'VX_alu_2_DW01_add_110' + Mapping 'VX_alu_2_DW01_add_111' + Mapping 'VX_alu_2_DW01_add_112' + Mapping 'VX_alu_2_DW01_add_113' + Mapping 'VX_alu_2_DW01_add_114' + Mapping 'VX_alu_2_DW01_add_115' + Mapping 'VX_alu_2_DW01_add_116' + Mapping 'VX_alu_2_DW01_add_117' + Mapping 'VX_alu_2_DW01_add_118' + Mapping 'VX_alu_2_DW01_add_119' + Mapping 'VX_alu_2_DW01_add_120' + Mapping 'VX_alu_2_DW01_add_121' + Mapping 'VX_alu_2_DW01_add_122' + Mapping 'VX_alu_2_DW01_add_123' + Mapping 'VX_alu_2_DW01_add_124' + Mapping 'VX_alu_2_DW01_add_125' + Mapping 'VX_alu_2_DW01_add_126' + Mapping 'VX_alu_2_DW01_add_127' + Mapping 'VX_alu_2_DW01_add_128' + Mapping 'VX_alu_2_DW01_add_129' + Mapping 'VX_alu_2_DW01_add_130' + Mapping 'VX_alu_2_DW01_add_131' + Mapping 'VX_alu_2_DW01_add_132' + Mapping 'VX_alu_2_DW01_add_133' + Mapping 'VX_alu_2_DW01_add_134' + Mapping 'VX_alu_2_DW01_add_135' + Mapping 'VX_alu_2_DW01_add_136' + Mapping 'VX_alu_2_DW01_add_137' + Mapping 'VX_alu_2_DW01_add_138' + Mapping 'VX_alu_2_DW01_add_139' + Mapping 'VX_alu_2_DW01_add_140' + Mapping 'VX_alu_2_DW01_add_141' + Mapping 'VX_alu_2_DW01_add_142' + Mapping 'VX_alu_2_DW01_add_143' + Mapping 'VX_alu_2_DW01_add_144' + Mapping 'VX_alu_2_DW01_add_145' + Mapping 'VX_alu_2_DW01_add_146' + Structuring 'VX_alu_0_DW_div_tc_0' + Mapping 'VX_alu_0_DW_div_tc_0' + Structuring 'VX_alu_0_DW01_absval_0' + Mapping 'VX_alu_0_DW01_absval_0' + Structuring 'VX_alu_0_DW01_inc_0' + Mapping 'VX_alu_0_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_147' + Mapping 'VX_alu_0_DW01_add_148' + Mapping 'VX_alu_0_DW01_add_149' + Mapping 'VX_alu_0_DW01_add_150' + Mapping 'VX_alu_0_DW01_add_151' + Mapping 'VX_alu_0_DW01_add_152' + Mapping 'VX_alu_0_DW01_add_153' + Mapping 'VX_alu_0_DW01_add_154' + Mapping 'VX_alu_0_DW01_add_155' + Mapping 'VX_alu_0_DW01_add_156' + Mapping 'VX_alu_0_DW01_add_157' + Mapping 'VX_alu_0_DW01_add_158' + Mapping 'VX_alu_0_DW01_add_159' + Mapping 'VX_alu_0_DW01_add_160' + Mapping 'VX_alu_0_DW01_add_161' + Mapping 'VX_alu_0_DW01_add_162' + Mapping 'VX_alu_0_DW01_add_163' + Mapping 'VX_alu_0_DW01_add_164' + Mapping 'VX_alu_0_DW01_add_165' + Mapping 'VX_alu_0_DW01_add_166' + Mapping 'VX_alu_0_DW01_add_167' + Mapping 'VX_alu_0_DW01_add_168' + Mapping 'VX_alu_0_DW01_add_169' + Mapping 'VX_alu_0_DW01_add_170' + Mapping 'VX_alu_0_DW01_add_171' + Mapping 'VX_alu_0_DW01_add_172' + Mapping 'VX_alu_0_DW01_add_173' + Mapping 'VX_alu_0_DW_inc_1' + Structuring 'VX_alu_0_DW_div_tc_1' + Mapping 'VX_alu_0_DW_div_tc_1' + Structuring 'VX_alu_0_DW01_absval_1' + Mapping 'VX_alu_0_DW01_absval_1' + Structuring 'VX_alu_0_DW01_inc_1' + Mapping 'VX_alu_0_DW01_inc_1' + Mapping 'VX_alu_0_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_175' + Mapping 'VX_alu_0_DW01_add_176' + Mapping 'VX_alu_0_DW01_add_177' + Mapping 'VX_alu_0_DW01_add_178' + Mapping 'VX_alu_0_DW01_add_179' + Mapping 'VX_alu_0_DW01_add_180' + Mapping 'VX_alu_0_DW01_add_181' + Mapping 'VX_alu_0_DW01_add_182' + Mapping 'VX_alu_0_DW01_add_183' + Mapping 'VX_alu_0_DW01_add_184' + Mapping 'VX_alu_0_DW01_add_185' + Mapping 'VX_alu_0_DW01_add_186' + Mapping 'VX_alu_0_DW01_add_187' + Mapping 'VX_alu_0_DW01_add_188' + Mapping 'VX_alu_0_DW01_add_189' + Mapping 'VX_alu_0_DW01_add_190' + Mapping 'VX_alu_0_DW01_add_191' + Mapping 'VX_alu_0_DW01_add_192' + Mapping 'VX_alu_0_DW01_add_193' + Mapping 'VX_alu_0_DW01_add_194' + Mapping 'VX_alu_0_DW01_add_195' + Mapping 'VX_alu_0_DW01_add_196' + Mapping 'VX_alu_0_DW01_add_197' + Mapping 'VX_alu_0_DW01_add_198' + Mapping 'VX_alu_0_DW01_add_199' + Mapping 'VX_alu_0_DW01_add_200' + Mapping 'VX_alu_0_DW01_add_201' + Mapping 'VX_alu_0_DW01_add_202' + Mapping 'VX_alu_0_DW01_add_203' + Mapping 'VX_alu_0_DW01_add_204' + Mapping 'VX_alu_0_DW01_add_205' + Mapping 'VX_alu_0_DW01_add_206' + Mapping 'VX_alu_0_DW01_add_207' + Mapping 'VX_alu_0_DW01_add_208' + Mapping 'VX_alu_0_DW01_add_209' + Mapping 'VX_alu_0_DW01_add_210' + Mapping 'VX_alu_0_DW01_add_211' + Mapping 'VX_alu_0_DW01_add_212' + Mapping 'VX_alu_0_DW01_add_213' + Mapping 'VX_alu_0_DW_inc_3' + Structuring 'VX_alu_0_DW_div_tc_2' + Mapping 'VX_alu_0_DW_div_tc_2' + Structuring 'VX_alu_0_DW01_absval_2' + Mapping 'VX_alu_0_DW01_absval_2' + Structuring 'VX_alu_0_DW01_inc_2' + Mapping 'VX_alu_0_DW01_inc_2' + Mapping 'VX_alu_0_DW01_add_214' + Mapping 'VX_alu_0_DW01_add_215' + Mapping 'VX_alu_0_DW01_add_216' + Mapping 'VX_alu_0_DW01_sub_1' + Mapping 'VX_alu_0_DW01_add_217' + Mapping 'VX_alu_0_DW01_add_218' + Mapping 'VX_alu_0_DW01_add_219' + Mapping 'VX_alu_0_DW01_add_224' + Mapping 'VX_alu_0_DW01_add_225' + Mapping 'VX_alu_0_DW01_add_226' + Mapping 'VX_alu_0_DW01_add_227' + Mapping 'VX_alu_0_DW01_add_228' + Mapping 'VX_alu_0_DW01_add_229' + Mapping 'VX_alu_0_DW01_add_230' + Mapping 'VX_alu_0_DW01_add_231' + Mapping 'VX_alu_0_DW01_add_232' + Mapping 'VX_alu_0_DW01_add_233' + Mapping 'VX_alu_0_DW01_add_234' + Mapping 'VX_alu_0_DW01_add_235' + Mapping 'VX_alu_0_DW01_add_236' + Mapping 'VX_alu_0_DW01_add_237' + Mapping 'VX_alu_0_DW01_add_238' + Mapping 'VX_alu_0_DW01_add_239' + Mapping 'VX_alu_0_DW01_add_240' + Mapping 'VX_alu_0_DW01_add_241' + Mapping 'VX_alu_0_DW01_add_242' + Mapping 'VX_alu_0_DW01_add_243' + Mapping 'VX_alu_0_DW01_add_244' + Mapping 'VX_alu_0_DW01_add_245' + Mapping 'VX_alu_0_DW01_add_246' + Mapping 'VX_alu_0_DW01_add_247' + Mapping 'VX_alu_0_DW01_add_248' + Mapping 'VX_alu_0_DW01_add_249' + Mapping 'VX_alu_0_DW01_add_250' + Mapping 'VX_alu_0_DW01_add_251' + Mapping 'VX_alu_0_DW01_add_252' + Mapping 'VX_alu_0_DW01_add_253' + Mapping 'VX_alu_0_DW01_add_254' + Mapping 'VX_alu_0_DW01_add_255' + Mapping 'VX_alu_0_DW01_add_256' + Mapping 'VX_alu_0_DW01_add_257' + Mapping 'VX_alu_0_DW01_add_258' + Mapping 'VX_alu_0_DW01_add_259' + Mapping 'VX_alu_0_DW01_add_260' + Mapping 'VX_alu_0_DW01_add_261' + Mapping 'VX_alu_0_DW01_add_262' + Mapping 'VX_alu_0_DW01_add_263' + Mapping 'VX_alu_0_DW01_add_264' + Mapping 'VX_alu_0_DW01_add_265' + Mapping 'VX_alu_0_DW01_add_266' + Mapping 'VX_alu_0_DW01_add_267' + Mapping 'VX_alu_0_DW01_add_268' + Mapping 'VX_alu_0_DW01_add_269' + Mapping 'VX_alu_0_DW01_add_270' + Mapping 'VX_alu_0_DW01_add_271' + Mapping 'VX_alu_0_DW01_add_272' + Mapping 'VX_alu_0_DW01_add_273' + Mapping 'VX_alu_0_DW01_add_274' + Mapping 'VX_alu_0_DW01_add_275' + Mapping 'VX_alu_0_DW01_add_276' + Mapping 'VX_alu_0_DW01_add_277' + Mapping 'VX_alu_0_DW01_add_278' + Mapping 'VX_alu_0_DW01_add_279' + Mapping 'VX_alu_0_DW01_add_280' + Mapping 'VX_alu_0_DW01_add_281' + Mapping 'VX_alu_0_DW01_add_282' + Mapping 'VX_alu_0_DW01_add_283' + Mapping 'VX_alu_0_DW01_add_284' + Mapping 'VX_alu_0_DW01_add_285' + Mapping 'VX_alu_0_DW01_add_286' + Mapping 'VX_alu_0_DW01_add_287' + Mapping 'VX_alu_0_DW01_add_288' + Mapping 'VX_alu_0_DW01_add_289' + Mapping 'VX_alu_0_DW01_add_290' + Mapping 'VX_alu_0_DW01_add_291' + Mapping 'VX_alu_0_DW01_add_292' + Mapping 'VX_alu_0_DW01_add_293' + Mapping 'VX_alu_0_DW_inc_5' + Structuring 'VX_alu_0_DW_div_tc_3' + Mapping 'VX_alu_0_DW_div_tc_3' + Structuring 'VX_alu_0_DW01_absval_3' + Mapping 'VX_alu_0_DW01_absval_3' + Structuring 'VX_alu_0_DW01_inc_3' + Mapping 'VX_alu_0_DW01_inc_3' + Mapping 'VX_alu_0_DW01_add_294' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_295' + Mapping 'VX_alu_0_DW01_add_296' + Mapping 'VX_alu_0_DW01_add_297' + Mapping 'VX_alu_0_DW01_add_298' + Mapping 'VX_alu_0_DW01_add_299' + Mapping 'VX_alu_0_DW01_add_300' + Mapping 'VX_alu_0_DW01_add_301' + Mapping 'VX_alu_0_DW01_add_302' + Mapping 'VX_alu_0_DW01_add_303' + Mapping 'VX_alu_0_DW01_add_304' + Mapping 'VX_alu_0_DW01_add_305' + Mapping 'VX_alu_0_DW01_add_306' + Mapping 'VX_alu_0_DW01_add_307' + Mapping 'VX_alu_0_DW01_add_308' + Mapping 'VX_alu_0_DW01_add_309' + Mapping 'VX_alu_0_DW01_add_310' + Mapping 'VX_alu_0_DW01_add_311' + Mapping 'VX_alu_0_DW01_add_312' + Mapping 'VX_alu_0_DW01_add_313' + Mapping 'VX_alu_0_DW01_add_314' + Mapping 'VX_alu_0_DW01_add_315' + Mapping 'VX_alu_0_DW01_add_316' + Mapping 'VX_alu_0_DW01_add_317' + Mapping 'VX_alu_0_DW01_add_318' + Mapping 'VX_alu_0_DW01_add_319' + Mapping 'VX_alu_0_DW01_add_320' + Mapping 'VX_alu_0_DW01_add_321' + Mapping 'VX_alu_0_DW01_add_322' + Mapping 'VX_alu_0_DW01_add_323' + Mapping 'VX_alu_0_DW01_add_324' + Mapping 'VX_alu_0_DW01_add_325' + Mapping 'VX_alu_0_DW01_add_326' + Mapping 'VX_alu_0_DW01_add_327' + Mapping 'VX_alu_0_DW01_add_328' + Mapping 'VX_alu_0_DW01_add_329' + Mapping 'VX_alu_0_DW01_add_330' + Mapping 'VX_alu_0_DW01_add_331' + Mapping 'VX_alu_0_DW01_add_332' + Mapping 'VX_alu_0_DW01_add_333' + Mapping 'VX_alu_0_DW_inc_7' + Mapping 'VX_alu_0_DW_div_tc_3' + Structuring 'VX_alu_1_DW_div_tc_0' + Mapping 'VX_alu_1_DW_div_tc_0' + Structuring 'VX_alu_1_DW01_absval_0' + Mapping 'VX_alu_1_DW01_absval_0' + Structuring 'VX_alu_1_DW01_inc_0' + Mapping 'VX_alu_1_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_147' + Mapping 'VX_alu_1_DW01_add_148' + Mapping 'VX_alu_1_DW01_add_149' + Mapping 'VX_alu_1_DW01_add_150' + Mapping 'VX_alu_1_DW01_add_151' + Mapping 'VX_alu_1_DW01_add_152' + Mapping 'VX_alu_1_DW01_add_153' + Mapping 'VX_alu_1_DW01_add_154' + Mapping 'VX_alu_1_DW01_add_155' + Mapping 'VX_alu_1_DW01_add_156' + Mapping 'VX_alu_1_DW01_add_157' + Mapping 'VX_alu_1_DW01_add_158' + Mapping 'VX_alu_1_DW01_add_159' + Mapping 'VX_alu_1_DW01_add_160' + Mapping 'VX_alu_1_DW01_add_161' + Mapping 'VX_alu_1_DW01_add_162' + Mapping 'VX_alu_1_DW01_add_163' + Mapping 'VX_alu_1_DW01_add_164' + Mapping 'VX_alu_1_DW01_add_165' + Mapping 'VX_alu_1_DW01_add_166' + Mapping 'VX_alu_1_DW01_add_167' + Mapping 'VX_alu_1_DW01_add_168' + Mapping 'VX_alu_1_DW01_add_169' + Mapping 'VX_alu_1_DW01_add_170' + Mapping 'VX_alu_1_DW01_add_171' + Mapping 'VX_alu_1_DW01_add_172' + Mapping 'VX_alu_1_DW01_add_173' + Mapping 'VX_alu_1_DW_inc_1' + Structuring 'VX_alu_1_DW_div_tc_1' + Mapping 'VX_alu_1_DW_div_tc_1' + Structuring 'VX_alu_1_DW01_absval_1' + Mapping 'VX_alu_1_DW01_absval_1' + Structuring 'VX_alu_1_DW01_inc_1' + Mapping 'VX_alu_1_DW01_inc_1' + Mapping 'VX_alu_1_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_175' + Mapping 'VX_alu_1_DW01_add_176' + Mapping 'VX_alu_1_DW01_add_177' + Mapping 'VX_alu_1_DW01_add_178' + Mapping 'VX_alu_1_DW01_add_179' + Mapping 'VX_alu_1_DW01_add_180' + Mapping 'VX_alu_1_DW01_add_181' + Mapping 'VX_alu_1_DW01_add_182' + Mapping 'VX_alu_1_DW01_add_183' + Mapping 'VX_alu_1_DW01_add_184' + Mapping 'VX_alu_1_DW01_add_185' + Mapping 'VX_alu_1_DW01_add_186' + Mapping 'VX_alu_1_DW01_add_187' + Mapping 'VX_alu_1_DW01_add_188' + Mapping 'VX_alu_1_DW01_add_189' + Mapping 'VX_alu_1_DW01_add_190' + Mapping 'VX_alu_1_DW01_add_191' + Mapping 'VX_alu_1_DW01_add_192' + Mapping 'VX_alu_1_DW01_add_193' + Mapping 'VX_alu_1_DW01_add_194' + Mapping 'VX_alu_1_DW01_add_195' + Mapping 'VX_alu_1_DW01_add_196' + Mapping 'VX_alu_1_DW01_add_197' + Mapping 'VX_alu_1_DW01_add_198' + Mapping 'VX_alu_1_DW01_add_199' + Mapping 'VX_alu_1_DW01_add_200' + Mapping 'VX_alu_1_DW01_add_201' + Mapping 'VX_alu_1_DW01_add_202' + Mapping 'VX_alu_1_DW01_add_203' + Mapping 'VX_alu_1_DW01_add_204' + Mapping 'VX_alu_1_DW01_add_205' + Mapping 'VX_alu_1_DW01_add_206' + Mapping 'VX_alu_1_DW01_add_207' + Mapping 'VX_alu_1_DW01_add_208' + Mapping 'VX_alu_1_DW01_add_209' + Mapping 'VX_alu_1_DW01_add_210' + Mapping 'VX_alu_1_DW01_add_211' + Mapping 'VX_alu_1_DW01_add_212' + Mapping 'VX_alu_1_DW01_add_213' + Mapping 'VX_alu_1_DW_inc_3' + Structuring 'VX_alu_1_DW_div_tc_2' + Mapping 'VX_alu_1_DW_div_tc_2' + Structuring 'VX_alu_1_DW01_absval_2' + Mapping 'VX_alu_1_DW01_absval_2' + Structuring 'VX_alu_1_DW01_inc_2' + Mapping 'VX_alu_1_DW01_inc_2' + Mapping 'VX_alu_1_DW01_add_214' + Mapping 'VX_alu_1_DW01_add_215' + Mapping 'VX_alu_1_DW01_add_216' + Mapping 'VX_alu_1_DW01_sub_1' + Mapping 'VX_alu_1_DW01_add_217' + Mapping 'VX_alu_1_DW01_add_218' + Mapping 'VX_alu_1_DW01_add_219' + Mapping 'VX_alu_1_DW01_add_224' + Mapping 'VX_alu_1_DW01_add_225' + Mapping 'VX_alu_1_DW01_add_226' + Mapping 'VX_alu_1_DW01_add_227' + Mapping 'VX_alu_1_DW01_add_228' + Mapping 'VX_alu_1_DW01_add_229' + Mapping 'VX_alu_1_DW01_add_230' + Mapping 'VX_alu_1_DW01_add_231' + Mapping 'VX_alu_1_DW01_add_232' + Mapping 'VX_alu_1_DW01_add_233' + Mapping 'VX_alu_1_DW01_add_234' + Mapping 'VX_alu_1_DW01_add_235' + Mapping 'VX_alu_1_DW01_add_236' + Mapping 'VX_alu_1_DW01_add_237' + Mapping 'VX_alu_1_DW01_add_238' + Mapping 'VX_alu_1_DW01_add_239' + Mapping 'VX_alu_1_DW01_add_240' + Mapping 'VX_alu_1_DW01_add_241' + Mapping 'VX_alu_1_DW01_add_242' + Mapping 'VX_alu_1_DW01_add_243' + Mapping 'VX_alu_1_DW01_add_244' + Mapping 'VX_alu_1_DW01_add_245' + Mapping 'VX_alu_1_DW01_add_246' + Mapping 'VX_alu_1_DW01_add_247' + Mapping 'VX_alu_1_DW01_add_248' + Mapping 'VX_alu_1_DW01_add_249' + Mapping 'VX_alu_1_DW01_add_250' + Mapping 'VX_alu_1_DW01_add_251' + Mapping 'VX_alu_1_DW01_add_252' + Mapping 'VX_alu_1_DW01_add_253' + Mapping 'VX_alu_1_DW01_add_254' + Mapping 'VX_alu_1_DW01_add_255' + Mapping 'VX_alu_1_DW01_add_256' + Mapping 'VX_alu_1_DW01_add_257' + Mapping 'VX_alu_1_DW01_add_258' + Mapping 'VX_alu_1_DW01_add_259' + Mapping 'VX_alu_1_DW01_add_260' + Mapping 'VX_alu_1_DW01_add_261' + Mapping 'VX_alu_1_DW01_add_262' + Mapping 'VX_alu_1_DW01_add_263' + Mapping 'VX_alu_1_DW01_add_264' + Mapping 'VX_alu_1_DW01_add_265' + Mapping 'VX_alu_1_DW01_add_266' + Mapping 'VX_alu_1_DW01_add_267' + Mapping 'VX_alu_1_DW01_add_268' + Mapping 'VX_alu_1_DW01_add_269' + Mapping 'VX_alu_1_DW01_add_270' + Mapping 'VX_alu_1_DW01_add_271' + Mapping 'VX_alu_1_DW01_add_272' + Mapping 'VX_alu_1_DW01_add_273' + Mapping 'VX_alu_1_DW01_add_274' + Mapping 'VX_alu_1_DW01_add_275' + Mapping 'VX_alu_1_DW01_add_276' + Mapping 'VX_alu_1_DW01_add_277' + Mapping 'VX_alu_1_DW01_add_278' + Mapping 'VX_alu_1_DW01_add_279' + Mapping 'VX_alu_1_DW01_add_280' + Mapping 'VX_alu_1_DW01_add_281' + Mapping 'VX_alu_1_DW01_add_282' + Mapping 'VX_alu_1_DW01_add_283' + Mapping 'VX_alu_1_DW01_add_284' + Mapping 'VX_alu_1_DW01_add_285' + Mapping 'VX_alu_1_DW01_add_286' + Mapping 'VX_alu_1_DW01_add_287' + Mapping 'VX_alu_1_DW01_add_288' + Mapping 'VX_alu_1_DW01_add_289' + Mapping 'VX_alu_1_DW01_add_290' + Mapping 'VX_alu_1_DW01_add_291' + Mapping 'VX_alu_1_DW01_add_292' + Mapping 'VX_alu_1_DW01_add_293' + Mapping 'VX_alu_1_DW_inc_5' + Structuring 'VX_alu_1_DW_div_tc_3' + Mapping 'VX_alu_1_DW_div_tc_3' + Structuring 'VX_alu_1_DW01_absval_3' + Mapping 'VX_alu_1_DW01_absval_3' + Structuring 'VX_alu_1_DW01_inc_3' + Mapping 'VX_alu_1_DW01_inc_3' + Mapping 'VX_alu_1_DW01_add_294' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_295' + Mapping 'VX_alu_1_DW01_add_296' + Mapping 'VX_alu_1_DW01_add_297' + Mapping 'VX_alu_1_DW01_add_298' + Mapping 'VX_alu_1_DW01_add_299' + Mapping 'VX_alu_1_DW01_add_300' + Mapping 'VX_alu_1_DW01_add_301' + Mapping 'VX_alu_1_DW01_add_302' + Mapping 'VX_alu_1_DW01_add_303' + Mapping 'VX_alu_1_DW01_add_304' + Mapping 'VX_alu_1_DW01_add_305' + Mapping 'VX_alu_1_DW01_add_306' + Mapping 'VX_alu_1_DW01_add_307' + Mapping 'VX_alu_1_DW01_add_308' + Mapping 'VX_alu_1_DW01_add_309' + Mapping 'VX_alu_1_DW01_add_310' + Mapping 'VX_alu_1_DW01_add_311' + Mapping 'VX_alu_1_DW01_add_312' + Mapping 'VX_alu_1_DW01_add_313' + Mapping 'VX_alu_1_DW01_add_314' + Mapping 'VX_alu_1_DW01_add_315' + Mapping 'VX_alu_1_DW01_add_316' + Mapping 'VX_alu_1_DW01_add_317' + Mapping 'VX_alu_1_DW01_add_318' + Mapping 'VX_alu_1_DW01_add_319' + Mapping 'VX_alu_1_DW01_add_320' + Mapping 'VX_alu_1_DW01_add_321' + Mapping 'VX_alu_1_DW01_add_322' + Mapping 'VX_alu_1_DW01_add_323' + Mapping 'VX_alu_1_DW01_add_324' + Mapping 'VX_alu_1_DW01_add_325' + Mapping 'VX_alu_1_DW01_add_326' + Mapping 'VX_alu_1_DW01_add_327' + Mapping 'VX_alu_1_DW01_add_328' + Mapping 'VX_alu_1_DW01_add_329' + Mapping 'VX_alu_1_DW01_add_330' + Mapping 'VX_alu_1_DW01_add_331' + Mapping 'VX_alu_1_DW01_add_332' + Mapping 'VX_alu_1_DW01_add_333' + Mapping 'VX_alu_1_DW_inc_7' + Mapping 'VX_alu_1_DW_div_tc_3' + Structuring 'VX_alu_2_DW_div_tc_0' + Mapping 'VX_alu_2_DW_div_tc_0' + Structuring 'VX_alu_2_DW01_absval_0' + Mapping 'VX_alu_2_DW01_absval_0' + Structuring 'VX_alu_2_DW01_inc_0' + Mapping 'VX_alu_2_DW01_inc_0' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_147' + Mapping 'VX_alu_2_DW01_add_148' + Mapping 'VX_alu_2_DW01_add_149' + Mapping 'VX_alu_2_DW01_add_150' + Mapping 'VX_alu_2_DW01_add_151' + Mapping 'VX_alu_2_DW01_add_152' + Mapping 'VX_alu_2_DW01_add_153' + Mapping 'VX_alu_2_DW01_add_154' + Mapping 'VX_alu_2_DW01_add_155' + Mapping 'VX_alu_2_DW01_add_156' + Mapping 'VX_alu_2_DW01_add_157' + Mapping 'VX_alu_2_DW01_add_158' + Mapping 'VX_alu_2_DW01_add_159' + Mapping 'VX_alu_2_DW01_add_160' + Mapping 'VX_alu_2_DW01_add_161' + Mapping 'VX_alu_2_DW01_add_162' + Mapping 'VX_alu_2_DW01_add_163' + Mapping 'VX_alu_2_DW01_add_164' + Mapping 'VX_alu_2_DW01_add_165' + Mapping 'VX_alu_2_DW01_add_166' + Mapping 'VX_alu_2_DW01_add_167' + Mapping 'VX_alu_2_DW01_add_168' + Mapping 'VX_alu_2_DW01_add_169' + Mapping 'VX_alu_2_DW01_add_170' + Mapping 'VX_alu_2_DW01_add_171' + Mapping 'VX_alu_2_DW01_add_172' + Mapping 'VX_alu_2_DW01_add_173' + Mapping 'VX_alu_2_DW_inc_1' + Structuring 'VX_alu_2_DW_div_tc_1' + Mapping 'VX_alu_2_DW_div_tc_1' + Structuring 'VX_alu_2_DW01_absval_1' + Mapping 'VX_alu_2_DW01_absval_1' + Structuring 'VX_alu_2_DW01_inc_1' + Mapping 'VX_alu_2_DW01_inc_1' + Mapping 'VX_alu_2_DW01_add_174' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_175' + Mapping 'VX_alu_2_DW01_add_176' + Mapping 'VX_alu_2_DW01_add_177' + Mapping 'VX_alu_2_DW01_add_178' + Mapping 'VX_alu_2_DW01_add_179' + Mapping 'VX_alu_2_DW01_add_180' + Mapping 'VX_alu_2_DW01_add_181' + Mapping 'VX_alu_2_DW01_add_182' + Mapping 'VX_alu_2_DW01_add_183' + Mapping 'VX_alu_2_DW01_add_184' + Mapping 'VX_alu_2_DW01_add_185' + Mapping 'VX_alu_2_DW01_add_186' + Mapping 'VX_alu_2_DW01_add_187' + Mapping 'VX_alu_2_DW01_add_188' + Mapping 'VX_alu_2_DW01_add_189' + Mapping 'VX_alu_2_DW01_add_190' + Mapping 'VX_alu_2_DW01_add_191' + Mapping 'VX_alu_2_DW01_add_192' + Mapping 'VX_alu_2_DW01_add_193' + Mapping 'VX_alu_2_DW01_add_194' + Mapping 'VX_alu_2_DW01_add_195' + Mapping 'VX_alu_2_DW01_add_196' + Mapping 'VX_alu_2_DW01_add_197' + Mapping 'VX_alu_2_DW01_add_198' + Mapping 'VX_alu_2_DW01_add_199' + Mapping 'VX_alu_2_DW01_add_200' + Mapping 'VX_alu_2_DW01_add_201' + Mapping 'VX_alu_2_DW01_add_202' + Mapping 'VX_alu_2_DW01_add_203' + Mapping 'VX_alu_2_DW01_add_204' + Mapping 'VX_alu_2_DW01_add_205' + Mapping 'VX_alu_2_DW01_add_206' + Mapping 'VX_alu_2_DW01_add_207' + Mapping 'VX_alu_2_DW01_add_208' + Mapping 'VX_alu_2_DW01_add_209' + Mapping 'VX_alu_2_DW01_add_210' + Mapping 'VX_alu_2_DW01_add_211' + Mapping 'VX_alu_2_DW01_add_212' + Mapping 'VX_alu_2_DW01_add_213' + Mapping 'VX_alu_2_DW_inc_3' + Structuring 'VX_alu_2_DW_div_tc_2' + Mapping 'VX_alu_2_DW_div_tc_2' + Structuring 'VX_alu_2_DW01_absval_2' + Mapping 'VX_alu_2_DW01_absval_2' + Structuring 'VX_alu_2_DW01_inc_2' + Mapping 'VX_alu_2_DW01_inc_2' + Mapping 'VX_alu_2_DW01_add_214' + Mapping 'VX_alu_2_DW01_add_215' + Mapping 'VX_alu_2_DW01_add_216' + Mapping 'VX_alu_2_DW01_sub_1' + Mapping 'VX_alu_2_DW01_add_217' + Mapping 'VX_alu_2_DW01_add_218' + Mapping 'VX_alu_2_DW01_add_219' + Mapping 'VX_alu_2_DW01_add_224' + Mapping 'VX_alu_2_DW01_add_225' + Mapping 'VX_alu_2_DW01_add_226' + Mapping 'VX_alu_2_DW01_add_227' + Mapping 'VX_alu_2_DW01_add_228' + Mapping 'VX_alu_2_DW01_add_229' + Mapping 'VX_alu_2_DW01_add_230' + Mapping 'VX_alu_2_DW01_add_231' + Mapping 'VX_alu_2_DW01_add_232' + Mapping 'VX_alu_2_DW01_add_233' + Mapping 'VX_alu_2_DW01_add_234' + Mapping 'VX_alu_2_DW01_add_235' + Mapping 'VX_alu_2_DW01_add_236' + Mapping 'VX_alu_2_DW01_add_237' + Mapping 'VX_alu_2_DW01_add_238' + Mapping 'VX_alu_2_DW01_add_239' + Mapping 'VX_alu_2_DW01_add_240' + Mapping 'VX_alu_2_DW01_add_241' + Mapping 'VX_alu_2_DW01_add_242' + Mapping 'VX_alu_2_DW01_add_243' + Mapping 'VX_alu_2_DW01_add_244' + Mapping 'VX_alu_2_DW01_add_245' + Mapping 'VX_alu_2_DW01_add_246' + Mapping 'VX_alu_2_DW01_add_247' + Mapping 'VX_alu_2_DW01_add_248' + Mapping 'VX_alu_2_DW01_add_249' + Mapping 'VX_alu_2_DW01_add_250' + Mapping 'VX_alu_2_DW01_add_251' + Mapping 'VX_alu_2_DW01_add_252' + Mapping 'VX_alu_2_DW01_add_253' + Mapping 'VX_alu_2_DW01_add_254' + Mapping 'VX_alu_2_DW01_add_255' + Mapping 'VX_alu_2_DW01_add_256' + Mapping 'VX_alu_2_DW01_add_257' + Mapping 'VX_alu_2_DW01_add_258' + Mapping 'VX_alu_2_DW01_add_259' + Mapping 'VX_alu_2_DW01_add_260' + Mapping 'VX_alu_2_DW01_add_261' + Mapping 'VX_alu_2_DW01_add_262' + Mapping 'VX_alu_2_DW01_add_263' + Mapping 'VX_alu_2_DW01_add_264' + Mapping 'VX_alu_2_DW01_add_265' + Mapping 'VX_alu_2_DW01_add_266' + Mapping 'VX_alu_2_DW01_add_267' + Mapping 'VX_alu_2_DW01_add_268' + Mapping 'VX_alu_2_DW01_add_269' + Mapping 'VX_alu_2_DW01_add_270' + Mapping 'VX_alu_2_DW01_add_271' + Mapping 'VX_alu_2_DW01_add_272' + Mapping 'VX_alu_2_DW01_add_273' + Mapping 'VX_alu_2_DW01_add_274' + Mapping 'VX_alu_2_DW01_add_275' + Mapping 'VX_alu_2_DW01_add_276' + Mapping 'VX_alu_2_DW01_add_277' + Mapping 'VX_alu_2_DW01_add_278' + Mapping 'VX_alu_2_DW01_add_279' + Mapping 'VX_alu_2_DW01_add_280' + Mapping 'VX_alu_2_DW01_add_281' + Mapping 'VX_alu_2_DW01_add_282' + Mapping 'VX_alu_2_DW01_add_283' + Mapping 'VX_alu_2_DW01_add_284' + Mapping 'VX_alu_2_DW01_add_285' + Mapping 'VX_alu_2_DW01_add_286' + Mapping 'VX_alu_2_DW01_add_287' + Mapping 'VX_alu_2_DW01_add_288' + Mapping 'VX_alu_2_DW01_add_289' + Mapping 'VX_alu_2_DW01_add_290' + Mapping 'VX_alu_2_DW01_add_291' + Mapping 'VX_alu_2_DW01_add_292' + Mapping 'VX_alu_2_DW01_add_293' + Mapping 'VX_alu_2_DW_inc_5' + Structuring 'VX_alu_2_DW_div_tc_3' + Mapping 'VX_alu_2_DW_div_tc_3' + Structuring 'VX_alu_2_DW01_absval_3' + Mapping 'VX_alu_2_DW01_absval_3' + Structuring 'VX_alu_2_DW01_inc_3' + Mapping 'VX_alu_2_DW01_inc_3' + Mapping 'VX_alu_2_DW01_add_294' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_295' + Mapping 'VX_alu_2_DW01_add_296' + Mapping 'VX_alu_2_DW01_add_297' + Mapping 'VX_alu_2_DW01_add_298' + Mapping 'VX_alu_2_DW01_add_299' + Mapping 'VX_alu_2_DW01_add_300' + Mapping 'VX_alu_2_DW01_add_301' + Mapping 'VX_alu_2_DW01_add_302' + Mapping 'VX_alu_2_DW01_add_303' + Mapping 'VX_alu_2_DW01_add_304' + Mapping 'VX_alu_2_DW01_add_305' + Mapping 'VX_alu_2_DW01_add_306' + Mapping 'VX_alu_2_DW01_add_307' + Mapping 'VX_alu_2_DW01_add_308' + Mapping 'VX_alu_2_DW01_add_309' + Mapping 'VX_alu_2_DW01_add_310' + Mapping 'VX_alu_2_DW01_add_311' + Mapping 'VX_alu_2_DW01_add_312' + Mapping 'VX_alu_2_DW01_add_313' + Mapping 'VX_alu_2_DW01_add_314' + Mapping 'VX_alu_2_DW01_add_315' + Mapping 'VX_alu_2_DW01_add_316' + Mapping 'VX_alu_2_DW01_add_317' + Mapping 'VX_alu_2_DW01_add_318' + Mapping 'VX_alu_2_DW01_add_319' + Mapping 'VX_alu_2_DW01_add_320' + Mapping 'VX_alu_2_DW01_add_321' + Mapping 'VX_alu_2_DW01_add_322' + Mapping 'VX_alu_2_DW01_add_323' + Mapping 'VX_alu_2_DW01_add_324' + Mapping 'VX_alu_2_DW01_add_325' + Mapping 'VX_alu_2_DW01_add_326' + Mapping 'VX_alu_2_DW01_add_327' + Mapping 'VX_alu_2_DW01_add_328' + Mapping 'VX_alu_2_DW01_add_329' + Mapping 'VX_alu_2_DW01_add_330' + Mapping 'VX_alu_2_DW01_add_331' + Mapping 'VX_alu_2_DW01_add_332' + Mapping 'VX_alu_2_DW01_add_333' + Mapping 'VX_alu_2_DW_inc_7' + Mapping 'VX_alu_2_DW_div_tc_3' + Structuring 'VX_alu_0_DW_div_uns_3' + Mapping 'VX_alu_0_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_334' + Mapping 'VX_alu_0_DW01_add_335' + Mapping 'VX_alu_0_DW01_add_336' + Mapping 'VX_alu_0_DW01_add_337' + Mapping 'VX_alu_0_DW01_add_338' + Mapping 'VX_alu_0_DW01_add_339' + Mapping 'VX_alu_0_DW01_add_340' + Mapping 'VX_alu_0_DW01_add_341' + Mapping 'VX_alu_0_DW01_add_342' + Mapping 'VX_alu_0_DW01_add_343' + Mapping 'VX_alu_0_DW01_add_344' + Mapping 'VX_alu_0_DW01_add_345' + Mapping 'VX_alu_0_DW01_add_346' + Mapping 'VX_alu_0_DW01_add_347' + Mapping 'VX_alu_0_DW01_add_348' + Mapping 'VX_alu_0_DW01_add_349' + Mapping 'VX_alu_0_DW01_add_350' + Mapping 'VX_alu_0_DW01_add_351' + Mapping 'VX_alu_0_DW01_add_352' + Mapping 'VX_alu_0_DW01_add_353' + Mapping 'VX_alu_0_DW01_add_354' + Mapping 'VX_alu_0_DW01_add_355' + Mapping 'VX_alu_0_DW01_add_356' + Mapping 'VX_alu_0_DW01_add_357' + Mapping 'VX_alu_0_DW01_add_358' + Mapping 'VX_alu_0_DW01_add_359' + Mapping 'VX_alu_0_DW01_add_360' + Structuring 'VX_alu_0_DW_div_uns_4' + Mapping 'VX_alu_0_DW_div_uns_4' + Mapping 'VX_alu_0_DW01_add_361' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_362' + Mapping 'VX_alu_0_DW01_add_363' + Mapping 'VX_alu_0_DW01_add_364' + Mapping 'VX_alu_0_DW01_add_365' + Mapping 'VX_alu_0_DW01_add_366' + Mapping 'VX_alu_0_DW01_add_367' + Mapping 'VX_alu_0_DW01_add_368' + Mapping 'VX_alu_0_DW01_add_369' + Mapping 'VX_alu_0_DW01_add_370' + Mapping 'VX_alu_0_DW01_add_371' + Mapping 'VX_alu_0_DW01_add_372' + Mapping 'VX_alu_0_DW01_add_373' + Mapping 'VX_alu_0_DW01_add_374' + Mapping 'VX_alu_0_DW01_add_375' + Mapping 'VX_alu_0_DW01_add_376' + Mapping 'VX_alu_0_DW01_add_377' + Mapping 'VX_alu_0_DW01_add_378' + Mapping 'VX_alu_0_DW01_add_379' + Mapping 'VX_alu_0_DW01_add_380' + Mapping 'VX_alu_0_DW01_add_381' + Mapping 'VX_alu_0_DW01_add_382' + Mapping 'VX_alu_0_DW01_add_383' + Mapping 'VX_alu_0_DW01_add_384' + Mapping 'VX_alu_0_DW01_add_385' + Mapping 'VX_alu_0_DW01_add_386' + Mapping 'VX_alu_0_DW01_add_387' + Mapping 'VX_alu_0_DW01_add_388' + Mapping 'VX_alu_0_DW01_add_389' + Mapping 'VX_alu_0_DW01_add_390' + Mapping 'VX_alu_0_DW01_add_391' + Mapping 'VX_alu_0_DW01_add_392' + Mapping 'VX_alu_0_DW01_add_393' + Mapping 'VX_alu_0_DW01_add_394' + Mapping 'VX_alu_0_DW01_add_395' + Mapping 'VX_alu_0_DW01_add_396' + Mapping 'VX_alu_0_DW01_add_397' + Mapping 'VX_alu_0_DW01_add_398' + Mapping 'VX_alu_0_DW01_add_399' + Mapping 'VX_alu_0_DW01_add_400' + Structuring 'VX_alu_0_DW_div_uns_5' + Mapping 'VX_alu_0_DW_div_uns_5' + Mapping 'VX_alu_0_DW01_add_401' + Mapping 'VX_alu_0_DW01_add_402' + Mapping 'VX_alu_0_DW01_add_403' + Mapping 'VX_alu_0_DW01_sub_2' + Mapping 'VX_alu_0_DW01_add_404' + Mapping 'VX_alu_0_DW01_add_405' + Mapping 'VX_alu_0_DW01_add_406' + Mapping 'VX_alu_0_DW01_add_411' + Mapping 'VX_alu_0_DW01_add_412' + Mapping 'VX_alu_0_DW01_add_413' + Mapping 'VX_alu_0_DW01_add_414' + Mapping 'VX_alu_0_DW01_add_415' + Mapping 'VX_alu_0_DW01_add_416' + Mapping 'VX_alu_0_DW01_add_417' + Mapping 'VX_alu_0_DW01_add_418' + Mapping 'VX_alu_0_DW01_add_419' + Mapping 'VX_alu_0_DW01_add_420' + Mapping 'VX_alu_0_DW01_add_421' + Mapping 'VX_alu_0_DW01_add_422' + Mapping 'VX_alu_0_DW01_add_423' + Mapping 'VX_alu_0_DW01_add_424' + Mapping 'VX_alu_0_DW01_add_425' + Mapping 'VX_alu_0_DW01_add_426' + Mapping 'VX_alu_0_DW01_add_427' + Mapping 'VX_alu_0_DW01_add_428' + Mapping 'VX_alu_0_DW01_add_429' + Mapping 'VX_alu_0_DW01_add_430' + Mapping 'VX_alu_0_DW01_add_431' + Mapping 'VX_alu_0_DW01_add_432' + Mapping 'VX_alu_0_DW01_add_433' + Mapping 'VX_alu_0_DW01_add_434' + Mapping 'VX_alu_0_DW01_add_435' + Mapping 'VX_alu_0_DW01_add_436' + Mapping 'VX_alu_0_DW01_add_437' + Mapping 'VX_alu_0_DW01_add_438' + Mapping 'VX_alu_0_DW01_add_439' + Mapping 'VX_alu_0_DW01_add_440' + Mapping 'VX_alu_0_DW01_add_441' + Mapping 'VX_alu_0_DW01_add_442' + Mapping 'VX_alu_0_DW01_add_443' + Mapping 'VX_alu_0_DW01_add_444' + Mapping 'VX_alu_0_DW01_add_445' + Mapping 'VX_alu_0_DW01_add_446' + Mapping 'VX_alu_0_DW01_add_447' + Mapping 'VX_alu_0_DW01_add_448' + Mapping 'VX_alu_0_DW01_add_449' + Mapping 'VX_alu_0_DW01_add_450' + Mapping 'VX_alu_0_DW01_add_451' + Mapping 'VX_alu_0_DW01_add_452' + Mapping 'VX_alu_0_DW01_add_453' + Mapping 'VX_alu_0_DW01_add_454' + Mapping 'VX_alu_0_DW01_add_455' + Mapping 'VX_alu_0_DW01_add_456' + Mapping 'VX_alu_0_DW01_add_457' + Mapping 'VX_alu_0_DW01_add_458' + Mapping 'VX_alu_0_DW01_add_459' + Mapping 'VX_alu_0_DW01_add_460' + Mapping 'VX_alu_0_DW01_add_461' + Mapping 'VX_alu_0_DW01_add_462' + Mapping 'VX_alu_0_DW01_add_463' + Mapping 'VX_alu_0_DW01_add_464' + Mapping 'VX_alu_0_DW01_add_465' + Mapping 'VX_alu_0_DW01_add_466' + Mapping 'VX_alu_0_DW01_add_467' + Mapping 'VX_alu_0_DW01_add_468' + Mapping 'VX_alu_0_DW01_add_469' + Mapping 'VX_alu_0_DW01_add_470' + Mapping 'VX_alu_0_DW01_add_471' + Mapping 'VX_alu_0_DW01_add_472' + Mapping 'VX_alu_0_DW01_add_473' + Mapping 'VX_alu_0_DW01_add_474' + Mapping 'VX_alu_0_DW01_add_475' + Mapping 'VX_alu_0_DW01_add_476' + Mapping 'VX_alu_0_DW01_add_477' + Mapping 'VX_alu_0_DW01_add_478' + Mapping 'VX_alu_0_DW01_add_479' + Mapping 'VX_alu_0_DW01_add_480' + Structuring 'VX_alu_0_DW_div_uns_6' + Mapping 'VX_alu_0_DW_div_uns_6' + Mapping 'VX_alu_0_DW01_add_481' + Mapping 'VX_alu_0_DW01_add_482' + Mapping 'VX_alu_0_DW01_add_483' + Mapping 'VX_alu_0_DW01_sub_3' + Mapping 'VX_alu_0_DW01_add_484' + Mapping 'VX_alu_0_DW01_add_485' + Mapping 'VX_alu_0_DW01_add_486' + Mapping 'VX_alu_0_DW01_add_491' + Mapping 'VX_alu_0_DW01_add_492' + Mapping 'VX_alu_0_DW01_add_493' + Mapping 'VX_alu_0_DW01_add_494' + Mapping 'VX_alu_0_DW01_add_495' + Mapping 'VX_alu_0_DW01_add_496' + Mapping 'VX_alu_0_DW01_add_497' + Mapping 'VX_alu_0_DW01_add_498' + Mapping 'VX_alu_0_DW01_add_499' + Mapping 'VX_alu_0_DW01_add_500' + Mapping 'VX_alu_0_DW01_add_501' + Mapping 'VX_alu_0_DW01_add_502' + Mapping 'VX_alu_0_DW01_add_503' + Mapping 'VX_alu_0_DW01_add_504' + Mapping 'VX_alu_0_DW01_add_505' + Mapping 'VX_alu_0_DW01_add_506' + Mapping 'VX_alu_0_DW01_add_507' + Mapping 'VX_alu_0_DW01_add_508' + Mapping 'VX_alu_0_DW01_add_509' + Mapping 'VX_alu_0_DW01_add_510' + Mapping 'VX_alu_0_DW01_add_511' + Mapping 'VX_alu_0_DW01_add_512' + Mapping 'VX_alu_0_DW01_add_513' + Mapping 'VX_alu_0_DW01_add_514' + Mapping 'VX_alu_0_DW01_add_515' + Mapping 'VX_alu_0_DW01_add_516' + Mapping 'VX_alu_0_DW01_add_517' + Mapping 'VX_alu_0_DW01_add_518' + Mapping 'VX_alu_0_DW01_add_519' + Mapping 'VX_alu_0_DW01_add_520' + Mapping 'VX_alu_0_DW01_add_521' + Mapping 'VX_alu_0_DW01_add_522' + Mapping 'VX_alu_0_DW01_add_523' + Mapping 'VX_alu_0_DW01_add_524' + Mapping 'VX_alu_0_DW01_add_525' + Mapping 'VX_alu_0_DW01_add_526' + Mapping 'VX_alu_0_DW01_add_527' + Mapping 'VX_alu_0_DW01_add_528' + Mapping 'VX_alu_0_DW01_add_529' + Mapping 'VX_alu_0_DW01_add_530' + Mapping 'VX_alu_0_DW01_add_531' + Mapping 'VX_alu_0_DW01_add_532' + Mapping 'VX_alu_0_DW01_add_533' + Mapping 'VX_alu_0_DW01_add_534' + Mapping 'VX_alu_0_DW01_add_535' + Mapping 'VX_alu_0_DW01_add_536' + Mapping 'VX_alu_0_DW01_add_537' + Mapping 'VX_alu_0_DW01_add_538' + Mapping 'VX_alu_0_DW01_add_539' + Mapping 'VX_alu_0_DW01_add_540' + Mapping 'VX_alu_0_DW01_add_541' + Mapping 'VX_alu_0_DW01_add_542' + Mapping 'VX_alu_0_DW01_add_543' + Mapping 'VX_alu_0_DW01_add_544' + Mapping 'VX_alu_0_DW01_add_545' + Mapping 'VX_alu_0_DW01_add_546' + Mapping 'VX_alu_0_DW01_add_547' + Mapping 'VX_alu_0_DW01_add_548' + Mapping 'VX_alu_0_DW01_add_549' + Mapping 'VX_alu_0_DW01_add_550' + Mapping 'VX_alu_0_DW01_add_551' + Mapping 'VX_alu_0_DW01_add_552' + Mapping 'VX_alu_0_DW01_add_553' + Mapping 'VX_alu_0_DW01_add_554' + Mapping 'VX_alu_0_DW01_add_555' + Mapping 'VX_alu_0_DW01_add_556' + Mapping 'VX_alu_0_DW01_add_557' + Mapping 'VX_alu_0_DW01_add_558' + Mapping 'VX_alu_0_DW01_add_559' + Mapping 'VX_alu_0_DW01_add_560' + Mapping 'VX_alu_0_DW_div_uns_6' + Structuring 'VX_alu_1_DW_div_uns_3' + Mapping 'VX_alu_1_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_334' + Mapping 'VX_alu_1_DW01_add_335' + Mapping 'VX_alu_1_DW01_add_336' + Mapping 'VX_alu_1_DW01_add_337' + Mapping 'VX_alu_1_DW01_add_338' + Mapping 'VX_alu_1_DW01_add_339' + Mapping 'VX_alu_1_DW01_add_340' + Mapping 'VX_alu_1_DW01_add_341' + Mapping 'VX_alu_1_DW01_add_342' + Mapping 'VX_alu_1_DW01_add_343' + Mapping 'VX_alu_1_DW01_add_344' + Mapping 'VX_alu_1_DW01_add_345' + Mapping 'VX_alu_1_DW01_add_346' + Mapping 'VX_alu_1_DW01_add_347' + Mapping 'VX_alu_1_DW01_add_348' + Mapping 'VX_alu_1_DW01_add_349' + Mapping 'VX_alu_1_DW01_add_350' + Mapping 'VX_alu_1_DW01_add_351' + Mapping 'VX_alu_1_DW01_add_352' + Mapping 'VX_alu_1_DW01_add_353' + Mapping 'VX_alu_1_DW01_add_354' + Mapping 'VX_alu_1_DW01_add_355' + Mapping 'VX_alu_1_DW01_add_356' + Mapping 'VX_alu_1_DW01_add_357' + Mapping 'VX_alu_1_DW01_add_358' + Mapping 'VX_alu_1_DW01_add_359' + Mapping 'VX_alu_1_DW01_add_360' + Structuring 'VX_alu_1_DW_div_uns_4' + Mapping 'VX_alu_1_DW_div_uns_4' + Mapping 'VX_alu_1_DW01_add_361' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_362' + Mapping 'VX_alu_1_DW01_add_363' + Mapping 'VX_alu_1_DW01_add_364' + Mapping 'VX_alu_1_DW01_add_365' + Mapping 'VX_alu_1_DW01_add_366' + Mapping 'VX_alu_1_DW01_add_367' + Mapping 'VX_alu_1_DW01_add_368' + Mapping 'VX_alu_1_DW01_add_369' + Mapping 'VX_alu_1_DW01_add_370' + Mapping 'VX_alu_1_DW01_add_371' + Mapping 'VX_alu_1_DW01_add_372' + Mapping 'VX_alu_1_DW01_add_373' + Mapping 'VX_alu_1_DW01_add_374' + Mapping 'VX_alu_1_DW01_add_375' + Mapping 'VX_alu_1_DW01_add_376' + Mapping 'VX_alu_1_DW01_add_377' + Mapping 'VX_alu_1_DW01_add_378' + Mapping 'VX_alu_1_DW01_add_379' + Mapping 'VX_alu_1_DW01_add_380' + Mapping 'VX_alu_1_DW01_add_381' + Mapping 'VX_alu_1_DW01_add_382' + Mapping 'VX_alu_1_DW01_add_383' + Mapping 'VX_alu_1_DW01_add_384' + Mapping 'VX_alu_1_DW01_add_385' + Mapping 'VX_alu_1_DW01_add_386' + Mapping 'VX_alu_1_DW01_add_387' + Mapping 'VX_alu_1_DW01_add_388' + Mapping 'VX_alu_1_DW01_add_389' + Mapping 'VX_alu_1_DW01_add_390' + Mapping 'VX_alu_1_DW01_add_391' + Mapping 'VX_alu_1_DW01_add_392' + Mapping 'VX_alu_1_DW01_add_393' + Mapping 'VX_alu_1_DW01_add_394' + Mapping 'VX_alu_1_DW01_add_395' + Mapping 'VX_alu_1_DW01_add_396' + Mapping 'VX_alu_1_DW01_add_397' + Mapping 'VX_alu_1_DW01_add_398' + Mapping 'VX_alu_1_DW01_add_399' + Mapping 'VX_alu_1_DW01_add_400' + Structuring 'VX_alu_1_DW_div_uns_5' + Mapping 'VX_alu_1_DW_div_uns_5' + Mapping 'VX_alu_1_DW01_add_401' + Mapping 'VX_alu_1_DW01_add_402' + Mapping 'VX_alu_1_DW01_add_403' + Mapping 'VX_alu_1_DW01_sub_2' + Mapping 'VX_alu_1_DW01_add_404' + Mapping 'VX_alu_1_DW01_add_405' + Mapping 'VX_alu_1_DW01_add_406' + Mapping 'VX_alu_1_DW01_add_411' + Mapping 'VX_alu_1_DW01_add_412' + Mapping 'VX_alu_1_DW01_add_413' + Mapping 'VX_alu_1_DW01_add_414' + Mapping 'VX_alu_1_DW01_add_415' + Mapping 'VX_alu_1_DW01_add_416' + Mapping 'VX_alu_1_DW01_add_417' + Mapping 'VX_alu_1_DW01_add_418' + Mapping 'VX_alu_1_DW01_add_419' + Mapping 'VX_alu_1_DW01_add_420' + Mapping 'VX_alu_1_DW01_add_421' + Mapping 'VX_alu_1_DW01_add_422' + Mapping 'VX_alu_1_DW01_add_423' + Mapping 'VX_alu_1_DW01_add_424' + Mapping 'VX_alu_1_DW01_add_425' + Mapping 'VX_alu_1_DW01_add_426' + Mapping 'VX_alu_1_DW01_add_427' + Mapping 'VX_alu_1_DW01_add_428' + Mapping 'VX_alu_1_DW01_add_429' + Mapping 'VX_alu_1_DW01_add_430' + Mapping 'VX_alu_1_DW01_add_431' + Mapping 'VX_alu_1_DW01_add_432' + Mapping 'VX_alu_1_DW01_add_433' + Mapping 'VX_alu_1_DW01_add_434' + Mapping 'VX_alu_1_DW01_add_435' + Mapping 'VX_alu_1_DW01_add_436' + Mapping 'VX_alu_1_DW01_add_437' + Mapping 'VX_alu_1_DW01_add_438' + Mapping 'VX_alu_1_DW01_add_439' + Mapping 'VX_alu_1_DW01_add_440' + Mapping 'VX_alu_1_DW01_add_441' + Mapping 'VX_alu_1_DW01_add_442' + Mapping 'VX_alu_1_DW01_add_443' + Mapping 'VX_alu_1_DW01_add_444' + Mapping 'VX_alu_1_DW01_add_445' + Mapping 'VX_alu_1_DW01_add_446' + Mapping 'VX_alu_1_DW01_add_447' + Mapping 'VX_alu_1_DW01_add_448' + Mapping 'VX_alu_1_DW01_add_449' + Mapping 'VX_alu_1_DW01_add_450' + Mapping 'VX_alu_1_DW01_add_451' + Mapping 'VX_alu_1_DW01_add_452' + Mapping 'VX_alu_1_DW01_add_453' + Mapping 'VX_alu_1_DW01_add_454' + Mapping 'VX_alu_1_DW01_add_455' + Mapping 'VX_alu_1_DW01_add_456' + Mapping 'VX_alu_1_DW01_add_457' + Mapping 'VX_alu_1_DW01_add_458' + Mapping 'VX_alu_1_DW01_add_459' + Mapping 'VX_alu_1_DW01_add_460' + Mapping 'VX_alu_1_DW01_add_461' + Mapping 'VX_alu_1_DW01_add_462' + Mapping 'VX_alu_1_DW01_add_463' + Mapping 'VX_alu_1_DW01_add_464' + Mapping 'VX_alu_1_DW01_add_465' + Mapping 'VX_alu_1_DW01_add_466' + Mapping 'VX_alu_1_DW01_add_467' + Mapping 'VX_alu_1_DW01_add_468' + Mapping 'VX_alu_1_DW01_add_469' + Mapping 'VX_alu_1_DW01_add_470' + Mapping 'VX_alu_1_DW01_add_471' + Mapping 'VX_alu_1_DW01_add_472' + Mapping 'VX_alu_1_DW01_add_473' + Mapping 'VX_alu_1_DW01_add_474' + Mapping 'VX_alu_1_DW01_add_475' + Mapping 'VX_alu_1_DW01_add_476' + Mapping 'VX_alu_1_DW01_add_477' + Mapping 'VX_alu_1_DW01_add_478' + Mapping 'VX_alu_1_DW01_add_479' + Mapping 'VX_alu_1_DW01_add_480' + Structuring 'VX_alu_1_DW_div_uns_6' + Mapping 'VX_alu_1_DW_div_uns_6' + Mapping 'VX_alu_1_DW01_add_481' + Mapping 'VX_alu_1_DW01_add_482' + Mapping 'VX_alu_1_DW01_add_483' + Mapping 'VX_alu_1_DW01_sub_3' + Mapping 'VX_alu_1_DW01_add_484' + Mapping 'VX_alu_1_DW01_add_485' + Mapping 'VX_alu_1_DW01_add_486' + Mapping 'VX_alu_1_DW01_add_491' + Mapping 'VX_alu_1_DW01_add_492' + Mapping 'VX_alu_1_DW01_add_493' + Mapping 'VX_alu_1_DW01_add_494' + Mapping 'VX_alu_1_DW01_add_495' + Mapping 'VX_alu_1_DW01_add_496' + Mapping 'VX_alu_1_DW01_add_497' + Mapping 'VX_alu_1_DW01_add_498' + Mapping 'VX_alu_1_DW01_add_499' + Mapping 'VX_alu_1_DW01_add_500' + Mapping 'VX_alu_1_DW01_add_501' + Mapping 'VX_alu_1_DW01_add_502' + Mapping 'VX_alu_1_DW01_add_503' + Mapping 'VX_alu_1_DW01_add_504' + Mapping 'VX_alu_1_DW01_add_505' + Mapping 'VX_alu_1_DW01_add_506' + Mapping 'VX_alu_1_DW01_add_507' + Mapping 'VX_alu_1_DW01_add_508' + Mapping 'VX_alu_1_DW01_add_509' + Mapping 'VX_alu_1_DW01_add_510' + Mapping 'VX_alu_1_DW01_add_511' + Mapping 'VX_alu_1_DW01_add_512' + Mapping 'VX_alu_1_DW01_add_513' + Mapping 'VX_alu_1_DW01_add_514' + Mapping 'VX_alu_1_DW01_add_515' + Mapping 'VX_alu_1_DW01_add_516' + Mapping 'VX_alu_1_DW01_add_517' + Mapping 'VX_alu_1_DW01_add_518' + Mapping 'VX_alu_1_DW01_add_519' + Mapping 'VX_alu_1_DW01_add_520' + Mapping 'VX_alu_1_DW01_add_521' + Mapping 'VX_alu_1_DW01_add_522' + Mapping 'VX_alu_1_DW01_add_523' + Mapping 'VX_alu_1_DW01_add_524' + Mapping 'VX_alu_1_DW01_add_525' + Mapping 'VX_alu_1_DW01_add_526' + Mapping 'VX_alu_1_DW01_add_527' + Mapping 'VX_alu_1_DW01_add_528' + Mapping 'VX_alu_1_DW01_add_529' + Mapping 'VX_alu_1_DW01_add_530' + Mapping 'VX_alu_1_DW01_add_531' + Mapping 'VX_alu_1_DW01_add_532' + Mapping 'VX_alu_1_DW01_add_533' + Mapping 'VX_alu_1_DW01_add_534' + Mapping 'VX_alu_1_DW01_add_535' + Mapping 'VX_alu_1_DW01_add_536' + Mapping 'VX_alu_1_DW01_add_537' + Mapping 'VX_alu_1_DW01_add_538' + Mapping 'VX_alu_1_DW01_add_539' + Mapping 'VX_alu_1_DW01_add_540' + Mapping 'VX_alu_1_DW01_add_541' + Mapping 'VX_alu_1_DW01_add_542' + Mapping 'VX_alu_1_DW01_add_543' + Mapping 'VX_alu_1_DW01_add_544' + Mapping 'VX_alu_1_DW01_add_545' + Mapping 'VX_alu_1_DW01_add_546' + Mapping 'VX_alu_1_DW01_add_547' + Mapping 'VX_alu_1_DW01_add_548' + Mapping 'VX_alu_1_DW01_add_549' + Mapping 'VX_alu_1_DW01_add_550' + Mapping 'VX_alu_1_DW01_add_551' + Mapping 'VX_alu_1_DW01_add_552' + Mapping 'VX_alu_1_DW01_add_553' + Mapping 'VX_alu_1_DW01_add_554' + Mapping 'VX_alu_1_DW01_add_555' + Mapping 'VX_alu_1_DW01_add_556' + Mapping 'VX_alu_1_DW01_add_557' + Mapping 'VX_alu_1_DW01_add_558' + Mapping 'VX_alu_1_DW01_add_559' + Mapping 'VX_alu_1_DW01_add_560' + Mapping 'VX_alu_1_DW_div_uns_6' + Structuring 'VX_alu_2_DW_div_uns_3' + Mapping 'VX_alu_2_DW_div_uns_3' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_334' + Mapping 'VX_alu_2_DW01_add_335' + Mapping 'VX_alu_2_DW01_add_336' + Mapping 'VX_alu_2_DW01_add_337' + Mapping 'VX_alu_2_DW01_add_338' + Mapping 'VX_alu_2_DW01_add_339' + Mapping 'VX_alu_2_DW01_add_340' + Mapping 'VX_alu_2_DW01_add_341' + Mapping 'VX_alu_2_DW01_add_342' + Mapping 'VX_alu_2_DW01_add_343' + Mapping 'VX_alu_2_DW01_add_344' + Mapping 'VX_alu_2_DW01_add_345' + Mapping 'VX_alu_2_DW01_add_346' + Mapping 'VX_alu_2_DW01_add_347' + Mapping 'VX_alu_2_DW01_add_348' + Mapping 'VX_alu_2_DW01_add_349' + Mapping 'VX_alu_2_DW01_add_350' + Mapping 'VX_alu_2_DW01_add_351' + Mapping 'VX_alu_2_DW01_add_352' + Mapping 'VX_alu_2_DW01_add_353' + Mapping 'VX_alu_2_DW01_add_354' + Mapping 'VX_alu_2_DW01_add_355' + Mapping 'VX_alu_2_DW01_add_356' + Mapping 'VX_alu_2_DW01_add_357' + Mapping 'VX_alu_2_DW01_add_358' + Mapping 'VX_alu_2_DW01_add_359' + Mapping 'VX_alu_2_DW01_add_360' + Structuring 'VX_alu_2_DW_div_uns_4' + Mapping 'VX_alu_2_DW_div_uns_4' + Mapping 'VX_alu_2_DW01_add_361' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_362' + Mapping 'VX_alu_2_DW01_add_363' + Mapping 'VX_alu_2_DW01_add_364' + Mapping 'VX_alu_2_DW01_add_365' + Mapping 'VX_alu_2_DW01_add_366' + Mapping 'VX_alu_2_DW01_add_367' + Mapping 'VX_alu_2_DW01_add_368' + Mapping 'VX_alu_2_DW01_add_369' + Mapping 'VX_alu_2_DW01_add_370' + Mapping 'VX_alu_2_DW01_add_371' + Mapping 'VX_alu_2_DW01_add_372' + Mapping 'VX_alu_2_DW01_add_373' + Mapping 'VX_alu_2_DW01_add_374' + Mapping 'VX_alu_2_DW01_add_375' + Mapping 'VX_alu_2_DW01_add_376' + Mapping 'VX_alu_2_DW01_add_377' + Mapping 'VX_alu_2_DW01_add_378' + Mapping 'VX_alu_2_DW01_add_379' + Mapping 'VX_alu_2_DW01_add_380' + Mapping 'VX_alu_2_DW01_add_381' + Mapping 'VX_alu_2_DW01_add_382' + Mapping 'VX_alu_2_DW01_add_383' + Mapping 'VX_alu_2_DW01_add_384' + Mapping 'VX_alu_2_DW01_add_385' + Mapping 'VX_alu_2_DW01_add_386' + Mapping 'VX_alu_2_DW01_add_387' + Mapping 'VX_alu_2_DW01_add_388' + Mapping 'VX_alu_2_DW01_add_389' + Mapping 'VX_alu_2_DW01_add_390' + Mapping 'VX_alu_2_DW01_add_391' + Mapping 'VX_alu_2_DW01_add_392' + Mapping 'VX_alu_2_DW01_add_393' + Mapping 'VX_alu_2_DW01_add_394' + Mapping 'VX_alu_2_DW01_add_395' + Mapping 'VX_alu_2_DW01_add_396' + Mapping 'VX_alu_2_DW01_add_397' + Mapping 'VX_alu_2_DW01_add_398' + Mapping 'VX_alu_2_DW01_add_399' + Mapping 'VX_alu_2_DW01_add_400' + Structuring 'VX_alu_2_DW_div_uns_5' + Mapping 'VX_alu_2_DW_div_uns_5' + Mapping 'VX_alu_2_DW01_add_401' + Mapping 'VX_alu_2_DW01_add_402' + Mapping 'VX_alu_2_DW01_add_403' + Mapping 'VX_alu_2_DW01_sub_2' + Mapping 'VX_alu_2_DW01_add_404' + Mapping 'VX_alu_2_DW01_add_405' + Mapping 'VX_alu_2_DW01_add_406' + Mapping 'VX_alu_2_DW01_add_411' + Mapping 'VX_alu_2_DW01_add_412' + Mapping 'VX_alu_2_DW01_add_413' + Mapping 'VX_alu_2_DW01_add_414' + Mapping 'VX_alu_2_DW01_add_415' + Mapping 'VX_alu_2_DW01_add_416' + Mapping 'VX_alu_2_DW01_add_417' + Mapping 'VX_alu_2_DW01_add_418' + Mapping 'VX_alu_2_DW01_add_419' + Mapping 'VX_alu_2_DW01_add_420' + Mapping 'VX_alu_2_DW01_add_421' + Mapping 'VX_alu_2_DW01_add_422' + Mapping 'VX_alu_2_DW01_add_423' + Mapping 'VX_alu_2_DW01_add_424' + Mapping 'VX_alu_2_DW01_add_425' + Mapping 'VX_alu_2_DW01_add_426' + Mapping 'VX_alu_2_DW01_add_427' + Mapping 'VX_alu_2_DW01_add_428' + Mapping 'VX_alu_2_DW01_add_429' + Mapping 'VX_alu_2_DW01_add_430' + Mapping 'VX_alu_2_DW01_add_431' + Mapping 'VX_alu_2_DW01_add_432' + Mapping 'VX_alu_2_DW01_add_433' + Mapping 'VX_alu_2_DW01_add_434' + Mapping 'VX_alu_2_DW01_add_435' + Mapping 'VX_alu_2_DW01_add_436' + Mapping 'VX_alu_2_DW01_add_437' + Mapping 'VX_alu_2_DW01_add_438' + Mapping 'VX_alu_2_DW01_add_439' + Mapping 'VX_alu_2_DW01_add_440' + Mapping 'VX_alu_2_DW01_add_441' + Mapping 'VX_alu_2_DW01_add_442' + Mapping 'VX_alu_2_DW01_add_443' + Mapping 'VX_alu_2_DW01_add_444' + Mapping 'VX_alu_2_DW01_add_445' + Mapping 'VX_alu_2_DW01_add_446' + Mapping 'VX_alu_2_DW01_add_447' + Mapping 'VX_alu_2_DW01_add_448' + Mapping 'VX_alu_2_DW01_add_449' + Mapping 'VX_alu_2_DW01_add_450' + Mapping 'VX_alu_2_DW01_add_451' + Mapping 'VX_alu_2_DW01_add_452' + Mapping 'VX_alu_2_DW01_add_453' + Mapping 'VX_alu_2_DW01_add_454' + Mapping 'VX_alu_2_DW01_add_455' + Mapping 'VX_alu_2_DW01_add_456' + Mapping 'VX_alu_2_DW01_add_457' + Mapping 'VX_alu_2_DW01_add_458' + Mapping 'VX_alu_2_DW01_add_459' + Mapping 'VX_alu_2_DW01_add_460' + Mapping 'VX_alu_2_DW01_add_461' + Mapping 'VX_alu_2_DW01_add_462' + Mapping 'VX_alu_2_DW01_add_463' + Mapping 'VX_alu_2_DW01_add_464' + Mapping 'VX_alu_2_DW01_add_465' + Mapping 'VX_alu_2_DW01_add_466' + Mapping 'VX_alu_2_DW01_add_467' + Mapping 'VX_alu_2_DW01_add_468' + Mapping 'VX_alu_2_DW01_add_469' + Mapping 'VX_alu_2_DW01_add_470' + Mapping 'VX_alu_2_DW01_add_471' + Mapping 'VX_alu_2_DW01_add_472' + Mapping 'VX_alu_2_DW01_add_473' + Mapping 'VX_alu_2_DW01_add_474' + Mapping 'VX_alu_2_DW01_add_475' + Mapping 'VX_alu_2_DW01_add_476' + Mapping 'VX_alu_2_DW01_add_477' + Mapping 'VX_alu_2_DW01_add_478' + Mapping 'VX_alu_2_DW01_add_479' + Mapping 'VX_alu_2_DW01_add_480' + Structuring 'VX_alu_2_DW_div_uns_6' + Mapping 'VX_alu_2_DW_div_uns_6' + Mapping 'VX_alu_2_DW01_add_481' + Mapping 'VX_alu_2_DW01_add_482' + Mapping 'VX_alu_2_DW01_add_483' + Mapping 'VX_alu_2_DW01_sub_3' + Mapping 'VX_alu_2_DW01_add_484' + Mapping 'VX_alu_2_DW01_add_485' + Mapping 'VX_alu_2_DW01_add_486' + Mapping 'VX_alu_2_DW01_add_491' + Mapping 'VX_alu_2_DW01_add_492' + Mapping 'VX_alu_2_DW01_add_493' + Mapping 'VX_alu_2_DW01_add_494' + Mapping 'VX_alu_2_DW01_add_495' + Mapping 'VX_alu_2_DW01_add_496' + Mapping 'VX_alu_2_DW01_add_497' + Mapping 'VX_alu_2_DW01_add_498' + Mapping 'VX_alu_2_DW01_add_499' + Mapping 'VX_alu_2_DW01_add_500' + Mapping 'VX_alu_2_DW01_add_501' + Mapping 'VX_alu_2_DW01_add_502' + Mapping 'VX_alu_2_DW01_add_503' + Mapping 'VX_alu_2_DW01_add_504' + Mapping 'VX_alu_2_DW01_add_505' + Mapping 'VX_alu_2_DW01_add_506' + Mapping 'VX_alu_2_DW01_add_507' + Mapping 'VX_alu_2_DW01_add_508' + Mapping 'VX_alu_2_DW01_add_509' + Mapping 'VX_alu_2_DW01_add_510' + Mapping 'VX_alu_2_DW01_add_511' + Mapping 'VX_alu_2_DW01_add_512' + Mapping 'VX_alu_2_DW01_add_513' + Mapping 'VX_alu_2_DW01_add_514' + Mapping 'VX_alu_2_DW01_add_515' + Mapping 'VX_alu_2_DW01_add_516' + Mapping 'VX_alu_2_DW01_add_517' + Mapping 'VX_alu_2_DW01_add_518' + Mapping 'VX_alu_2_DW01_add_519' + Mapping 'VX_alu_2_DW01_add_520' + Mapping 'VX_alu_2_DW01_add_521' + Mapping 'VX_alu_2_DW01_add_522' + Mapping 'VX_alu_2_DW01_add_523' + Mapping 'VX_alu_2_DW01_add_524' + Mapping 'VX_alu_2_DW01_add_525' + Mapping 'VX_alu_2_DW01_add_526' + Mapping 'VX_alu_2_DW01_add_527' + Mapping 'VX_alu_2_DW01_add_528' + Mapping 'VX_alu_2_DW01_add_529' + Mapping 'VX_alu_2_DW01_add_530' + Mapping 'VX_alu_2_DW01_add_531' + Mapping 'VX_alu_2_DW01_add_532' + Mapping 'VX_alu_2_DW01_add_533' + Mapping 'VX_alu_2_DW01_add_534' + Mapping 'VX_alu_2_DW01_add_535' + Mapping 'VX_alu_2_DW01_add_536' + Mapping 'VX_alu_2_DW01_add_537' + Mapping 'VX_alu_2_DW01_add_538' + Mapping 'VX_alu_2_DW01_add_539' + Mapping 'VX_alu_2_DW01_add_540' + Mapping 'VX_alu_2_DW01_add_541' + Mapping 'VX_alu_2_DW01_add_542' + Mapping 'VX_alu_2_DW01_add_543' + Mapping 'VX_alu_2_DW01_add_544' + Mapping 'VX_alu_2_DW01_add_545' + Mapping 'VX_alu_2_DW01_add_546' + Mapping 'VX_alu_2_DW01_add_547' + Mapping 'VX_alu_2_DW01_add_548' + Mapping 'VX_alu_2_DW01_add_549' + Mapping 'VX_alu_2_DW01_add_550' + Mapping 'VX_alu_2_DW01_add_551' + Mapping 'VX_alu_2_DW01_add_552' + Mapping 'VX_alu_2_DW01_add_553' + Mapping 'VX_alu_2_DW01_add_554' + Mapping 'VX_alu_2_DW01_add_555' + Mapping 'VX_alu_2_DW01_add_556' + Mapping 'VX_alu_2_DW01_add_557' + Mapping 'VX_alu_2_DW01_add_558' + Mapping 'VX_alu_2_DW01_add_559' + Mapping 'VX_alu_2_DW01_add_560' + Mapping 'VX_alu_2_DW_div_uns_6' + Structuring 'VX_alu_0_DW_div_tc_4' + Mapping 'VX_alu_0_DW_div_tc_4' + Structuring 'VX_alu_0_DW01_absval_4' + Mapping 'VX_alu_0_DW01_absval_4' + Structuring 'VX_alu_0_DW01_inc_4' + Mapping 'VX_alu_0_DW01_inc_4' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_561' + Mapping 'VX_alu_0_DW01_add_562' + Mapping 'VX_alu_0_DW01_add_563' + Mapping 'VX_alu_0_DW01_add_564' + Mapping 'VX_alu_0_DW01_add_565' + Mapping 'VX_alu_0_DW01_add_566' + Mapping 'VX_alu_0_DW01_add_567' + Mapping 'VX_alu_0_DW01_add_568' + Mapping 'VX_alu_0_DW01_add_569' + Mapping 'VX_alu_0_DW01_add_570' + Mapping 'VX_alu_0_DW01_add_571' + Mapping 'VX_alu_0_DW01_add_572' + Mapping 'VX_alu_0_DW01_add_573' + Mapping 'VX_alu_0_DW01_add_574' + Mapping 'VX_alu_0_DW01_add_575' + Mapping 'VX_alu_0_DW01_add_576' + Mapping 'VX_alu_0_DW01_add_577' + Mapping 'VX_alu_0_DW01_add_578' + Mapping 'VX_alu_0_DW01_add_579' + Mapping 'VX_alu_0_DW01_add_580' + Mapping 'VX_alu_0_DW01_add_581' + Mapping 'VX_alu_0_DW01_add_582' + Mapping 'VX_alu_0_DW01_add_583' + Mapping 'VX_alu_0_DW01_add_584' + Mapping 'VX_alu_0_DW01_add_585' + Mapping 'VX_alu_0_DW01_add_586' + Mapping 'VX_alu_0_DW01_add_587' + Mapping 'VX_alu_0_DW_inc_8' + Structuring 'VX_alu_0_DW_div_tc_5' + Mapping 'VX_alu_0_DW_div_tc_5' + Structuring 'VX_alu_0_DW01_absval_5' + Mapping 'VX_alu_0_DW01_absval_5' + Structuring 'VX_alu_0_DW01_inc_5' + Mapping 'VX_alu_0_DW01_inc_5' + Mapping 'VX_alu_0_DW01_add_588' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_589' + Mapping 'VX_alu_0_DW01_add_590' + Mapping 'VX_alu_0_DW01_add_591' + Mapping 'VX_alu_0_DW01_add_592' + Mapping 'VX_alu_0_DW01_add_593' + Mapping 'VX_alu_0_DW01_add_594' + Mapping 'VX_alu_0_DW01_add_595' + Mapping 'VX_alu_0_DW01_add_596' + Mapping 'VX_alu_0_DW01_add_597' + Mapping 'VX_alu_0_DW01_add_598' + Mapping 'VX_alu_0_DW01_add_599' + Mapping 'VX_alu_0_DW01_add_600' + Mapping 'VX_alu_0_DW01_add_601' + Mapping 'VX_alu_0_DW01_add_602' + Mapping 'VX_alu_0_DW01_add_603' + Mapping 'VX_alu_0_DW01_add_604' + Mapping 'VX_alu_0_DW01_add_605' + Mapping 'VX_alu_0_DW01_add_606' + Mapping 'VX_alu_0_DW01_add_607' + Mapping 'VX_alu_0_DW01_add_608' + Mapping 'VX_alu_0_DW01_add_609' + Mapping 'VX_alu_0_DW01_add_610' + Mapping 'VX_alu_0_DW01_add_611' + Mapping 'VX_alu_0_DW01_add_612' + Mapping 'VX_alu_0_DW01_add_613' + Mapping 'VX_alu_0_DW01_add_614' + Mapping 'VX_alu_0_DW01_add_615' + Mapping 'VX_alu_0_DW01_add_616' + Mapping 'VX_alu_0_DW01_add_617' + Mapping 'VX_alu_0_DW01_add_618' + Mapping 'VX_alu_0_DW01_add_619' + Mapping 'VX_alu_0_DW01_add_620' + Mapping 'VX_alu_0_DW01_add_621' + Mapping 'VX_alu_0_DW01_add_622' + Mapping 'VX_alu_0_DW01_add_623' + Mapping 'VX_alu_0_DW01_add_624' + Mapping 'VX_alu_0_DW01_add_625' + Mapping 'VX_alu_0_DW01_add_626' + Mapping 'VX_alu_0_DW01_add_627' + Mapping 'VX_alu_0_DW_inc_10' + Structuring 'VX_alu_0_DW_div_tc_6' + Mapping 'VX_alu_0_DW_div_tc_6' + Structuring 'VX_alu_0_DW01_absval_6' + Mapping 'VX_alu_0_DW01_absval_6' + Structuring 'VX_alu_0_DW01_inc_6' + Mapping 'VX_alu_0_DW01_inc_6' + Mapping 'VX_alu_0_DW01_add_628' + Mapping 'VX_alu_0_DW01_add_629' + Mapping 'VX_alu_0_DW01_add_630' + Mapping 'VX_alu_0_DW01_sub_4' + Mapping 'VX_alu_0_DW01_add_631' + Mapping 'VX_alu_0_DW01_add_632' + Mapping 'VX_alu_0_DW01_add_633' + Mapping 'VX_alu_0_DW01_add_638' + Mapping 'VX_alu_0_DW01_add_639' + Mapping 'VX_alu_0_DW01_add_640' + Mapping 'VX_alu_0_DW01_add_641' + Mapping 'VX_alu_0_DW01_add_642' + Mapping 'VX_alu_0_DW01_add_643' + Mapping 'VX_alu_0_DW01_add_644' + Mapping 'VX_alu_0_DW01_add_645' + Mapping 'VX_alu_0_DW01_add_646' + Mapping 'VX_alu_0_DW01_add_647' + Mapping 'VX_alu_0_DW01_add_648' + Mapping 'VX_alu_0_DW01_add_649' + Mapping 'VX_alu_0_DW01_add_650' + Mapping 'VX_alu_0_DW01_add_651' + Mapping 'VX_alu_0_DW01_add_652' + Mapping 'VX_alu_0_DW01_add_653' + Mapping 'VX_alu_0_DW01_add_654' + Mapping 'VX_alu_0_DW01_add_655' + Mapping 'VX_alu_0_DW01_add_656' + Mapping 'VX_alu_0_DW01_add_657' + Mapping 'VX_alu_0_DW01_add_658' + Mapping 'VX_alu_0_DW01_add_659' + Mapping 'VX_alu_0_DW01_add_660' + Mapping 'VX_alu_0_DW01_add_661' + Mapping 'VX_alu_0_DW01_add_662' + Mapping 'VX_alu_0_DW01_add_663' + Mapping 'VX_alu_0_DW01_add_664' + Mapping 'VX_alu_0_DW01_add_665' + Mapping 'VX_alu_0_DW01_add_666' + Mapping 'VX_alu_0_DW01_add_667' + Mapping 'VX_alu_0_DW01_add_668' + Mapping 'VX_alu_0_DW01_add_669' + Mapping 'VX_alu_0_DW01_add_670' + Mapping 'VX_alu_0_DW01_add_671' + Mapping 'VX_alu_0_DW01_add_672' + Mapping 'VX_alu_0_DW01_add_673' + Mapping 'VX_alu_0_DW01_add_674' + Mapping 'VX_alu_0_DW01_add_675' + Mapping 'VX_alu_0_DW01_add_676' + Mapping 'VX_alu_0_DW01_add_677' + Mapping 'VX_alu_0_DW01_add_678' + Mapping 'VX_alu_0_DW01_add_679' + Mapping 'VX_alu_0_DW01_add_680' + Mapping 'VX_alu_0_DW01_add_681' + Mapping 'VX_alu_0_DW01_add_682' + Mapping 'VX_alu_0_DW01_add_683' + Mapping 'VX_alu_0_DW01_add_684' + Mapping 'VX_alu_0_DW01_add_685' + Mapping 'VX_alu_0_DW01_add_686' + Mapping 'VX_alu_0_DW01_add_687' + Mapping 'VX_alu_0_DW01_add_688' + Mapping 'VX_alu_0_DW01_add_689' + Mapping 'VX_alu_0_DW01_add_690' + Mapping 'VX_alu_0_DW01_add_691' + Mapping 'VX_alu_0_DW01_add_692' + Mapping 'VX_alu_0_DW01_add_693' + Mapping 'VX_alu_0_DW01_add_694' + Mapping 'VX_alu_0_DW01_add_695' + Mapping 'VX_alu_0_DW01_add_696' + Mapping 'VX_alu_0_DW01_add_697' + Mapping 'VX_alu_0_DW01_add_698' + Mapping 'VX_alu_0_DW01_add_699' + Mapping 'VX_alu_0_DW01_add_700' + Mapping 'VX_alu_0_DW01_add_701' + Mapping 'VX_alu_0_DW01_add_702' + Mapping 'VX_alu_0_DW01_add_703' + Mapping 'VX_alu_0_DW01_add_704' + Mapping 'VX_alu_0_DW01_add_705' + Mapping 'VX_alu_0_DW01_add_706' + Mapping 'VX_alu_0_DW01_add_707' + Mapping 'VX_alu_0_DW_inc_12' + Structuring 'VX_alu_0_DW_div_tc_7' + Mapping 'VX_alu_0_DW_div_tc_7' + Structuring 'VX_alu_0_DW01_absval_7' + Mapping 'VX_alu_0_DW01_absval_7' + Structuring 'VX_alu_0_DW01_inc_7' + Mapping 'VX_alu_0_DW01_inc_7' + Mapping 'VX_alu_0_DW01_add_708' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_0_DW01_add_709' + Mapping 'VX_alu_0_DW01_add_710' + Mapping 'VX_alu_0_DW01_add_711' + Mapping 'VX_alu_0_DW01_add_712' + Mapping 'VX_alu_0_DW01_add_713' + Mapping 'VX_alu_0_DW01_add_714' + Mapping 'VX_alu_0_DW01_add_715' + Mapping 'VX_alu_0_DW01_add_716' + Mapping 'VX_alu_0_DW01_add_717' + Mapping 'VX_alu_0_DW01_add_718' + Mapping 'VX_alu_0_DW01_add_719' + Mapping 'VX_alu_0_DW01_add_720' + Mapping 'VX_alu_0_DW01_add_721' + Mapping 'VX_alu_0_DW01_add_722' + Mapping 'VX_alu_0_DW01_add_723' + Mapping 'VX_alu_0_DW01_add_724' + Mapping 'VX_alu_0_DW01_add_725' + Mapping 'VX_alu_0_DW01_add_726' + Mapping 'VX_alu_0_DW01_add_727' + Mapping 'VX_alu_0_DW01_add_728' + Mapping 'VX_alu_0_DW01_add_729' + Mapping 'VX_alu_0_DW01_add_730' + Mapping 'VX_alu_0_DW01_add_731' + Mapping 'VX_alu_0_DW01_add_732' + Mapping 'VX_alu_0_DW01_add_733' + Mapping 'VX_alu_0_DW01_add_734' + Mapping 'VX_alu_0_DW01_add_735' + Mapping 'VX_alu_0_DW01_add_736' + Mapping 'VX_alu_0_DW01_add_737' + Mapping 'VX_alu_0_DW01_add_738' + Mapping 'VX_alu_0_DW01_add_739' + Mapping 'VX_alu_0_DW01_add_740' + Mapping 'VX_alu_0_DW01_add_741' + Mapping 'VX_alu_0_DW01_add_742' + Mapping 'VX_alu_0_DW01_add_743' + Mapping 'VX_alu_0_DW01_add_744' + Mapping 'VX_alu_0_DW01_add_745' + Mapping 'VX_alu_0_DW01_add_746' + Mapping 'VX_alu_0_DW01_add_747' + Mapping 'VX_alu_0_DW_inc_14' + Mapping 'VX_alu_0_DW_div_tc_7' + Structuring 'VX_alu_1_DW_div_tc_4' + Mapping 'VX_alu_1_DW_div_tc_4' + Structuring 'VX_alu_1_DW01_absval_4' + Mapping 'VX_alu_1_DW01_absval_4' + Structuring 'VX_alu_1_DW01_inc_4' + Mapping 'VX_alu_1_DW01_inc_4' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_561' + Mapping 'VX_alu_1_DW01_add_562' + Mapping 'VX_alu_1_DW01_add_563' + Mapping 'VX_alu_1_DW01_add_564' + Mapping 'VX_alu_1_DW01_add_565' + Mapping 'VX_alu_1_DW01_add_566' + Mapping 'VX_alu_1_DW01_add_567' + Mapping 'VX_alu_1_DW01_add_568' + Mapping 'VX_alu_1_DW01_add_569' + Mapping 'VX_alu_1_DW01_add_570' + Mapping 'VX_alu_1_DW01_add_571' + Mapping 'VX_alu_1_DW01_add_572' + Mapping 'VX_alu_1_DW01_add_573' + Mapping 'VX_alu_1_DW01_add_574' + Mapping 'VX_alu_1_DW01_add_575' + Mapping 'VX_alu_1_DW01_add_576' + Mapping 'VX_alu_1_DW01_add_577' + Mapping 'VX_alu_1_DW01_add_578' + Mapping 'VX_alu_1_DW01_add_579' + Mapping 'VX_alu_1_DW01_add_580' + Mapping 'VX_alu_1_DW01_add_581' + Mapping 'VX_alu_1_DW01_add_582' + Mapping 'VX_alu_1_DW01_add_583' + Mapping 'VX_alu_1_DW01_add_584' + Mapping 'VX_alu_1_DW01_add_585' + Mapping 'VX_alu_1_DW01_add_586' + Mapping 'VX_alu_1_DW01_add_587' + Mapping 'VX_alu_1_DW_inc_8' + Structuring 'VX_alu_1_DW_div_tc_5' + Mapping 'VX_alu_1_DW_div_tc_5' + Structuring 'VX_alu_1_DW01_absval_5' + Mapping 'VX_alu_1_DW01_absval_5' + Structuring 'VX_alu_1_DW01_inc_5' + Mapping 'VX_alu_1_DW01_inc_5' + Mapping 'VX_alu_1_DW01_add_588' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_589' + Mapping 'VX_alu_1_DW01_add_590' + Mapping 'VX_alu_1_DW01_add_591' + Mapping 'VX_alu_1_DW01_add_592' + Mapping 'VX_alu_1_DW01_add_593' + Mapping 'VX_alu_1_DW01_add_594' + Mapping 'VX_alu_1_DW01_add_595' + Mapping 'VX_alu_1_DW01_add_596' + Mapping 'VX_alu_1_DW01_add_597' + Mapping 'VX_alu_1_DW01_add_598' + Mapping 'VX_alu_1_DW01_add_599' + Mapping 'VX_alu_1_DW01_add_600' + Mapping 'VX_alu_1_DW01_add_601' + Mapping 'VX_alu_1_DW01_add_602' + Mapping 'VX_alu_1_DW01_add_603' + Mapping 'VX_alu_1_DW01_add_604' + Mapping 'VX_alu_1_DW01_add_605' + Mapping 'VX_alu_1_DW01_add_606' + Mapping 'VX_alu_1_DW01_add_607' + Mapping 'VX_alu_1_DW01_add_608' + Mapping 'VX_alu_1_DW01_add_609' + Mapping 'VX_alu_1_DW01_add_610' + Mapping 'VX_alu_1_DW01_add_611' + Mapping 'VX_alu_1_DW01_add_612' + Mapping 'VX_alu_1_DW01_add_613' + Mapping 'VX_alu_1_DW01_add_614' + Mapping 'VX_alu_1_DW01_add_615' + Mapping 'VX_alu_1_DW01_add_616' + Mapping 'VX_alu_1_DW01_add_617' + Mapping 'VX_alu_1_DW01_add_618' + Mapping 'VX_alu_1_DW01_add_619' + Mapping 'VX_alu_1_DW01_add_620' + Mapping 'VX_alu_1_DW01_add_621' + Mapping 'VX_alu_1_DW01_add_622' + Mapping 'VX_alu_1_DW01_add_623' + Mapping 'VX_alu_1_DW01_add_624' + Mapping 'VX_alu_1_DW01_add_625' + Mapping 'VX_alu_1_DW01_add_626' + Mapping 'VX_alu_1_DW01_add_627' + Mapping 'VX_alu_1_DW_inc_10' + Structuring 'VX_alu_1_DW_div_tc_6' + Mapping 'VX_alu_1_DW_div_tc_6' + Structuring 'VX_alu_1_DW01_absval_6' + Mapping 'VX_alu_1_DW01_absval_6' + Structuring 'VX_alu_1_DW01_inc_6' + Mapping 'VX_alu_1_DW01_inc_6' + Mapping 'VX_alu_1_DW01_add_628' + Mapping 'VX_alu_1_DW01_add_629' + Mapping 'VX_alu_1_DW01_add_630' + Mapping 'VX_alu_1_DW01_sub_4' + Mapping 'VX_alu_1_DW01_add_631' + Mapping 'VX_alu_1_DW01_add_632' + Mapping 'VX_alu_1_DW01_add_633' + Mapping 'VX_alu_1_DW01_add_638' + Mapping 'VX_alu_1_DW01_add_639' + Mapping 'VX_alu_1_DW01_add_640' + Mapping 'VX_alu_1_DW01_add_641' + Mapping 'VX_alu_1_DW01_add_642' + Mapping 'VX_alu_1_DW01_add_643' + Mapping 'VX_alu_1_DW01_add_644' + Mapping 'VX_alu_1_DW01_add_645' + Mapping 'VX_alu_1_DW01_add_646' + Mapping 'VX_alu_1_DW01_add_647' + Mapping 'VX_alu_1_DW01_add_648' + Mapping 'VX_alu_1_DW01_add_649' + Mapping 'VX_alu_1_DW01_add_650' + Mapping 'VX_alu_1_DW01_add_651' + Mapping 'VX_alu_1_DW01_add_652' + Mapping 'VX_alu_1_DW01_add_653' + Mapping 'VX_alu_1_DW01_add_654' + Mapping 'VX_alu_1_DW01_add_655' + Mapping 'VX_alu_1_DW01_add_656' + Mapping 'VX_alu_1_DW01_add_657' + Mapping 'VX_alu_1_DW01_add_658' + Mapping 'VX_alu_1_DW01_add_659' + Mapping 'VX_alu_1_DW01_add_660' + Mapping 'VX_alu_1_DW01_add_661' + Mapping 'VX_alu_1_DW01_add_662' + Mapping 'VX_alu_1_DW01_add_663' + Mapping 'VX_alu_1_DW01_add_664' + Mapping 'VX_alu_1_DW01_add_665' + Mapping 'VX_alu_1_DW01_add_666' + Mapping 'VX_alu_1_DW01_add_667' + Mapping 'VX_alu_1_DW01_add_668' + Mapping 'VX_alu_1_DW01_add_669' + Mapping 'VX_alu_1_DW01_add_670' + Mapping 'VX_alu_1_DW01_add_671' + Mapping 'VX_alu_1_DW01_add_672' + Mapping 'VX_alu_1_DW01_add_673' + Mapping 'VX_alu_1_DW01_add_674' + Mapping 'VX_alu_1_DW01_add_675' + Mapping 'VX_alu_1_DW01_add_676' + Mapping 'VX_alu_1_DW01_add_677' + Mapping 'VX_alu_1_DW01_add_678' + Mapping 'VX_alu_1_DW01_add_679' + Mapping 'VX_alu_1_DW01_add_680' + Mapping 'VX_alu_1_DW01_add_681' + Mapping 'VX_alu_1_DW01_add_682' + Mapping 'VX_alu_1_DW01_add_683' + Mapping 'VX_alu_1_DW01_add_684' + Mapping 'VX_alu_1_DW01_add_685' + Mapping 'VX_alu_1_DW01_add_686' + Mapping 'VX_alu_1_DW01_add_687' + Mapping 'VX_alu_1_DW01_add_688' + Mapping 'VX_alu_1_DW01_add_689' + Mapping 'VX_alu_1_DW01_add_690' + Mapping 'VX_alu_1_DW01_add_691' + Mapping 'VX_alu_1_DW01_add_692' + Mapping 'VX_alu_1_DW01_add_693' + Mapping 'VX_alu_1_DW01_add_694' + Mapping 'VX_alu_1_DW01_add_695' + Mapping 'VX_alu_1_DW01_add_696' + Mapping 'VX_alu_1_DW01_add_697' + Mapping 'VX_alu_1_DW01_add_698' + Mapping 'VX_alu_1_DW01_add_699' + Mapping 'VX_alu_1_DW01_add_700' + Mapping 'VX_alu_1_DW01_add_701' + Mapping 'VX_alu_1_DW01_add_702' + Mapping 'VX_alu_1_DW01_add_703' + Mapping 'VX_alu_1_DW01_add_704' + Mapping 'VX_alu_1_DW01_add_705' + Mapping 'VX_alu_1_DW01_add_706' + Mapping 'VX_alu_1_DW01_add_707' + Mapping 'VX_alu_1_DW_inc_12' + Structuring 'VX_alu_1_DW_div_tc_7' + Mapping 'VX_alu_1_DW_div_tc_7' + Structuring 'VX_alu_1_DW01_absval_7' + Mapping 'VX_alu_1_DW01_absval_7' + Structuring 'VX_alu_1_DW01_inc_7' + Mapping 'VX_alu_1_DW01_inc_7' + Mapping 'VX_alu_1_DW01_add_708' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_1_DW01_add_709' + Mapping 'VX_alu_1_DW01_add_710' + Mapping 'VX_alu_1_DW01_add_711' + Mapping 'VX_alu_1_DW01_add_712' + Mapping 'VX_alu_1_DW01_add_713' + Mapping 'VX_alu_1_DW01_add_714' + Mapping 'VX_alu_1_DW01_add_715' + Mapping 'VX_alu_1_DW01_add_716' + Mapping 'VX_alu_1_DW01_add_717' + Mapping 'VX_alu_1_DW01_add_718' + Mapping 'VX_alu_1_DW01_add_719' + Mapping 'VX_alu_1_DW01_add_720' + Mapping 'VX_alu_1_DW01_add_721' + Mapping 'VX_alu_1_DW01_add_722' + Mapping 'VX_alu_1_DW01_add_723' + Mapping 'VX_alu_1_DW01_add_724' + Mapping 'VX_alu_1_DW01_add_725' + Mapping 'VX_alu_1_DW01_add_726' + Mapping 'VX_alu_1_DW01_add_727' + Mapping 'VX_alu_1_DW01_add_728' + Mapping 'VX_alu_1_DW01_add_729' + Mapping 'VX_alu_1_DW01_add_730' + Mapping 'VX_alu_1_DW01_add_731' + Mapping 'VX_alu_1_DW01_add_732' + Mapping 'VX_alu_1_DW01_add_733' + Mapping 'VX_alu_1_DW01_add_734' + Mapping 'VX_alu_1_DW01_add_735' + Mapping 'VX_alu_1_DW01_add_736' + Mapping 'VX_alu_1_DW01_add_737' + Mapping 'VX_alu_1_DW01_add_738' + Mapping 'VX_alu_1_DW01_add_739' + Mapping 'VX_alu_1_DW01_add_740' + Mapping 'VX_alu_1_DW01_add_741' + Mapping 'VX_alu_1_DW01_add_742' + Mapping 'VX_alu_1_DW01_add_743' + Mapping 'VX_alu_1_DW01_add_744' + Mapping 'VX_alu_1_DW01_add_745' + Mapping 'VX_alu_1_DW01_add_746' + Mapping 'VX_alu_1_DW01_add_747' + Mapping 'VX_alu_1_DW_inc_14' + Mapping 'VX_alu_1_DW_div_tc_7' + Structuring 'VX_alu_2_DW_div_tc_4' + Mapping 'VX_alu_2_DW_div_tc_4' + Structuring 'VX_alu_2_DW01_absval_4' + Mapping 'VX_alu_2_DW01_absval_4' + Structuring 'VX_alu_2_DW01_inc_4' + Mapping 'VX_alu_2_DW01_inc_4' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_561' + Mapping 'VX_alu_2_DW01_add_562' + Mapping 'VX_alu_2_DW01_add_563' + Mapping 'VX_alu_2_DW01_add_564' + Mapping 'VX_alu_2_DW01_add_565' + Mapping 'VX_alu_2_DW01_add_566' + Mapping 'VX_alu_2_DW01_add_567' + Mapping 'VX_alu_2_DW01_add_568' + Mapping 'VX_alu_2_DW01_add_569' + Mapping 'VX_alu_2_DW01_add_570' + Mapping 'VX_alu_2_DW01_add_571' + Mapping 'VX_alu_2_DW01_add_572' + Mapping 'VX_alu_2_DW01_add_573' + Mapping 'VX_alu_2_DW01_add_574' + Mapping 'VX_alu_2_DW01_add_575' + Mapping 'VX_alu_2_DW01_add_576' + Mapping 'VX_alu_2_DW01_add_577' + Mapping 'VX_alu_2_DW01_add_578' + Mapping 'VX_alu_2_DW01_add_579' + Mapping 'VX_alu_2_DW01_add_580' + Mapping 'VX_alu_2_DW01_add_581' + Mapping 'VX_alu_2_DW01_add_582' + Mapping 'VX_alu_2_DW01_add_583' + Mapping 'VX_alu_2_DW01_add_584' + Mapping 'VX_alu_2_DW01_add_585' + Mapping 'VX_alu_2_DW01_add_586' + Mapping 'VX_alu_2_DW01_add_587' + Mapping 'VX_alu_2_DW_inc_8' + Structuring 'VX_alu_2_DW_div_tc_5' + Mapping 'VX_alu_2_DW_div_tc_5' + Structuring 'VX_alu_2_DW01_absval_5' + Mapping 'VX_alu_2_DW01_absval_5' + Structuring 'VX_alu_2_DW01_inc_5' + Mapping 'VX_alu_2_DW01_inc_5' + Mapping 'VX_alu_2_DW01_add_588' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_589' + Mapping 'VX_alu_2_DW01_add_590' + Mapping 'VX_alu_2_DW01_add_591' + Mapping 'VX_alu_2_DW01_add_592' + Mapping 'VX_alu_2_DW01_add_593' + Mapping 'VX_alu_2_DW01_add_594' + Mapping 'VX_alu_2_DW01_add_595' + Mapping 'VX_alu_2_DW01_add_596' + Mapping 'VX_alu_2_DW01_add_597' + Mapping 'VX_alu_2_DW01_add_598' + Mapping 'VX_alu_2_DW01_add_599' + Mapping 'VX_alu_2_DW01_add_600' + Mapping 'VX_alu_2_DW01_add_601' + Mapping 'VX_alu_2_DW01_add_602' + Mapping 'VX_alu_2_DW01_add_603' + Mapping 'VX_alu_2_DW01_add_604' + Mapping 'VX_alu_2_DW01_add_605' + Mapping 'VX_alu_2_DW01_add_606' + Mapping 'VX_alu_2_DW01_add_607' + Mapping 'VX_alu_2_DW01_add_608' + Mapping 'VX_alu_2_DW01_add_609' + Mapping 'VX_alu_2_DW01_add_610' + Mapping 'VX_alu_2_DW01_add_611' + Mapping 'VX_alu_2_DW01_add_612' + Mapping 'VX_alu_2_DW01_add_613' + Mapping 'VX_alu_2_DW01_add_614' + Mapping 'VX_alu_2_DW01_add_615' + Mapping 'VX_alu_2_DW01_add_616' + Mapping 'VX_alu_2_DW01_add_617' + Mapping 'VX_alu_2_DW01_add_618' + Mapping 'VX_alu_2_DW01_add_619' + Mapping 'VX_alu_2_DW01_add_620' + Mapping 'VX_alu_2_DW01_add_621' + Mapping 'VX_alu_2_DW01_add_622' + Mapping 'VX_alu_2_DW01_add_623' + Mapping 'VX_alu_2_DW01_add_624' + Mapping 'VX_alu_2_DW01_add_625' + Mapping 'VX_alu_2_DW01_add_626' + Mapping 'VX_alu_2_DW01_add_627' + Mapping 'VX_alu_2_DW_inc_10' + Structuring 'VX_alu_2_DW_div_tc_6' + Mapping 'VX_alu_2_DW_div_tc_6' + Structuring 'VX_alu_2_DW01_absval_6' + Mapping 'VX_alu_2_DW01_absval_6' + Structuring 'VX_alu_2_DW01_inc_6' + Mapping 'VX_alu_2_DW01_inc_6' + Mapping 'VX_alu_2_DW01_add_628' + Mapping 'VX_alu_2_DW01_add_629' + Mapping 'VX_alu_2_DW01_add_630' + Mapping 'VX_alu_2_DW01_sub_4' + Mapping 'VX_alu_2_DW01_add_631' + Mapping 'VX_alu_2_DW01_add_632' + Mapping 'VX_alu_2_DW01_add_633' + Mapping 'VX_alu_2_DW01_add_638' + Mapping 'VX_alu_2_DW01_add_639' + Mapping 'VX_alu_2_DW01_add_640' + Mapping 'VX_alu_2_DW01_add_641' + Mapping 'VX_alu_2_DW01_add_642' + Mapping 'VX_alu_2_DW01_add_643' + Mapping 'VX_alu_2_DW01_add_644' + Mapping 'VX_alu_2_DW01_add_645' + Mapping 'VX_alu_2_DW01_add_646' + Mapping 'VX_alu_2_DW01_add_647' + Mapping 'VX_alu_2_DW01_add_648' + Mapping 'VX_alu_2_DW01_add_649' + Mapping 'VX_alu_2_DW01_add_650' + Mapping 'VX_alu_2_DW01_add_651' + Mapping 'VX_alu_2_DW01_add_652' + Mapping 'VX_alu_2_DW01_add_653' + Mapping 'VX_alu_2_DW01_add_654' + Mapping 'VX_alu_2_DW01_add_655' + Mapping 'VX_alu_2_DW01_add_656' + Mapping 'VX_alu_2_DW01_add_657' + Mapping 'VX_alu_2_DW01_add_658' + Mapping 'VX_alu_2_DW01_add_659' + Mapping 'VX_alu_2_DW01_add_660' + Mapping 'VX_alu_2_DW01_add_661' + Mapping 'VX_alu_2_DW01_add_662' + Mapping 'VX_alu_2_DW01_add_663' + Mapping 'VX_alu_2_DW01_add_664' + Mapping 'VX_alu_2_DW01_add_665' + Mapping 'VX_alu_2_DW01_add_666' + Mapping 'VX_alu_2_DW01_add_667' + Mapping 'VX_alu_2_DW01_add_668' + Mapping 'VX_alu_2_DW01_add_669' + Mapping 'VX_alu_2_DW01_add_670' + Mapping 'VX_alu_2_DW01_add_671' + Mapping 'VX_alu_2_DW01_add_672' + Mapping 'VX_alu_2_DW01_add_673' + Mapping 'VX_alu_2_DW01_add_674' + Mapping 'VX_alu_2_DW01_add_675' + Mapping 'VX_alu_2_DW01_add_676' + Mapping 'VX_alu_2_DW01_add_677' + Mapping 'VX_alu_2_DW01_add_678' + Mapping 'VX_alu_2_DW01_add_679' + Mapping 'VX_alu_2_DW01_add_680' + Mapping 'VX_alu_2_DW01_add_681' + Mapping 'VX_alu_2_DW01_add_682' + Mapping 'VX_alu_2_DW01_add_683' + Mapping 'VX_alu_2_DW01_add_684' + Mapping 'VX_alu_2_DW01_add_685' + Mapping 'VX_alu_2_DW01_add_686' + Mapping 'VX_alu_2_DW01_add_687' + Mapping 'VX_alu_2_DW01_add_688' + Mapping 'VX_alu_2_DW01_add_689' + Mapping 'VX_alu_2_DW01_add_690' + Mapping 'VX_alu_2_DW01_add_691' + Mapping 'VX_alu_2_DW01_add_692' + Mapping 'VX_alu_2_DW01_add_693' + Mapping 'VX_alu_2_DW01_add_694' + Mapping 'VX_alu_2_DW01_add_695' + Mapping 'VX_alu_2_DW01_add_696' + Mapping 'VX_alu_2_DW01_add_697' + Mapping 'VX_alu_2_DW01_add_698' + Mapping 'VX_alu_2_DW01_add_699' + Mapping 'VX_alu_2_DW01_add_700' + Mapping 'VX_alu_2_DW01_add_701' + Mapping 'VX_alu_2_DW01_add_702' + Mapping 'VX_alu_2_DW01_add_703' + Mapping 'VX_alu_2_DW01_add_704' + Mapping 'VX_alu_2_DW01_add_705' + Mapping 'VX_alu_2_DW01_add_706' + Mapping 'VX_alu_2_DW01_add_707' + Mapping 'VX_alu_2_DW_inc_12' + Structuring 'VX_alu_2_DW_div_tc_7' + Mapping 'VX_alu_2_DW_div_tc_7' + Structuring 'VX_alu_2_DW01_absval_7' + Mapping 'VX_alu_2_DW01_absval_7' + Structuring 'VX_alu_2_DW01_inc_7' + Mapping 'VX_alu_2_DW01_inc_7' + Mapping 'VX_alu_2_DW01_add_708' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'DW01_add' + Mapping 'VX_alu_2_DW01_add_709' + Mapping 'VX_alu_2_DW01_add_710' + Mapping 'VX_alu_2_DW01_add_711' + Mapping 'VX_alu_2_DW01_add_712' + Mapping 'VX_alu_2_DW01_add_713' + Mapping 'VX_alu_2_DW01_add_714' + Mapping 'VX_alu_2_DW01_add_715' + Mapping 'VX_alu_2_DW01_add_716' + Mapping 'VX_alu_2_DW01_add_717' + Mapping 'VX_alu_2_DW01_add_718' + Mapping 'VX_alu_2_DW01_add_719' + Mapping 'VX_alu_2_DW01_add_720' + Mapping 'VX_alu_2_DW01_add_721' + Mapping 'VX_alu_2_DW01_add_722' + Mapping 'VX_alu_2_DW01_add_723' + Mapping 'VX_alu_2_DW01_add_724' + Mapping 'VX_alu_2_DW01_add_725' + Mapping 'VX_alu_2_DW01_add_726' + Mapping 'VX_alu_2_DW01_add_727' + Mapping 'VX_alu_2_DW01_add_728' + Mapping 'VX_alu_2_DW01_add_729' + Mapping 'VX_alu_2_DW01_add_730' + Mapping 'VX_alu_2_DW01_add_731' + Mapping 'VX_alu_2_DW01_add_732' + Mapping 'VX_alu_2_DW01_add_733' + Mapping 'VX_alu_2_DW01_add_734' + Mapping 'VX_alu_2_DW01_add_735' + Mapping 'VX_alu_2_DW01_add_736' + Mapping 'VX_alu_2_DW01_add_737' + Mapping 'VX_alu_2_DW01_add_738' + Mapping 'VX_alu_2_DW01_add_739' + Mapping 'VX_alu_2_DW01_add_740' + Mapping 'VX_alu_2_DW01_add_741' + Mapping 'VX_alu_2_DW01_add_742' + Mapping 'VX_alu_2_DW01_add_743' + Mapping 'VX_alu_2_DW01_add_744' + Mapping 'VX_alu_2_DW01_add_745' + Mapping 'VX_alu_2_DW01_add_746' + Mapping 'VX_alu_2_DW01_add_747' + Mapping 'VX_alu_2_DW_inc_14' + Mapping 'VX_alu_2_DW_div_tc_7' + Mapping Optimization (Phase 1) + Mapping Optimization (Phase 2) + Mapping Optimization (Phase 3) + Mapping Optimization (Phase 4) + Mapping Optimization (Phase 5) + Mapping Optimization (Phase 6) + Mapping Optimization (Phase 7) + Mapping Optimization (Phase 8) + Mapping Optimization (Phase 9) + Mapping Optimization (Phase 10) + Mapping Optimization (Phase 11) + Mapping Optimization (Phase 12) + Mapping Optimization (Phase 13) + Mapping Optimization (Phase 14) + Mapping Optimization (Phase 15) + Mapping Optimization (Phase 16) + Mapping Optimization (Phase 17) + Mapping Optimization (Phase 18) + Mapping Optimization (Phase 19) + Mapping Optimization (Phase 20) + Mapping Optimization (Phase 21) + Mapping Optimization (Phase 22) + Mapping Optimization (Phase 23) + Mapping Optimization (Phase 24) + Mapping Optimization (Phase 25) + Mapping Optimization (Phase 26) + Mapping Optimization (Phase 27) + Mapping Optimization (Phase 28) + Mapping Optimization (Phase 29) + Mapping Optimization (Phase 30) + Mapping Optimization (Phase 31) + Mapping Optimization (Phase 32) + Mapping Optimization (Phase 33) + Mapping Optimization (Phase 34) + Mapping Optimization (Phase 35) + Mapping Optimization (Phase 36) + Mapping Optimization (Phase 37) + Mapping Optimization (Phase 38) + Mapping Optimization (Phase 39) + Mapping Optimization (Phase 40) + Mapping Optimization (Phase 41) + Mapping Optimization (Phase 42) + Mapping Optimization (Phase 43) + Mapping Optimization (Phase 44) + Mapping Optimization (Phase 45) + Mapping Optimization (Phase 46) + Mapping Optimization (Phase 47) + Mapping Optimization (Phase 48) + Mapping Optimization (Phase 49) + Mapping Optimization (Phase 50) + Mapping Optimization (Phase 51) + Mapping Optimization (Phase 52) + Mapping Optimization (Phase 53) + Mapping Optimization (Phase 54) + Mapping Optimization (Phase 55) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[0]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[1]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[2]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[3]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[4]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[5]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[6]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[7]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[8]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[9]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[10]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[11]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[12]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[13]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[14]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[15]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[16]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[17]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[18]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[19]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[20]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[21]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[22]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[23]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[24]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[25]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[26]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[27]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[28]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[29]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[30]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[31]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[32]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[33]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[34]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[35]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[36]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[37]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[38]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[39]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[40]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[41]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[42]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[43]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[44]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[45]' is a constant and will be removed. (OPT-1206) +Information: The register 'vx_back_end/VX_gpr_stage/exec_unit_reg/value_reg[46]' is a constant and will be removed. (OPT-1206) + + Beginning Constant Register Removal + ----------------------------------- + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 0:31:32 980726.1 7.76 33256.2 0.9 158.9538 + 0:31:32 980726.1 7.76 33256.2 0.9 158.9538 + 0:31:35 981516.7 7.76 33027.8 0.9 159.2815 + 0:31:38 981976.3 7.61 32795.8 0.9 159.4690 + + Beginning Global Optimizations + ------------------------------ + Numerical Synthesis (Phase 1) + Numerical Synthesis (Phase 2) + Global Optimization (Phase 1) + Global Optimization (Phase 2) + Global Optimization (Phase 3) + Global Optimization (Phase 4) + Global Optimization (Phase 5) + Global Optimization (Phase 6) + Global Optimization (Phase 7) + Global Optimization (Phase 8) + Global Optimization (Phase 9) + Global Optimization (Phase 10) + Global Optimization (Phase 11) + Global Optimization (Phase 12) + Global Optimization (Phase 13) + Global Optimization (Phase 14) + Global Optimization (Phase 15) + Global Optimization (Phase 16) + Global Optimization (Phase 17) + Global Optimization (Phase 18) + Global Optimization (Phase 19) + Global Optimization (Phase 20) + Global Optimization (Phase 21) + Global Optimization (Phase 22) + Global Optimization (Phase 23) + Global Optimization (Phase 24) + Global Optimization (Phase 25) + Global Optimization (Phase 26) + Global Optimization (Phase 27) + Global Optimization (Phase 28) + Global Optimization (Phase 29) + Global Optimization (Phase 30) + Global Optimization (Phase 31) + Global Optimization (Phase 32) + Global Optimization (Phase 33) + Mapping 'VX_alu_1_DW01_add_1126' + Mapping 'VX_alu_1_DW01_add_1127' + Mapping 'VX_alu_1_DW01_add_1128' + Mapping 'VX_alu_1_DW01_add_1129' + Mapping 'VX_alu_3_DW01_add_1154' + Mapping 'VX_alu_3_DW01_add_1155' + Mapping 'VX_alu_1_DW01_add_1130' + Mapping 'VX_alu_3_DW01_add_1156' + Mapping 'VX_alu_1_DW01_add_1131' + Mapping 'VX_alu_0_DW01_add_1176' + Mapping 'VX_alu_0_DW01_add_1177' + Mapping 'VX_alu_1_DW01_add_1132' + Mapping 'VX_alu_3_DW01_add_1157' + Mapping 'VX_alu_0_DW01_add_1178' + Mapping 'VX_alu_3_DW01_add_1158' + Mapping 'VX_alu_1_DW01_add_1133' + Mapping 'VX_alu_0_DW01_add_1179' + Mapping 'VX_alu_2_DW01_add_1137' + Mapping 'VX_alu_1_DW01_add_1134' + Mapping 'VX_alu_0_DW01_add_1180' + Mapping 'VX_alu_3_DW01_add_1159' + Mapping 'VX_alu_1_DW01_add_1135' + Mapping 'VX_alu_2_DW01_add_1138' + Mapping 'VX_alu_0_DW01_add_1181' + Mapping 'VX_alu_3_DW01_add_1160' + Mapping 'VX_alu_0_DW01_add_1182' + Mapping 'VX_alu_1_DW01_add_1136' + Mapping 'VX_alu_3_DW01_add_1161' + Mapping 'VX_alu_2_DW01_add_1139' + Mapping 'VX_alu_3_DW01_add_1162' + Mapping 'VX_alu_1_DW01_add_1137' + Mapping 'VX_alu_0_DW01_add_1183' + Mapping 'VX_alu_3_DW01_add_1163' + Mapping 'VX_alu_0_DW01_add_1184' + Mapping 'VX_alu_1_DW01_add_1138' + Mapping 'VX_alu_2_DW01_add_1140' + Mapping 'VX_alu_0_DW01_add_1185' + Mapping 'VX_alu_1_DW01_add_1139' + Mapping 'VX_alu_1_DW01_add_1140' + Mapping 'VX_alu_0_DW01_add_1186' + Mapping 'VX_alu_3_DW01_add_1164' + Mapping 'VX_alu_1_DW01_add_1141' + Mapping 'VX_alu_1_DW01_add_1142' + Mapping 'VX_alu_1_DW01_add_1143' + Mapping 'VX_alu_1_DW01_add_1144' + Mapping 'VX_alu_1_DW01_add_1145' + Mapping 'VX_alu_1_DW01_add_1146' + Mapping 'VX_alu_1_DW01_add_1147' + Mapping 'VX_alu_1_DW01_add_1148' + Mapping 'VX_alu_1_DW01_add_1149' + Mapping 'VX_alu_1_DW01_add_1150' + Mapping 'VX_alu_1_DW01_add_1151' + Mapping 'VX_alu_1_DW01_add_1152' + Mapping 'VX_alu_1_DW01_add_1153' + Mapping 'VX_alu_3_DW01_add_1165' + Mapping 'VX_alu_0_DW01_add_1187' + Mapping 'VX_alu_1_DW01_add_1154' + Mapping 'VX_alu_1_DW01_add_1155' + Mapping 'VX_alu_1_DW01_add_1156' + Mapping 'VX_alu_1_DW01_add_1157' + Mapping 'VX_alu_1_DW01_add_1158' + Mapping 'VX_alu_1_DW01_add_1159' +Information: Added key list 'DesignWare' to design 'VX_execute_unit_I_VX_exec_unit_req_VX_exec_unit_req_inter__I_VX_inst_exec_wb_VX_inst_exec_wb_inter__I_VX_jal_rsp_VX_jal_response_inter__I_VX_branch_rsp_VX_branch_response_inter__'. (DDB-72) +Information: Added key list 'DesignWare' to design 'VX_lsu_addr_gen'. (DDB-72) + + Beginning Isolate Ports + ----------------------- + + Beginning Delay Optimization + ---------------------------- + 0:35:06 749079.4 9.28 32414.6 3.2 91.2115 + 0:39:57 753625.8 6.76 26799.6 2.2 92.6779 + 0:39:57 753625.8 6.76 26799.6 2.2 92.6779 + 0:40:00 753619.4 6.76 26809.4 2.2 92.6776 + + Beginning WLM Backend Optimization + -------------------------------------- + 0:46:39 736402.2 7.13 27452.3 2.1 88.9808 + 0:46:47 735773.0 7.13 27453.5 2.1 88.7728 + 0:46:54 735219.6 7.13 27450.5 2.0 88.5669 + 0:46:59 734761.5 7.13 27449.1 1.9 88.3929 + 0:47:02 734229.7 7.13 27445.8 1.9 88.1884 + 0:47:09 733706.2 7.09 27367.7 1.9 88.0102 + 0:47:12 733474.4 7.08 27270.7 1.8 87.9439 + 0:47:14 733223.3 7.04 27222.9 1.8 87.8667 + 0:47:18 732607.6 7.04 27216.7 1.8 87.6432 + 0:47:29 731962.5 7.02 27186.6 1.7 87.4201 + 0:47:50 731116.2 7.00 27201.5 1.2 87.1496 + 0:48:01 730398.2 7.00 27238.3 1.2 86.9453 + 0:48:08 729668.7 7.00 27269.6 1.1 86.7381 + 0:48:13 729130.1 7.00 27417.4 1.1 86.5899 + 0:48:19 728566.3 7.00 27414.2 1.0 86.4286 + 0:48:24 728014.0 7.00 27417.1 1.0 86.2623 + 0:48:38 727554.6 6.85 27078.0 0.9 86.1133 + 0:48:52 727401.0 6.82 27020.6 0.9 86.0696 + 0:49:00 727279.0 6.82 26988.9 0.9 86.0322 + 0:49:10 727117.9 6.82 26931.4 0.9 85.9886 + 0:49:20 727046.3 6.81 26922.1 0.9 85.9637 + 0:50:23 725539.7 6.78 26800.3 0.4 85.3831 + 0:50:24 725539.7 6.78 26800.3 0.4 85.3831 + 1:17:26 729551.6 5.90 24832.9 1.3 86.7683 + 1:17:26 729551.6 5.90 24832.9 1.3 86.7683 + 1:17:55 730072.3 5.86 24785.9 1.3 86.9256 + 1:17:55 730072.3 5.86 24785.9 1.3 86.9256 + 1:22:12 730494.1 5.83 24715.2 1.5 87.0533 + 1:22:12 730494.1 5.83 24715.2 1.5 87.0533 + 1:25:51 735170.6 5.64 24297.2 1.4 88.2832 + 1:25:51 735170.6 5.64 24297.2 1.4 88.2832 + 1:29:57 735283.0 5.62 24245.4 1.4 88.3205 + 1:29:57 735283.0 5.62 24245.4 1.4 88.3205 + 1:31:43 736747.6 5.57 24152.9 1.4 88.6744 + 1:31:43 736747.6 5.57 24152.9 1.4 88.6744 + 1:34:54 736739.4 5.56 24128.5 1.4 88.6785 + 1:34:54 736739.4 5.56 24128.5 1.4 88.6785 + 1:36:33 737742.8 5.54 24097.0 1.4 88.9232 + 1:36:33 737742.8 5.54 24097.0 1.4 88.9232 + 1:38:07 737669.1 5.53 24073.9 1.4 88.9001 + + + Beginning Design Rule Fixing (max_transition) (max_capacitance) + ---------------------------- + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 1:38:07 737669.1 5.53 24073.9 1.4 88.9001 + Global Optimization (Phase 34) + Global Optimization (Phase 35) + Global Optimization (Phase 36) + 1:38:16 737693.4 5.53 24060.0 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[4][29]/D 88.9074 + 1:38:18 737686.4 5.52 24057.3 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[4][29]/D 88.9055 + 1:38:19 737687.4 5.52 24057.2 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[4][29]/D 88.9057 + 1:38:21 737685.0 5.52 24056.5 0.0 88.9050 + 1:40:41 737649.6 5.53 24061.9 0.0 88.8942 + + + Beginning Leakage Power Optimization (max_leakage_power 0) + ------------------------------------ + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 1:40:41 737649.6 5.53 24061.9 0.0 88.8942 + Global Optimization (Phase 37) + Global Optimization (Phase 38) + Global Optimization (Phase 39) + Global Optimization (Phase 40) + Global Optimization (Phase 41) + Global Optimization (Phase 42) + Global Optimization (Phase 43) + Global Optimization (Phase 44) + Global Optimization (Phase 45) + Global Optimization (Phase 46) + Global Optimization (Phase 47) + Global Optimization (Phase 48) + Global Optimization (Phase 49) + Global Optimization (Phase 50) + Global Optimization (Phase 51) + Global Optimization (Phase 52) + Global Optimization (Phase 53) + Global Optimization (Phase 54) + Global Optimization (Phase 55) + 1:42:06 712340.2 6.17 25109.5 0.0 80.9256 +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_1'. + The new name of the port is 'reset_BAR'. (OPT-319) +Information: Complementing port 'reset' in design 'VX_generic_stack_WIDTH37_DEPTH2_4'. + The new name of the port is 'reset_BAR'. (OPT-319) + 1:42:36 712508.7 5.63 24193.8 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[3][23]/D 80.9955 + 1:42:40 712520.4 5.61 24170.6 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[3][23]/D 81.0003 + 1:42:44 712511.6 5.60 24129.1 0.0 vx_front_end/vx_fetch/warp_scheduler/warp_pcs_reg[3][23]/D 80.9979 + 1:42:45 712510.0 5.59 24126.4 0.0 80.9974 + 1:48:21 712976.7 5.51 23914.7 0.0 81.1437 + 1:48:21 712976.7 5.51 23914.7 0.0 81.1437 + 1:48:59 712654.5 5.52 23894.2 0.0 81.0801 + 1:49:00 712654.5 5.52 23894.2 0.0 81.0801 + 1:52:40 712939.9 5.49 23848.7 0.0 81.1703 + 1:52:40 712939.9 5.49 23848.7 0.0 81.1703 + 1:52:49 713089.3 5.48 23834.1 0.0 81.2154 + 1:52:49 713089.3 5.48 23834.1 0.0 81.2154 + 1:56:45 713639.1 5.46 23800.4 0.0 81.3801 + 1:56:45 713639.1 5.46 23800.4 0.0 81.3801 + 1:59:06 715670.6 5.40 23682.2 0.0 81.9285 + 1:59:06 715670.6 5.40 23682.2 0.0 81.9285 + 2:01:14 715673.2 5.40 23675.8 0.0 81.9251 + 2:01:14 715673.2 5.40 23675.8 0.0 81.9251 + 2:02:34 716724.1 5.38 23621.9 0.0 82.2173 + 2:02:34 716724.1 5.38 23621.9 0.0 82.2173 + 2:04:41 716744.5 5.37 23613.7 0.0 82.2244 + 2:04:41 716744.5 5.37 23613.7 0.0 82.2244 + 2:05:46 717565.7 5.36 23589.5 0.0 82.4469 + 2:05:46 717565.7 5.36 23589.5 0.0 82.4469 + 2:06:36 717591.6 5.36 23582.9 0.0 82.4549 + + TOTAL + ELAPSED WORST NEG SETUP DESIGN LEAKAGE + TIME AREA SLACK COST RULE COST ENDPOINT POWER + --------- --------- --------- --------- --------- ------------------------- --------- + 2:06:40 717505.4 5.36 23582.9 0.0 82.4528 + 2:10:30 664571.4 5.56 30224.0 0.0 61.8626 + 2:11:09 664635.6 5.54 30207.3 0.0 61.8902 + 2:11:10 664602.1 5.54 30207.3 0.0 61.8803 + 2:11:11 664598.2 5.54 30207.3 0.0 61.8785 + 2:11:12 664596.6 5.54 30207.3 0.0 61.8781 + 2:11:13 664588.9 5.54 30207.3 0.0 61.8757 + 2:11:14 664588.9 5.54 30207.3 0.0 61.8757 + 2:13:02 664551.7 5.54 29035.4 0.0 62.1583 + 2:13:04 664525.6 5.54 29035.4 0.0 62.1512 + 2:13:05 664519.1 5.54 29035.4 0.0 62.1491 + 2:13:07 664481.0 5.54 29022.9 0.0 62.1389 + 2:13:14 664373.8 5.54 29023.7 0.0 62.1087 + 2:13:23 664244.0 5.54 29023.7 0.0 62.0791 + 2:13:29 664118.5 5.54 29031.9 0.0 62.0514 + 2:13:35 664025.2 5.54 29031.7 0.0 62.0298 + 2:13:40 663967.2 5.54 29040.2 0.0 62.0126 + 2:13:46 663928.5 5.54 29040.1 0.0 62.0020 + 2:13:53 663900.8 5.54 29039.6 0.0 61.9937 + 2:13:56 663871.1 5.54 29039.5 0.0 61.9840 + 2:14:00 663847.3 5.54 29039.2 0.0 61.9763 + 2:16:55 667798.6 5.44 28821.2 0.0 63.1831 + 2:16:55 667798.6 5.44 28821.2 0.0 63.1831 + 2:18:37 669252.9 5.42 28758.3 0.0 63.6121 + 2:18:37 669252.9 5.42 28758.3 0.0 63.6121 + 2:20:05 670267.7 5.40 28721.2 0.0 63.8963 + 2:20:05 670267.7 5.40 28721.2 0.0 63.8963 + 2:21:38 671007.2 5.39 28690.6 0.0 64.1135 + 2:21:42 670947.8 5.39 28690.5 0.0 64.0990 + 2:21:47 670790.0 5.39 28688.4 0.0 64.0613 + 2:21:53 670770.4 5.39 28683.5 0.0 64.0557 + 2:22:06 670740.4 5.39 28681.8 0.0 64.0493 + 2:22:18 670704.9 5.39 28678.2 0.0 64.0424 + 2:22:22 670731.8 5.39 28679.3 0.0 64.0507 + 2:26:11 668457.2 5.37 28631.4 0.0 63.3755 + 2:28:10 666193.2 5.37 28619.2 0.0 62.8007 + 2:29:58 663659.4 5.36 28573.5 0.0 62.1129 +Loading db file '/nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db' +Loading db file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db' + + +Note: Symbol # after min delay cost means estimated hold TNS across all active scenarios + + + Optimization Complete + --------------------- +Warning: Design 'Vortex' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) + Net 'VX_dmem_controller/dcache/genblk3[1].bank_structure/data_structures/clk': 2592 load(s), 1 driver(s) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Warning: The trip points for the library named USERLIB_ss_0p81v_0p81v_m40c differ from those in the library named sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c. (TIM-164) +Information: State dependent leakage is now switched from off to on. +Information: Propagating switching activity (low effort zero delay simulation). (PWR-6) +Warning: Design has unannotated black box outputs. (PWR-428) +1 +ungroup -all -flatten +Information: Updating graph... (UID-83) +Warning: Design 'Vortex' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) +Warning: Design 'Vortex' inherited license information from design 'VX_warp_scheduler'. (DDB-74) +Information: Added key list 'DesignWare' to design 'Vortex'. (DDB-72) +1 +uniquify +1 +define_name_rules verilog -remove_internal_net_bus -remove_port_bus +1 +change_names -rule verilog -hierarchy +1 +report_qor +Information: Updating design information... (UID-85) +Warning: Design 'Vortex' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) + +**************************************** +Report : qor +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:36:42 2019 +**************************************** + + + Timing Path Group 'clk' + ----------------------------------- + Levels of Logic: 172.00 + Critical Path Length: 6.33 + Critical Path Slack: -5.36 + Critical Path Clk Period: 1.00 + Total Negative Slack: -28570.89 + No. of Violating Paths: 10132.00 + Worst Hold Violation: -0.08 + Total Hold Violation: -120.79 + No. of Hold Violations: 2110.00 + ----------------------------------- + + + Cell Count + ----------------------------------- + Hierarchical Cell Count: 0 + Hierarchical Port Count: 0 + Leaf Cell Count: 178940 + Buf/Inv Cell Count: 31971 + Buf Cell Count: 2044 + Inv Cell Count: 29927 + CT Buf/Inv Cell Count: 0 + Combinational Cell Count: 176259 + Sequential Cell Count: 2681 + Macro Count: 0 + ----------------------------------- + + + Area + ----------------------------------- + Combinational Area: 189441.503158 + Noncombinational Area: 8355.311887 + Buf/Inv Area: 19144.998044 + Total Buffer Area: 2496.10 + Total Inverter Area: 16648.90 + Macro/Black Box Area: 465862.566406 + Net Area: 0.000000 + ----------------------------------- + Cell Area: 663659.381451 + Design Area: 663659.381451 + + + Design Rules + ----------------------------------- + Total Number of Nets: 188500 + Nets With Violations: 0 + Max Trans Violations: 0 + Max Cap Violations: 0 + ----------------------------------- + + + Hostname: gtcad-srv1 + + Compile CPU Statistics + ----------------------------------------- + Resource Sharing: 20.75 + Logic Optimization: 1727.66 + Mapping Optimization: 5763.15 + ----------------------------------------- + Overall Compile Time: 8942.13 + Overall Compile Wall Clock Time: 9021.51 + + -------------------------------------------------------------------- + + Design WNS: 5.36 TNS: 28570.89 Number of Violating Paths: 10132 + + + Design (Hold) WNS: 0.08 TNS: 120.79 Number of Violating Paths: 2110 + + -------------------------------------------------------------------- + + +1 +report_area + +**************************************** +Report : area +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:36:45 2019 +**************************************** + +Library(s) Used: + + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db) + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (File: /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db) + +Number of ports: 2215 +Number of nets: 188500 +Number of cells: 178987 +Number of combinational cells: 176259 +Number of sequential cells: 2641 +Number of macros/black boxes: 40 +Number of buf/inv: 31971 +Number of references: 487 + +Combinational area: 189441.503158 +Buf/Inv area: 19144.998044 +Noncombinational area: 8355.311887 +Macro/Black Box area: 465862.566406 +Net Interconnect area: 0.000000 + +Total cell area: 663659.381451 +Total area: 663659.381451 +1 +report_hierarchy + +**************************************** +Report : hierarchy +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:36:45 2019 +**************************************** + +Attributes: + r - licensed design + +Vortex r + ADDF_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + ADDF_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + ADDF_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + ADDH_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + ADDH_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + ADDH_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X8B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND2_X11M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND3_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AND4_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO1B2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21A1AI2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AO22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI2XB1_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21B_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI21_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22BB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI22_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI31_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + AOI211_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X1P2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X2P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X7P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X11M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUFH_X13M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X3P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X7P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + BUF_X13M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGENCON_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGENI_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGENI_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGENI_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + CGEN_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFQL_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQL_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQNL_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQN_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFRPQ_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFSQN_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + DFFSQN_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X0P8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X1P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X2P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X3P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X7P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X11M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + INV_X16M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + LATQ_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MX2_X8B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXIT2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + MXT2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2B_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2XB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X0P7B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X8B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3BB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3XXB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X0P5A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X6A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND3_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X0P5A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NAND4_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2B_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2XB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X0P5B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X0P7A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1P4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X6A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X8A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3BB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X2A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X3A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X4A_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR3_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + NOR4BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA1B2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21A1OI2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21B_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA21_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OA211_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI2XB1_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21B_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI21_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22BB_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI22_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI31_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OAI211_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X0P7B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X1P4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR2_X11M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + OR4_X8M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + TIEHI_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + TIELO_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XNOR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X0P7M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR2_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR3_X0P5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR3_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + XOR3_X1P4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c +1 +report_cell + +**************************************** +Report : cell +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:36:45 2019 +**************************************** + +Attributes: + b - black box (unknown) + d - dont_touch + h - hierarchical + n - noncombinational + r - removable + u - contains unmapped logic + +Cell Reference Library Area Attributes +-------------------------------------------------------------------------------- +U1 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +U2 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U3 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +U4 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U5 OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +U6 AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +U7 OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +U8 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U9 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U10 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +U11 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U12 OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +U13 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U14 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U15 NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +U16 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U14 NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U15 BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U16 NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_U17 BUF_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_U18 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U19 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U20 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U21 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U22 NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U23 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U24 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U25 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U26 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U27 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U28 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U29 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U30 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U31 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U32 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U33 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U34 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U35 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U36 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U37 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U38 NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U39 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U40 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U41 BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U42 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U43 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U44 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U45 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U46 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U47 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U48 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U49 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U50 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U51 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U52 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U53 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U54 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U55 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U56 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U57 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U58 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U59 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U60 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U61 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U62 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U63 NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_U64 NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_U65 NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_U66 NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U67 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U68 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U69 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U70 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U71 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U72 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U73 NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_U74 NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_U75 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U76 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U77 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U78 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U79 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U80 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U81 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U82 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U83 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U84 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U85 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U86 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U87 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U88 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U89 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U90 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U91 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U92 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U93 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U94 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U95 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U96 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U97 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U98 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U99 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U100 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U101 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U102 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U103 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U104 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U105 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U106 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U107 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U108 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U109 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U110 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U111 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U112 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U113 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U114 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U115 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U116 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U117 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U118 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U119 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U120 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U121 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U122 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U123 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U124 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U125 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U126 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U127 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U128 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U129 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U130 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U131 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U132 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U133 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U134 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U135 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U136 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U137 NAND3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_U138 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U139 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U140 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U141 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U142 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U143 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U144 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U145 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U146 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U147 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U148 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U149 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U150 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U151 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U152 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U153 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U154 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U155 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U156 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U157 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U158 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U159 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U160 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U161 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U162 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U163 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U164 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U165 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U166 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U167 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U168 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U169 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U170 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U171 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U172 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U173 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U174 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U175 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U176 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U177 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U178 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U179 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U180 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U181 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U182 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U183 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U184 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U185 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U186 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U187 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U188 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U189 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U190 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U191 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U192 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U193 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U194 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U195 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U196 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U197 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U198 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U199 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U200 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U201 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U202 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U203 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U204 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U205 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U206 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U207 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U208 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U209 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U210 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U211 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U212 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U213 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U214 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U215 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U216 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U217 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U218 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U219 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U220 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U221 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U222 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U223 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U224 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U225 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U226 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U227 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U228 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U229 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U230 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U231 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U232 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U233 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U234 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U235 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U236 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U237 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U238 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U239 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U240 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U241 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U242 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U243 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U244 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U245 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U246 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U247 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U248 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U249 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U250 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U251 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U252 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U253 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U254 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U255 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U256 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U257 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U258 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U259 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U260 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U261 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U262 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U263 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U264 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U265 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U266 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U267 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U268 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U269 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U270 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U271 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U272 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U273 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U274 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U275 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U276 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U277 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U278 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U279 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U280 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U281 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U282 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U283 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U284 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U285 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U286 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U287 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_U288 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U289 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U290 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U291 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U292 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U293 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_U294 NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_U295 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U296 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U297 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U298 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U299 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_U300 MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U3 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U4 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U5 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U6 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U7 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U8 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U9 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U10 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U11 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U12 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U13 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U14 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U15 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U16 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U17 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U18 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U19 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U20 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U21 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U22 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U23 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U24 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U25 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U26 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U27 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U28 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U29 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U30 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U31 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U32 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U33 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U34 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U35 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U36 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U37 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U38 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U39 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U40 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U41 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U42 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U43 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U44 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U45 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U46 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U47 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U48 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U49 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U50 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U51 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U52 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U53 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U54 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U55 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U56 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U57 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U58 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U59 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U60 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U61 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U62 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U63 + OAI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U64 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U65 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U66 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U67 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U68 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U69 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U70 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U71 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U72 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U73 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U74 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U75 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U76 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U77 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U78 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U79 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U80 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U81 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U82 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U83 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U84 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U85 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U86 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U87 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U88 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U89 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U90 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U91 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U92 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U93 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U94 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U95 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U96 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U97 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U98 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U99 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U100 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U101 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U102 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U103 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U104 + NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U105 + NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U106 + NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U107 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U108 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U109 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U110 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U111 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U112 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U113 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U114 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U115 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U116 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U117 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U118 + NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U119 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U120 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U121 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U122 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U123 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U124 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U125 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U126 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U127 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U128 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U129 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U130 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U131 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U132 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U133 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U134 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U135 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U136 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U137 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U138 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U139 + BUF_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U140 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U141 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U142 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U143 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U144 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U145 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U146 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U147 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U148 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U149 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U150 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U152 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U153 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U155 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U156 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U157 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U158 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U159 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U160 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U161 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U162 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U163 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U164 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U165 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U166 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U167 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U168 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U169 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U170 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U171 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U172 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U173 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U174 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U175 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U177 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U178 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U179 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U180 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U181 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U182 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U183 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U184 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U185 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U186 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U187 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U191 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U192 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U193 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U194 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U195 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U196 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U197 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U198 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U199 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U200 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U201 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U202 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U203 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U204 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U205 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U206 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U207 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U208 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U209 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U210 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U211 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U213 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U214 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U215 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U216 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U217 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U218 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U219 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U220 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U221 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U222 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U223 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U224 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U225 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U226 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U227 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U228 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U229 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U231 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U232 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U233 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U234 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U235 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U236 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U237 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U238 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U239 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U240 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U241 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U242 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U243 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U244 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U245 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U246 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U247 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U248 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U249 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U250 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U251 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U252 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U253 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U254 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U255 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U256 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U257 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U259 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U260 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U261 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U262 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U263 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U265 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U266 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U267 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U268 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U269 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U270 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U271 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U272 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U273 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U274 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U275 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U276 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U277 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U278 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U279 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U280 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U281 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U282 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U283 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U284 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U285 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U286 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U287 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U288 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U289 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U290 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U291 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U292 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U293 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U294 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U295 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U296 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U297 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U298 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U299 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U300 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U301 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U302 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U303 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U304 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U305 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U306 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U307 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U308 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U309 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U310 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U311 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U312 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U313 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U314 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U315 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U316 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U317 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U318 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U319 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U320 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U322 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U323 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U324 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U325 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U326 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U327 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U328 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U329 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U330 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U331 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U334 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U335 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U336 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U337 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U338 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U339 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U340 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U341 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U342 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U343 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U345 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U346 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U347 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U348 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U349 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U351 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U352 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U353 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U354 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U355 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U356 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U357 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U358 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U359 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U360 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U361 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U362 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U363 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U364 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U365 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U366 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U367 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U368 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U369 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U370 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U371 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U372 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U373 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U374 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U375 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U376 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U377 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U378 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U379 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U380 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U381 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U382 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U383 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U384 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U385 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U386 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U387 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U388 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U389 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U390 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U391 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U392 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U393 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U394 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U395 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U396 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U397 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U398 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U399 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U400 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U401 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U402 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U403 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U404 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U405 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U406 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U407 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U408 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U409 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U410 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U411 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U412 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U413 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U414 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U415 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U416 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U417 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U418 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U419 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U420 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U421 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U422 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U423 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U424 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U425 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U426 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U427 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U428 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U429 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U430 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U431 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U432 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U433 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U434 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U435 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U436 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U437 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U438 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U439 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U440 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U441 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U442 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U443 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U444 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U445 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U446 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U447 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U448 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U449 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U450 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U451 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U452 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U453 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U454 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U455 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U456 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U457 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U458 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U459 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U460 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U461 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U462 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U463 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U464 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U465 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U466 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U467 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U468 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U469 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U470 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U471 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U472 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U473 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U474 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U475 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U476 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U477 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U478 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U479 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U480 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U481 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U482 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U483 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U484 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U485 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U486 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U487 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U488 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U489 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U490 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U491 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U492 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U493 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U494 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U495 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U496 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U497 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U498 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U499 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U500 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U501 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U502 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U503 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U504 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U505 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U506 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U507 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U508 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U509 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U510 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U511 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U512 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U513 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U514 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U517 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U519 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U520 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U522 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U523 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U524 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U525 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U526 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U527 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U528 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U530 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U531 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U532 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U533 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U534 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U535 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U536 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U537 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U538 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U539 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U540 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U541 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U542 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U543 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U544 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U545 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U546 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U547 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U548 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U549 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U550 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U551 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U552 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U553 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U554 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U555 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U556 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U557 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U558 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U559 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U560 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U561 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U562 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U563 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U564 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U565 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U566 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U567 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U568 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U569 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U570 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U571 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U572 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U573 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U574 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U575 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U576 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U577 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U578 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U579 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U580 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U581 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U582 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U583 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U584 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U585 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U586 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U587 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U588 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U589 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U590 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U591 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U592 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U593 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U594 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U595 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U596 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U597 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U598 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U599 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U600 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U601 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U602 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U603 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U604 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U605 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U606 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U607 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U608 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U609 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U610 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U611 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U612 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U613 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U614 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U615 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U616 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U617 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U618 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U619 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U620 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U621 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U622 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U623 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U624 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U625 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U626 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U627 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U628 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U629 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U630 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U631 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U632 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U633 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U634 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U635 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U636 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U637 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U638 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U639 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U640 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U641 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U642 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U643 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U644 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U645 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U646 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U647 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U648 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U649 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U650 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U651 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U652 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U653 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U654 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U655 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U656 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U657 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U658 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U659 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U660 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U661 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U662 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U663 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U664 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U665 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U666 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U667 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U668 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U670 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U671 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U672 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U673 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U674 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U675 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U676 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U677 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U678 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U679 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U680 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U681 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U682 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U683 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U684 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U685 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U686 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U687 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U688 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U690 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U691 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U692 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U693 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U694 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U695 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U696 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U697 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U698 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U699 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U700 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U701 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U702 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U703 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U704 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U705 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U706 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U707 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U708 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U709 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U710 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U711 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U712 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U713 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U714 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U715 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U716 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U717 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U718 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U719 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U720 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U721 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U722 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U723 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U724 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U725 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U726 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U727 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U728 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U729 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U730 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U731 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U732 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U733 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U734 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U735 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U736 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U737 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U738 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U739 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U740 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U741 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U742 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U743 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U744 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U745 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U746 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U747 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U748 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U749 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U750 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U751 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U752 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U753 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U754 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U755 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U756 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U757 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U758 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U759 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U760 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U761 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U762 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U763 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U764 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U765 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U766 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U767 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U768 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U769 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U770 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U771 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U772 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U773 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U774 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U775 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U776 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U777 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U778 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U779 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U780 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U781 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U782 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U783 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U784 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U785 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U786 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U787 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U788 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U789 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U790 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U791 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U792 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U793 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U794 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U795 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U796 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U797 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U798 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U799 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U800 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U801 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U802 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U803 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U804 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U805 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U806 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U807 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U808 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U809 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U810 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U811 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U812 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U813 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U814 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U815 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U816 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U817 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U818 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U819 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U820 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U821 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U822 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U823 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U824 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U825 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U826 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U827 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U828 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U829 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U830 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U831 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U832 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U833 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U834 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U835 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U836 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U837 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U838 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U839 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U840 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U841 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U842 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U843 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U844 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U845 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U846 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U847 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U848 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U849 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U850 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U851 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U852 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U853 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U854 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U855 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U856 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U857 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U858 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U859 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U860 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U861 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U862 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U863 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U864 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U865 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U866 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U867 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U868 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U869 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U870 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U871 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U872 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U873 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U874 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U875 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U876 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U877 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U878 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U879 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U880 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U881 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U882 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U883 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U884 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U885 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U886 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U887 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U888 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U889 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U890 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U891 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U892 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U893 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U894 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U895 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U896 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U897 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U898 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U899 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U900 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U901 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U902 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U903 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U904 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U905 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U906 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U907 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U908 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U909 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U910 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U911 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U912 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U913 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U914 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U915 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U916 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U917 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U918 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U919 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U920 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U921 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U922 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U923 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U924 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U925 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U926 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U928 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U929 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U930 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U931 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U932 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U933 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U934 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U935 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U936 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U937 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U938 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U939 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U940 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U941 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U942 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U943 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U944 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U945 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U946 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U947 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U948 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U949 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U950 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U951 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U952 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U953 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U954 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U955 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U956 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U957 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U958 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U959 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U960 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U961 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U962 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U963 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U964 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U965 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U966 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U967 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U968 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U969 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U970 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U971 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U972 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U973 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U974 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U975 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U976 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U977 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U978 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U979 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U980 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U981 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U982 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U983 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U984 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U985 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U986 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U987 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U988 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U989 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U990 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U991 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U992 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U993 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U994 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U995 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U996 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U997 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U998 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U999 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1000 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1001 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1002 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1003 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1004 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1005 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1006 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1007 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1008 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1009 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1010 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1011 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1012 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1013 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1014 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1015 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1016 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1017 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1018 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1019 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1020 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1021 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1022 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1023 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1024 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1025 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1026 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1027 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1028 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1029 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U1030 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1031 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1032 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1033 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1034 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1035 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1036 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1037 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1038 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1039 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1040 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1041 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1042 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1043 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1044 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1045 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1046 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1047 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1048 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1049 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1050 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1051 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1052 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1053 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1054 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1055 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1056 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1057 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1058 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1059 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1060 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1061 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1062 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1063 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1064 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1065 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1066 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1067 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1068 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1069 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1070 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1071 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1072 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1073 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1074 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1075 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1076 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1077 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1078 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1079 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1080 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1081 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1082 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1083 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1084 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1085 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1086 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1087 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1088 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1089 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1090 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1091 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1092 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1093 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1094 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1095 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1096 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1097 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1098 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1099 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1100 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1101 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1102 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1103 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1104 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1105 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1106 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1107 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1108 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1111 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1112 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1113 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1116 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1117 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1119 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1121 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1123 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1124 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1126 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1127 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1130 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1131 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1133 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1135 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1137 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1138 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1148 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1149 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1151 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1152 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1153 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1154 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1156 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1158 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1159 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1161 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1165 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1180 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1181 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1194 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1201 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1204 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1205 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1208 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1209 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1210 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1211 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1212 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1213 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1214 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1215 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1216 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1217 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1218 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1219 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1220 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1221 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1222 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1223 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1224 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1225 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1229 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1231 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1232 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1233 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1236 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1237 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1241 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1245 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1247 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1249 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1250 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1252 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1253 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1255 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1256 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1260 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1267 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1274 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1283 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1284 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1285 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1287 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1291 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1292 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1293 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1297 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1300 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1301 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1304 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1305 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1307 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1310 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1311 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1312 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1313 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1315 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1316 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1317 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1318 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1319 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1320 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1323 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1326 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1327 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1329 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1330 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1333 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1334 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1335 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1336 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1337 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1338 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1339 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1340 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1341 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1342 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1343 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1344 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1345 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1346 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1347 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1350 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1351 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1353 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1354 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1356 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1357 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1358 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1359 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1360 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1362 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1363 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1364 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1366 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1367 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1368 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1370 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1371 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1372 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1373 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1374 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1375 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1376 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1377 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1379 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1381 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1384 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1385 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1386 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1387 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1388 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1389 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1390 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1391 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1392 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1393 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1396 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1399 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1400 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1401 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1402 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1403 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1404 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1405 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1406 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1407 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1408 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1409 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1410 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1411 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1412 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1413 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1414 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1415 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1416 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1417 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1418 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1419 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1420 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1421 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1422 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1423 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1424 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1425 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1426 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1427 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1428 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1429 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1430 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1431 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1432 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1433 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1434 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1435 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1436 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1437 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1438 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1439 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1440 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1441 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1442 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1443 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1444 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1445 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1446 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1447 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1448 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1449 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1450 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1451 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1452 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1453 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1454 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1455 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1456 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1457 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1458 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1459 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1460 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1461 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1462 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1463 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1464 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1465 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1466 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1467 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1468 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1469 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1470 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1471 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1472 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1473 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1474 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1475 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1476 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1477 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1478 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1479 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1480 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1481 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1482 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1483 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1484 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1485 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1486 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1487 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1488 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1489 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1490 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1491 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1492 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1493 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1494 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1495 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1496 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1497 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1498 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1499 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1500 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1501 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1502 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1503 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1504 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1505 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1506 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1507 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1508 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1509 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1510 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1511 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1512 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1513 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1514 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1515 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1516 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1517 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1518 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1519 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1520 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1521 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1522 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1523 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1524 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1525 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1526 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1527 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1528 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1529 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1530 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1531 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1532 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1533 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1534 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1535 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1536 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1537 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1538 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1539 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1540 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1541 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1542 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1543 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1544 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1545 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1546 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1547 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1548 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1549 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1550 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1551 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1552 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1553 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1554 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1555 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1556 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1557 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1558 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1559 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1560 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1561 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1562 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1563 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1564 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1565 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1566 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1567 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1568 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1569 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1570 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1571 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1572 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1573 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1574 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1575 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1576 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1577 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1578 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1579 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1580 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1581 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1582 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1583 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1584 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1585 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1586 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U1587 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1588 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1589 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1590 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U1591 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U1592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1594 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1595 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1596 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1597 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1598 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1599 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1600 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1601 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1602 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1603 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1604 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1606 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U1607 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1608 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1609 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1610 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1611 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1612 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1613 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1614 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1615 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1616 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1617 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1618 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1619 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1620 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1621 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1622 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1623 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1624 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1625 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1626 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1627 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1628 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1629 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1630 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1631 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1632 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1633 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1634 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1635 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1636 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1637 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1638 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1639 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1640 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1641 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1642 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1643 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U1644 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1645 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1646 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1647 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1648 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1649 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1650 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1651 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1652 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1653 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1654 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1655 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1656 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1657 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1658 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1659 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1660 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1661 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1662 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1663 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1664 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1665 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1666 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U1667 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1668 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1669 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1670 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_dcache_U1671 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U1672 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1673 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1674 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1675 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1676 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1677 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1678 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1679 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1680 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1681 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1682 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U1683 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1684 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1685 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1686 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1687 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1688 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1689 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1690 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1691 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1692 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1693 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1694 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1695 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1696 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1697 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1698 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1699 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1700 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1701 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1702 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1703 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1704 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1705 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1706 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1707 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1708 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1709 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1710 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1711 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1712 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1713 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1714 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1715 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1716 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1717 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1718 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1719 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1720 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1721 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1722 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1723 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1724 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1725 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1726 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1727 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1728 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1729 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1730 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1731 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1732 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1733 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1734 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1735 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1736 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1737 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1738 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1739 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1740 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1741 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1742 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1743 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1744 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1745 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1746 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1747 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1748 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1749 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1750 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1751 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1752 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1753 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1754 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1755 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1756 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1757 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1758 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1759 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1760 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1761 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1762 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1763 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1764 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1765 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1766 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1767 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1768 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1769 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1770 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1771 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1772 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1773 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1774 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1775 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1776 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1777 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1778 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1779 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1780 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1781 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1782 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1783 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1784 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1785 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1786 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1787 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1788 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1789 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1790 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1791 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1792 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1793 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1794 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1795 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1796 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1797 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1798 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1799 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1800 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1801 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1802 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1803 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1804 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1805 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1806 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1807 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1808 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1809 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1810 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1811 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1812 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1813 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1814 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1815 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1816 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1817 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1818 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1819 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1820 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1821 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1822 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1823 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1824 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1825 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1826 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1827 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1828 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1829 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1830 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1831 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1832 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1833 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1834 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1835 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1836 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1837 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1838 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1839 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1840 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1841 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1842 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1843 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1844 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1845 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1846 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1847 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1848 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1849 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1850 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1851 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1852 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1853 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1854 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1855 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1856 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1857 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1858 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1859 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1860 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1861 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1862 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1863 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1864 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1865 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1866 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1867 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1868 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1869 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1870 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1871 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1872 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1873 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1874 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1875 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1876 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1877 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1878 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1879 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1880 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1881 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1882 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1883 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1884 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1885 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1886 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1887 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1888 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1889 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1890 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1891 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1892 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1893 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1894 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1895 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1896 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1897 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1898 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1899 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1900 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1901 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1902 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1903 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1904 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1905 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1906 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1907 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1908 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1909 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1910 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1911 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1912 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1913 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1914 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1915 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1916 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1917 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1918 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1919 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1920 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1921 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1922 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1923 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1924 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1925 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1926 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1927 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1928 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1929 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1930 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1931 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1932 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1933 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1934 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1935 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1936 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1937 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1938 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1939 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1940 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1941 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1942 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1943 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1944 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1945 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1946 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1947 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1948 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1949 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1950 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1951 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1952 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1953 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1954 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1955 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1956 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1957 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1958 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1959 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1960 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1961 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1962 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1963 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1964 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1965 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1966 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1967 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1968 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1969 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1970 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1971 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1972 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1973 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1974 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1975 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1976 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1977 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1978 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1979 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1980 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1981 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U1982 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1983 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1984 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1985 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1986 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1987 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1988 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1989 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1990 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1991 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1992 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1993 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U1994 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1995 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1996 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1997 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U1998 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U1999 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2000 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2001 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2002 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2003 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2004 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2005 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2006 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2007 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2008 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2009 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2010 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2011 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2012 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2013 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2014 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2015 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2016 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2017 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2018 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2019 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2020 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2021 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2022 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2023 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2024 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2025 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2026 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2027 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2028 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2029 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2030 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2031 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2032 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2033 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2034 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2035 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2036 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2037 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2038 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2039 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2040 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U2041 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2042 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2043 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2044 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2045 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2046 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2047 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2048 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2049 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2050 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2051 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2052 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2053 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2054 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2055 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2056 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2057 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_U2058 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2059 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2060 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2061 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2062 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2063 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2064 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2065 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2066 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2067 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2068 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2069 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2070 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2071 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2072 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2073 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2074 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2075 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2076 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2077 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2078 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2079 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2080 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2081 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2082 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2083 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2084 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2085 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2086 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2087 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2088 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2089 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2090 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2091 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2092 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2093 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2094 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2095 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2096 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2097 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2098 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2099 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2100 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2101 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2102 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2103 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2105 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2106 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2107 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2108 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2109 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2110 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2111 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2112 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2113 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2114 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2115 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2116 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2117 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2118 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2119 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2120 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2121 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2122 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2123 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2124 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2125 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2126 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2127 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2128 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2129 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2130 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2131 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2132 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2133 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2134 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2135 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2136 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2137 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2138 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2139 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2141 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2142 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2143 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2144 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2145 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2146 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2147 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2149 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2151 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2153 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2155 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2156 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2157 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2158 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2160 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2161 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2162 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2163 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2164 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2165 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2166 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2168 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2169 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2170 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2171 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2172 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2173 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2174 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2175 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2176 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2177 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2178 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2179 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2180 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2181 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2182 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2183 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2184 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2185 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2187 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2188 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2191 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2192 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2194 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2195 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2196 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2197 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2199 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2200 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2201 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2202 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2203 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2204 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2205 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2206 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2207 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2208 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2209 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2210 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2211 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2212 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2213 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2214 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2215 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2216 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2217 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2218 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2219 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2220 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2221 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2222 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2223 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2224 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2225 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2226 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2227 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2228 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2229 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2231 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2232 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2233 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2234 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2235 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2236 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2237 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2239 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2240 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2241 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2243 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2244 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2245 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2247 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2248 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2249 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2250 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2251 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2252 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2253 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2254 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2255 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2256 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2257 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2258 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2259 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2260 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2261 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2264 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2267 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2269 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2270 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2271 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2272 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2273 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2275 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2276 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2277 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2278 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2279 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2280 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2281 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2282 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2284 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2285 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2286 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2288 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2289 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2291 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2293 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2294 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2295 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2296 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2297 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2298 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2299 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2300 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2301 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2302 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2303 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2304 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2305 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2306 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2307 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2308 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2309 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2310 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2311 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2314 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2315 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2316 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2317 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2318 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2319 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2320 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2321 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2323 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2324 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2326 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2328 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2329 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2332 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2334 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2336 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2337 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2338 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2339 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2340 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2341 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2342 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2343 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2344 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2345 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2346 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2347 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2348 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2349 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2350 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2351 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2352 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2353 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2354 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2355 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2356 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2357 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2358 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2359 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2360 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2362 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2363 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2364 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2365 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2366 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2367 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2368 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2369 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2370 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2371 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2372 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2373 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2374 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2375 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2376 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2377 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2378 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2379 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2380 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2381 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2382 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2383 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2384 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2385 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2386 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2387 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2388 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2389 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2390 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2391 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2392 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2393 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2394 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2395 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2396 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2397 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2398 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2399 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2400 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2401 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2402 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2403 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2404 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2405 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2406 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2407 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2408 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2409 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2410 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2411 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2412 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2413 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2414 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2415 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2416 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2417 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2418 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2419 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2420 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2421 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2422 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2423 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2424 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2425 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2426 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2427 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2428 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2429 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2430 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2431 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2432 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2433 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2434 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2435 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2436 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2437 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2438 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2439 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2440 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2441 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2442 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2443 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2444 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2445 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2446 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2447 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2448 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2449 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2450 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2451 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2452 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2453 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2454 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2455 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2456 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2457 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2458 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2459 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2460 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2461 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2462 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2463 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2464 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2465 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2466 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2467 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2468 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2469 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2470 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2471 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2472 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2473 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2474 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2475 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2476 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2477 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2478 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2479 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2480 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2481 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2482 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2483 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2484 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2485 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2486 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2487 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2488 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2489 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2490 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2491 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2492 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2493 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2494 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2495 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2496 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2497 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2498 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2499 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2500 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2501 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2502 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2503 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2504 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2505 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2506 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2507 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2508 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2509 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2510 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2511 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2512 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2513 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2514 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2515 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2516 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2517 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2518 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2519 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2520 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2521 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2522 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2523 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2524 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2525 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2526 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2527 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2528 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2529 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2530 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2531 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2532 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2533 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2534 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2535 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2536 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2537 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2538 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2539 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2540 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2541 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2542 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2543 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2544 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2545 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2546 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2547 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2548 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2549 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2550 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2551 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2552 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2553 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2554 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2555 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2556 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2557 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2558 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2559 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2560 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2561 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2562 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2563 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2564 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2565 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2566 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2567 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2568 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2569 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2570 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2571 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2572 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2573 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2574 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2575 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2576 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2577 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2578 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2579 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2580 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2581 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2582 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2583 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2584 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2585 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2586 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2587 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2588 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2589 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2590 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2591 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2592 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2593 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2594 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2595 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2596 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2597 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2598 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2599 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2600 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2601 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2602 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2603 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2604 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U2605 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2606 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2630 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2635 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2638 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2639 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2640 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2641 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2642 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2643 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2644 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2645 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2646 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2647 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2648 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2649 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2650 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2651 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2652 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2653 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2654 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2655 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2656 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2657 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2658 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2659 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2660 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2661 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2662 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2663 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2664 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2665 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2666 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2667 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2668 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2669 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2670 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2671 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2672 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2673 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2674 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2675 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2676 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2677 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2678 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2679 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2680 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2681 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2682 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2683 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2684 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2685 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2686 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2687 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2688 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2689 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2690 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2691 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2692 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2693 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2694 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2695 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2696 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2697 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2698 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2699 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2700 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2701 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2702 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2703 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2704 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2705 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2706 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2707 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2708 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2709 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2710 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2711 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2712 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2713 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2714 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2715 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2716 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2717 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2718 + AOI21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +VX_dmem_controller_dcache_U2719 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2720 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2721 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2722 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2723 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2724 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2725 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2726 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2727 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2728 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2729 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2730 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2731 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2732 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2733 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2734 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2735 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2736 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2737 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2738 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2739 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2740 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2741 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2742 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2743 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2744 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2745 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2746 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2747 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2748 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2749 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2750 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2759 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2760 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2761 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2762 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2763 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2764 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2765 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2766 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2767 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2768 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2769 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2770 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2771 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2772 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2773 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2782 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2783 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2784 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2785 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2786 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2787 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2788 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2789 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2790 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2791 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2792 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2793 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2794 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2795 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2796 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2797 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2798 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2799 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2800 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2801 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2802 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2803 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2804 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2805 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2806 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2807 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2808 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2809 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2810 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2811 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2812 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2813 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2814 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2815 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2816 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2817 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2818 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2819 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2820 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2821 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2822 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2823 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2824 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2825 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2826 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2827 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2828 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2829 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2830 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2831 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2832 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2833 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2834 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2835 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2836 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2837 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2838 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2839 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2840 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2841 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2842 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2843 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2844 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2845 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2846 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2847 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2848 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2849 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2850 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2851 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2852 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2853 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2854 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2855 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2856 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2857 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2858 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2859 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2860 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2861 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2862 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2863 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2864 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2865 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2866 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2867 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2868 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2869 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2870 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2871 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2872 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2873 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2874 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2875 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2876 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2877 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2878 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2879 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2880 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2881 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2882 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2883 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2884 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U2885 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2886 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2887 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2888 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2889 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2890 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2891 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2892 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2893 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2894 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2895 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2896 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2897 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2898 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2899 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2900 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2901 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2902 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2903 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2904 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2905 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2906 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2907 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2908 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2909 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2910 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U2911 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_U2912 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2913 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2914 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2915 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2916 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2917 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2918 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2919 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2920 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2921 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2922 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2923 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2924 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2925 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2926 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2927 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2928 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2929 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2930 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2931 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2932 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2933 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2934 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2935 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2936 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2937 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2938 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2939 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2940 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2941 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2942 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2943 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2944 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2945 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2946 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2947 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2948 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2949 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2950 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2951 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2952 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2953 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2954 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2955 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2956 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2957 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2958 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2959 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2960 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2961 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2962 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2963 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2964 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2965 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2966 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2967 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2968 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2969 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2970 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2971 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2972 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2973 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2974 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2975 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2976 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2977 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2978 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2979 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2980 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2981 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2982 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2983 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2984 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2985 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2986 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U2987 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2988 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2989 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2990 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2991 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2992 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2993 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2994 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2995 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2996 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2997 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U2998 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U2999 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3000 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3001 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3002 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3003 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3004 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3005 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3006 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3007 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3008 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3009 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3010 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3011 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3012 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3013 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3014 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3015 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3016 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3017 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3018 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3019 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3020 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3021 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3022 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3023 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3024 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3025 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3026 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3027 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3028 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3029 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3030 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3031 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3032 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3033 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3034 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3035 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3036 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3037 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3038 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3039 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3040 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3041 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3042 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3043 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3044 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3045 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3046 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3047 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3048 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3049 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3050 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3051 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3052 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3053 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3054 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3055 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3056 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3057 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3058 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3059 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3060 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3061 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3062 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3063 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3064 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3065 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3066 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3067 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3068 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3069 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3070 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3071 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3072 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3073 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3074 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3075 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3076 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3077 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3078 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3079 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3080 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3081 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3082 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3083 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3084 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3085 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3086 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3087 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3088 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3089 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3090 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3091 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3092 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3093 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3094 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3095 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3096 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3097 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3098 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3099 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3100 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3101 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3102 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3103 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3104 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3105 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3106 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3107 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3108 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3109 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3110 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3111 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3112 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3113 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3114 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3115 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3116 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3117 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3118 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3119 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3120 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3121 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3122 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3123 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3124 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3125 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3126 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3127 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3128 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3129 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3130 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3131 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3132 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3133 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3134 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3135 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3136 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3137 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3138 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3139 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3140 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3141 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3142 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3143 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3144 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3145 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3146 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3147 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3148 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3149 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3150 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3151 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3152 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3153 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3154 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3155 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3156 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3157 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3158 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3159 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3160 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3161 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3162 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3163 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3164 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3165 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3166 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3167 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3168 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3169 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3170 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3171 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3172 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3173 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3174 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3175 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3176 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3177 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3178 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3179 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3180 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3181 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3182 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3183 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3184 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3185 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3186 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3187 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3188 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3189 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3190 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3191 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3192 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3193 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3194 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3195 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3196 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3197 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3198 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3199 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3200 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3201 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3202 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3203 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3204 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3205 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3206 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3207 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3208 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3209 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3210 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3211 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3212 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3213 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3214 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3215 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3216 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3217 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3218 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3219 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3220 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3221 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3222 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3223 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3224 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3225 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3226 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3227 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3228 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3229 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3230 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3231 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3232 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3236 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3238 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3239 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3241 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3243 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3249 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3250 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3251 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3252 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3253 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3254 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3255 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3256 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3257 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3259 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3261 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3263 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3265 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3266 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3267 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3268 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3270 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3271 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3272 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3273 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3274 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3275 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3276 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3277 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3278 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3279 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3280 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3281 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3282 + OAI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_U3283 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3284 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3285 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_U3286 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_U3287 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3288 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_U3289 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3290 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3291 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3292 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3293 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3295 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3296 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3297 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3299 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3300 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3302 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_U3303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_U3304 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_evict_addr_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_evict_addr_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__27_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_0__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_1__31_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_2__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__24_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_final_data_read_reg_3__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_genblk1_0__choose_thread_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U4 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U5 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U6 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U7 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U9 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_0__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U3 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U4 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U7 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U9 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U10 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_1__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U3 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U5 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U6 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U7 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U9 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_2__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U3 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U5 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U6 + OAI21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U7 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U9 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_3__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U3 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U4 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U5 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U8 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U9 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_4__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U3 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U4 + OAI21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U6 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U8 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U10 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_5__choose_thread_U11 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U4 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U6 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U7 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U9 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U10 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_6__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U3 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U6 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U7 + OAI21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U8 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U9 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk1_7__choose_thread_U11 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U3 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U5 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U6 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U14 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U15 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U16 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U17 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U18 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U19 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U27 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U28 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U29 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U30 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U31 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U32 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U40 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U41 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U42 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U43 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U44 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U45 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U53 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U54 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U55 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U56 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U57 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U58 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U66 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U67 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U68 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U69 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U70 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U71 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U72 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U73 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U74 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U75 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U76 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U77 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U78 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U79 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U80 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U81 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U82 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U83 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U84 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U85 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U86 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U87 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U88 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U89 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U90 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U91 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U92 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U93 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U94 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U95 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U96 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U97 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U98 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U99 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U100 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U101 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U102 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U103 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U104 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U105 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U106 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U107 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U108 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U109 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U110 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U111 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U112 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U113 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U114 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U115 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U116 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U117 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U118 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U119 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U120 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U121 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U122 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U123 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U124 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U125 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U126 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U127 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U128 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U129 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U130 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U131 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U132 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U133 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U134 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U135 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U136 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U137 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U142 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U162 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U165 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U194 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U201 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U204 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U205 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U206 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U208 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U209 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U210 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U211 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U212 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U213 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U214 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U215 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U216 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U217 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U218 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U219 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U220 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U221 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U222 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U223 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U224 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U225 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U226 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U227 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U228 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U229 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U230 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U231 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U233 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U236 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U237 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U238 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U240 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U241 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U242 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U243 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U244 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U245 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U247 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U249 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U250 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U252 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U253 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U256 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U280 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U282 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U283 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U284 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U286 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U290 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U291 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U295 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U301 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U302 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U303 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U304 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U305 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U310 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U312 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U316 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U323 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U334 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U335 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U336 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U337 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U345 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U346 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U347 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U348 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U349 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U350 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U358 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U360 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U363 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U371 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U373 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U375 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U381 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U384 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U385 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U386 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U387 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U388 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U389 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U390 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U391 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U393 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U394 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U396 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U400 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U401 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U402 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U403 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U404 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U405 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U407 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U408 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U409 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U410 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U411 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U412 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U413 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U414 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U415 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U416 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U417 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U418 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U419 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U420 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U421 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U422 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U423 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U424 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U425 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U426 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U427 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U428 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U429 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U430 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U431 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U432 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U433 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U434 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U435 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U436 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U437 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U438 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U439 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U440 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U441 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U442 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U443 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U444 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U445 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U446 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U447 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U448 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U449 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U450 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U451 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U452 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U453 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U454 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U455 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U456 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U457 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U458 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U459 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U460 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U461 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U462 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U463 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U464 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U465 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U466 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U467 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U468 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U469 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U470 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U471 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U472 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U473 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U474 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U475 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U476 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U477 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U478 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U479 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U480 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U481 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U482 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U483 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U484 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U485 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U486 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U487 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U488 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U489 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U490 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U491 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U492 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U493 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U494 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U495 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U496 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U497 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U498 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U499 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U500 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U501 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U502 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U503 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U504 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U505 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U506 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U507 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U508 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U509 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U510 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U511 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U559 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U560 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U561 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U562 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U563 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U564 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U565 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U566 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U567 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U568 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U569 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U570 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U571 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U572 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U573 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U574 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U575 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U576 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U577 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U578 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U579 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U580 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U581 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U582 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U583 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U584 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U585 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U586 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U587 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U588 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U590 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U591 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U593 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U594 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U595 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U596 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U597 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U598 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U599 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U600 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U601 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U602 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U603 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U604 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U606 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U609 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U638 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U639 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U640 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_U641 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U28 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U30 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U31 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U32 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U33 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U34 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U35 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U44 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U45 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U46 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U47 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U48 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U52 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U53 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_U54 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_0__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_1__bank_structure_U3 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U5 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U6 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U7 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U8 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U9 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U10 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U11 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U12 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U13 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U14 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U15 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U16 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U17 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U18 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U19 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U20 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U21 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U22 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U23 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U24 + INV_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U25 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U26 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U27 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U28 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U29 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U30 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U31 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U32 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U33 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U34 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U35 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U36 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U37 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U38 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U39 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U40 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U41 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U42 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U44 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U45 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U46 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U47 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U48 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U49 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U50 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U51 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U52 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U60 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U61 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U62 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U63 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U64 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U65 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U73 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U74 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U75 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U76 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U77 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U78 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U86 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U87 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U88 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U89 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U90 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U91 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U99 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U100 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U101 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U102 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U103 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U112 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U113 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U114 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U115 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U116 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U117 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U119 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U120 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U121 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U122 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U123 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U124 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U125 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U126 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U127 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U130 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U133 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U135 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U165 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U179 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U194 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U201 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U203 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U204 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U205 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U206 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U207 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U208 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U209 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U210 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U211 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U213 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U214 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U215 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U216 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U217 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U218 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U219 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U220 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U221 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U222 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U223 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U224 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U225 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U226 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U227 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U228 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U229 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U230 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U231 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U232 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U233 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U234 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U235 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U236 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U237 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U238 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U239 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U240 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U241 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U242 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U243 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U244 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U245 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U246 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U247 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U248 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U250 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U251 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U252 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U253 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U254 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U255 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U256 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U257 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U258 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U261 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U266 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U277 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U279 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U284 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U285 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U287 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U292 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U299 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U301 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U304 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U309 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U310 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U311 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U312 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U314 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U316 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U323 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U325 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U326 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U327 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U334 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U336 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U338 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U339 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U340 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U342 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U346 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U347 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U353 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U354 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U356 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U357 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U358 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U360 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U361 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U363 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U364 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U365 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U367 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U370 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U373 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U375 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U380 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U381 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U384 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U385 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U386 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U387 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U388 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U389 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U390 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U391 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U393 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U396 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U404 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U405 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U407 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U408 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U409 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U418 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U431 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U432 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U433 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U434 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U435 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U443 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U444 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U445 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U446 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U447 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U448 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U449 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U450 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U451 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U452 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U453 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U454 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U455 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U456 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U457 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U458 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U459 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U460 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U461 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U462 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U463 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U464 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U465 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U466 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U467 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U468 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U469 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U470 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U471 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U472 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U473 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U474 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U475 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U476 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U477 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U478 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U479 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U480 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U488 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U489 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U490 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U491 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U492 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U493 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U501 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U502 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U503 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U504 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U505 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U506 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U514 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U515 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U516 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U517 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U518 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U519 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U520 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U521 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U522 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U555 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U557 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U566 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U567 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U568 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U569 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U570 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U579 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U580 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U581 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U582 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U583 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U584 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U592 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U593 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U594 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U595 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U596 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U597 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U605 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U606 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U607 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U608 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U609 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U610 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U611 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U612 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U613 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U614 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U616 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U635 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U638 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U639 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U640 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_U641 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U3 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U4 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U6 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U7 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U8 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U9 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U10 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U11 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U12 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U13 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U14 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U15 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U16 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U17 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U18 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U19 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U20 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U22 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U24 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U25 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U26 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U28 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U30 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U31 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U32 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U33 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U44 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U45 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U46 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U47 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U48 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U49 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U53 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_U54 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_1__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_2__bank_structure_U3 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U4 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U5 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U6 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U7 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U8 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U9 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U10 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U11 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U14 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U15 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U16 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U19 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U20 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U21 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U22 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U23 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U24 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U25 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U26 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U27 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U28 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U29 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U63 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U64 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U65 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U66 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U67 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U68 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U76 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U77 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U78 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U79 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U80 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U81 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U89 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U90 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U91 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U92 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U93 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U94 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U102 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U107 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U116 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U119 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U130 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U133 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U186 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U187 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U188 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U189 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U190 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U191 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U192 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U193 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U194 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U195 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U196 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U197 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U198 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U199 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U200 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U201 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U202 + AOI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U203 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U204 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U205 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U206 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U207 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U208 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U209 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U210 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U211 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U219 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U220 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U221 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U224 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U232 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U233 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U234 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U237 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U245 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U246 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U247 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U249 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U250 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U258 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U260 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U263 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U264 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U284 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U301 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U304 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U305 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U310 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U313 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U316 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U323 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U334 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U336 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U338 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U339 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U340 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U342 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U346 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U347 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U353 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U354 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U356 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U357 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U358 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U360 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U363 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U364 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U367 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U370 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U373 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U375 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U381 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U382 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U383 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U384 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U385 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U386 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U387 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U388 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U389 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U390 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U391 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U392 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U393 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U394 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U395 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U396 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U397 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U398 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U399 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U400 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U401 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U402 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U403 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U404 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U405 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U406 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U407 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U408 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U409 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U410 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U411 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U412 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U413 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U414 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U415 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U416 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U417 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U418 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U419 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U420 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U421 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U422 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U423 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U426 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U427 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U428 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U430 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U431 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U433 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U434 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U435 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U437 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U440 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U443 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U444 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U445 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U446 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U447 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U448 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U449 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U450 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U451 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U452 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U453 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U454 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U455 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U456 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U457 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U458 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U459 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U460 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U461 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U462 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U463 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U464 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U465 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U466 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U467 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U468 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U469 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U470 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U471 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U472 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U473 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U474 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U475 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U476 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U477 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U478 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U479 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U480 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U481 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U482 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U483 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U484 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U485 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U486 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U487 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U488 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U489 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U490 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U491 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U492 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U493 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U494 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U495 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U496 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U497 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U498 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U499 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U500 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U501 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U502 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U503 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U504 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U505 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U506 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U508 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U541 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U542 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U543 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U544 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U545 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U546 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U547 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U549 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U550 + OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U551 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U552 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U553 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U554 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U555 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U556 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U557 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U558 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U559 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U560 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U561 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U562 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U563 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U564 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U565 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U566 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U567 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U568 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U569 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U570 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U571 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U572 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U573 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U574 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U575 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U576 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U577 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U578 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U579 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U580 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U581 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U582 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U583 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U584 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U585 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U586 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U587 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U588 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U589 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U590 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U592 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U597 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U611 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U612 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U617 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U618 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_U619 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U4 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U6 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U7 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U8 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U9 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U10 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U11 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U12 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U13 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U14 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U15 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U16 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U17 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U18 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U19 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U21 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U30 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U31 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U32 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U33 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U34 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U35 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U36 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U44 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U45 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U46 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U47 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U48 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U49 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_2__bank_structure_data_structures_U50 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U10 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U11 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U12 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U13 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U14 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U15 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U23 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U24 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U25 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U26 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U27 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U28 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U36 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U37 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U38 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U40 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U41 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U49 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U50 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U52 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U53 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U54 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U62 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U63 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U64 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U65 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U66 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U67 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U68 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U69 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U70 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U71 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U72 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U73 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U74 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U75 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U76 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U77 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U78 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U79 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U80 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U88 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U89 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U90 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U91 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U92 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U93 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U101 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U102 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U103 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U105 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U106 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U114 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U115 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U116 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U117 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U118 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U119 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U127 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U128 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U129 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U130 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U131 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U132 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U140 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U141 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U142 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U143 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U144 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U145 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U153 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U154 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U155 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U156 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U157 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U158 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U166 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U167 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U168 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U169 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U170 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U171 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U179 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U180 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U181 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U182 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U183 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U184 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U192 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U193 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U194 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U195 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U196 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U197 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U198 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U199 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U200 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U201 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U202 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U203 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U204 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U205 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U206 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U207 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U208 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U209 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U210 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U211 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U213 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U214 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U215 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U216 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U217 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U218 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U220 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U221 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U222 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U223 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U224 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U228 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U238 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U240 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U241 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U242 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U243 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U244 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U245 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U246 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U247 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U248 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U249 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U250 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U251 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U252 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U253 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U254 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U255 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U256 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U257 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U258 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U259 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U260 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U261 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U262 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U263 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U264 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U265 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U266 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U267 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U268 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U269 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U270 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U271 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U272 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U273 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U274 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U275 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U276 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U277 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U278 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U279 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U280 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U281 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U282 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U283 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U284 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U285 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U286 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U287 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U288 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U289 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U290 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U291 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U292 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U293 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U294 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U295 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U296 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U297 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U300 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U302 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U304 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U305 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U317 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U327 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U329 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U330 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U331 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U332 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U333 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U334 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U335 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U336 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U337 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U339 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U340 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U341 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U342 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U343 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U344 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U345 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U346 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U347 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U348 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U349 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U350 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U351 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U352 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U353 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U354 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U355 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U356 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U357 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U358 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U359 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U360 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U361 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U362 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U363 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U364 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U365 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U366 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U367 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U368 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U369 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U370 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U371 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U372 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U373 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U374 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U375 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U376 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U377 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U378 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U379 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U380 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U381 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U382 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U383 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U384 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U385 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U386 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U387 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U388 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U389 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U390 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U391 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U392 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U393 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U394 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U395 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U396 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U397 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U398 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U399 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U400 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U401 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U402 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U403 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U404 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U405 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U406 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U407 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U408 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U409 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U410 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U411 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U412 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U413 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U414 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U415 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U416 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U417 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U418 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U419 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U420 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U421 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U422 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U423 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U424 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U425 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U426 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U427 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U428 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U429 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U430 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U431 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U432 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U433 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U434 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U435 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U436 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U437 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U438 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U439 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U440 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U441 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U442 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U443 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U444 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U445 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U446 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U447 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U448 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U449 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U450 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U451 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U452 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U453 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U454 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U455 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U456 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U457 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U458 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U459 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U460 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U461 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U462 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U463 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U464 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U465 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U466 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U467 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U468 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U469 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U470 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U471 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U474 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U475 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U476 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U477 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U478 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U479 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U480 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U481 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U484 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U485 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U486 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U487 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U488 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U489 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U490 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U491 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U494 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U501 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U505 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U506 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U513 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U515 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U516 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U517 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U518 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U519 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U520 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U526 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U527 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_U529 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U3 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U4 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U5 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U6 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U42 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U49 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U53 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_U54 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_3__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_4__bank_structure_U3 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U4 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U5 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U6 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U7 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U8 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U9 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U10 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U11 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U12 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U13 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U21 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U22 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U23 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U24 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U25 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U26 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U34 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U35 + OAI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U36 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U37 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U38 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U39 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U47 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U48 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U49 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U50 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U51 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U52 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U60 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U61 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U62 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U63 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U64 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U65 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U73 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U74 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U75 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U76 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U77 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U78 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U86 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U87 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U88 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U89 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U90 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U91 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U92 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U93 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U94 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U95 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U96 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U97 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U98 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U99 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U101 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U102 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U105 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U106 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U107 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U108 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U111 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U112 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U113 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U116 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U125 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U126 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U127 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U128 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U129 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U130 + OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U133 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U135 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U139 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U141 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U142 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U143 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U144 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U159 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U161 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U163 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U165 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U169 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U172 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U175 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U177 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U179 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U180 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U181 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U182 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U183 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U184 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U185 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U186 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U187 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U188 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U189 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U190 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U191 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U192 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U193 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U195 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U196 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U197 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U198 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U199 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U200 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U201 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U202 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U203 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U205 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U206 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U208 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U209 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U210 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U211 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U212 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U213 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U214 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U215 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U216 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U217 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U218 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U219 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U220 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U221 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U222 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U223 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U224 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U225 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U229 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U230 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U231 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U232 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U233 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U234 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U236 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U237 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U238 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U241 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U244 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U245 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U246 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U247 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U249 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U250 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U252 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U253 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U256 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U261 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U270 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U271 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U275 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U276 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U277 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U280 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U283 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U284 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U287 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U295 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U301 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U302 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U304 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U310 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U316 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U317 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U321 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U323 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U324 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U325 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U328 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U334 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U335 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U336 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U337 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U338 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U339 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U340 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U342 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U346 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U347 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U351 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U353 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U354 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U356 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U357 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U358 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U360 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U361 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U363 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U364 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U365 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U367 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U370 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U373 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U374 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U375 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U381 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U383 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U384 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U385 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U386 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U387 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U388 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U389 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U390 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U391 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U393 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U394 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U396 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U400 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U401 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U402 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U403 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U404 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U405 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U406 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U407 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U408 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U409 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U410 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U411 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U412 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U413 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U414 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U415 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U416 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U417 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U418 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U419 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U420 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U421 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U422 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U423 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U424 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U425 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U426 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U427 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U428 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U429 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U430 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U431 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U432 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U433 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U434 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U435 + AOI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U436 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U437 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U440 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U441 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U443 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U444 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U445 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U449 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U450 + OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U455 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U457 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U459 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U460 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U461 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U462 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U463 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U464 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U465 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U466 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U467 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U468 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U469 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U470 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U471 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U472 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U473 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U474 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U475 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U476 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U477 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U478 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U479 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U480 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U481 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U482 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U483 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U484 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U485 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U486 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U487 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U488 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U489 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U490 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U491 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U492 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U493 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U494 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U495 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U496 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U497 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U498 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U499 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U500 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U501 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U502 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U503 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U504 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U505 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U506 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U507 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U508 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U509 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U510 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U511 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U512 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U513 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U514 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U515 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U516 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U517 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U518 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U519 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U520 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U522 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U555 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U557 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U559 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U560 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U561 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U562 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U563 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U564 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U565 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U566 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U567 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U568 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U569 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U570 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U571 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U572 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U573 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U574 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U575 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U576 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U577 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U578 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U579 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U580 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U581 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U583 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U585 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U586 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U587 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U588 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U590 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U591 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U593 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U594 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U595 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U596 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U597 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U599 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U608 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U609 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U610 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U611 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U612 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U613 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U614 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U617 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_U618 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U3 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U4 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U5 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U6 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U7 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U8 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U9 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U10 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U11 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U12 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U13 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U14 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U15 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U16 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U19 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U20 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U25 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U26 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U28 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U29 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U30 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U31 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U32 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U33 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U34 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U36 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U44 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U45 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U46 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U47 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U48 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U49 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U50 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U53 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_U54 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_4__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_5__bank_structure_U3 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U4 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U5 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U6 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U8 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U9 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U10 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U11 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U14 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U15 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U16 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U17 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U18 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U19 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U20 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U21 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U22 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U23 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U24 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U25 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U26 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U27 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U28 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U29 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U30 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U31 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U32 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U33 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U34 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U35 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U36 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U37 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U38 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U39 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U47 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U48 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U49 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U50 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U51 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U52 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U60 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U61 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U62 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U63 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U64 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U65 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U73 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U74 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U75 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U76 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U77 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U78 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U86 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U87 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U88 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U89 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U90 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U91 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U92 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U93 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U94 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U95 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U96 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U97 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U98 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U99 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U100 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U101 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U102 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U103 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U105 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U106 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U107 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U108 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U109 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U110 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U111 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U112 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U113 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U114 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U116 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U117 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U119 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U120 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U121 + AOI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U122 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U123 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U125 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U126 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U127 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U128 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U129 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U130 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U131 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U132 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U133 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U134 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U136 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U138 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U140 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U142 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U143 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U144 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U145 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U146 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U165 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U166 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U194 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U200 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U201 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U202 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U203 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U204 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U205 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U206 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U207 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U208 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U209 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U210 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U211 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U212 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U213 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U214 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U215 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U216 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U217 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U218 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U219 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U220 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U221 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U222 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U223 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U224 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U225 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U226 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U227 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U228 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U229 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U230 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U231 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U232 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U233 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U235 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U236 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U237 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U238 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U239 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U240 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U244 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U249 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U250 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U251 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U252 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U253 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U254 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U256 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U259 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U264 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U280 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U281 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U283 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U284 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U285 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U286 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U289 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U294 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U295 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U296 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U297 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U298 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U301 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U303 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U304 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U305 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U308 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U309 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U310 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U311 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U316 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U320 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U321 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U323 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U324 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U334 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U336 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U338 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U339 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U340 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U341 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U342 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U346 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U347 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U350 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U351 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U353 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U354 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U356 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U357 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U358 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U359 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U360 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U363 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U364 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U367 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U370 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U372 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U373 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U375 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U376 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U379 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U381 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U382 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U384 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U385 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U386 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U387 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U388 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U389 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U390 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U391 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U393 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U396 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U400 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U401 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U402 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U403 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U404 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U405 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U407 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U408 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U409 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U410 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U411 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U412 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U413 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U414 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U415 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U416 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U418 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U419 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U421 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U424 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U425 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U426 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U428 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U429 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U430 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U431 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U432 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U433 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U434 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U435 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U436 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U437 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U438 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U439 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U440 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U441 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U442 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U443 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U444 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U445 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U446 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U447 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U448 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U449 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U450 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U451 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U452 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U453 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U454 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U455 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U456 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U457 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U458 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U459 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U460 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U461 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U462 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U463 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U464 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U465 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U466 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U467 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U468 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U469 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U470 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U471 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U472 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U473 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U474 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U475 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U476 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U477 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U478 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U479 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U480 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U481 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U482 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U483 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U484 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U485 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U486 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U487 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U488 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U489 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U490 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U491 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U492 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U493 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U494 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U495 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U496 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U497 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U498 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U499 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U500 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U501 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U502 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U503 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U504 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U505 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U506 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U507 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U508 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U509 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U510 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U511 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U551 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U552 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U553 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U554 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U555 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U556 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U557 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U558 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U559 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U560 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U561 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U562 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U563 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U564 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U565 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U566 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U567 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U568 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U569 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U570 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U571 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U572 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U573 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U574 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U575 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U576 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U577 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U578 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U579 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U580 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U581 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U583 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U585 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U586 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U587 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U588 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U590 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U591 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U593 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U594 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U595 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U597 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U635 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U636 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U645 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U647 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U648 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_U649 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U31 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U32 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U33 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U34 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U35 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U38 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 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1.458000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U53 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_U54 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_5__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_6__bank_structure_U3 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U5 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U6 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U7 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U8 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U9 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U10 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U11 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U12 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U13 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U14 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U15 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U16 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U17 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U18 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U19 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U20 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U21 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U22 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U23 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U24 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U25 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U26 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U27 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U28 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U29 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U30 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U31 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U32 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U33 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U34 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U35 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U36 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U37 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U38 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U39 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U40 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U41 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U42 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U43 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U44 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U45 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U46 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U47 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U48 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U49 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U50 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U51 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U52 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U53 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U61 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U62 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U63 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U64 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U65 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U66 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U74 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U75 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U76 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U77 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U78 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U79 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U80 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U81 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U82 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U83 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U84 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U85 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U86 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U87 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U88 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U89 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U90 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U91 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U92 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U93 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U94 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U95 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U96 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U97 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U98 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U99 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U100 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U101 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U102 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U103 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U104 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U105 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U106 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U107 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U108 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U109 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U110 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U111 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U112 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U113 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U114 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U116 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U117 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U119 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U121 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U123 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U124 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U126 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U127 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U129 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U130 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U133 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U135 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U145 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U146 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U147 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U149 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U151 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U153 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U154 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U155 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U156 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U157 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U158 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U161 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U163 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U164 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U165 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U166 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U167 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U168 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U169 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U174 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U175 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U176 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U178 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U179 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U180 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U186 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U187 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U191 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U192 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U194 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U195 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U196 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U197 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U198 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U201 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U202 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U203 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U204 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U205 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U206 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U207 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U208 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U209 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U210 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U211 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U212 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U213 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U214 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U215 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U216 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U217 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U218 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U219 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U220 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U221 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U222 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U223 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U224 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U225 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U226 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U227 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U228 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U229 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U230 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U231 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U232 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U233 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U234 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U237 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U238 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U239 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U240 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U243 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U246 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U249 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U250 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U251 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U252 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U253 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U254 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U255 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U256 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U257 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U258 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U259 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U260 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U261 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U262 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U263 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U264 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U265 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U268 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U269 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U270 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U271 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U272 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U274 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U278 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U279 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U280 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U281 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U283 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U284 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U285 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U286 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U288 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U289 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U290 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U291 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U292 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U293 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U295 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U296 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U297 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U298 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U300 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U301 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U302 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U303 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U304 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U305 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U306 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U307 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U308 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U309 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U310 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U311 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U314 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U315 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U316 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U319 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U320 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U321 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U322 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U323 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U324 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U325 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U326 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U328 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U329 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U330 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U334 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U336 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U337 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U338 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U339 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U340 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U342 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U346 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U347 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U348 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U349 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U350 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U352 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U353 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U354 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U355 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U356 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U357 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U358 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U360 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U361 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U362 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U363 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U364 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U366 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U367 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U368 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U370 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U372 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U373 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U374 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U375 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U376 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U377 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U378 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U381 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U382 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U383 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U384 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U385 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U386 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U387 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U388 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U389 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U390 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U391 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U392 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U393 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U394 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U395 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U396 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U400 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U401 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U402 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U403 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U404 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U405 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U407 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U408 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U409 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U410 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U411 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U412 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U413 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U414 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U415 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U416 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U418 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U419 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U421 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U422 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U423 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U424 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U425 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U426 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U427 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U428 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U429 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U430 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U431 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U432 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U433 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U434 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U435 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U436 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U437 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U438 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U439 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U440 + AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U441 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U442 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U443 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U444 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U445 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U446 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U447 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U448 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U449 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U450 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U451 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U452 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U453 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U454 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U455 + OAI21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U456 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U457 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U458 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U459 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U460 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U461 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U462 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U463 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U464 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U465 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U466 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U467 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U468 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U469 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U470 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U471 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U472 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U473 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U474 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U475 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U476 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U477 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U478 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U479 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U480 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U481 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U482 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U483 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U484 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U485 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U486 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U487 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U488 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U489 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U490 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U491 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U492 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U493 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U494 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U495 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U496 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U497 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U498 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U499 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U500 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U501 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U502 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U503 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U504 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U505 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U506 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U507 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U508 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U509 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U510 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U511 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U512 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U513 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U514 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U515 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U516 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U555 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U556 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U557 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U558 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U559 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U560 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U561 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U562 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U563 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U564 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U565 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U566 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U567 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U568 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U569 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U570 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U571 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U572 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U573 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U574 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U575 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U576 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U577 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U578 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U579 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U580 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U581 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U583 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U585 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U586 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U587 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U588 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U590 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U591 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U593 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U594 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U595 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U597 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U598 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U630 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U635 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U637 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U638 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U639 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U640 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U641 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U642 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U643 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U645 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U647 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U648 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U649 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_U650 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U3 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U4 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U5 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U6 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U7 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U8 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U9 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U10 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U11 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U12 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U13 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U14 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U15 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U16 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U17 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U18 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U19 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U20 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U21 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U22 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U25 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U26 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U28 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U29 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U30 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U31 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U32 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U33 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U34 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U35 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U44 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U45 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U46 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U47 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U48 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U52 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U53 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_U54 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_6__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_genblk3_7__bank_structure_U3 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U4 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U5 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U6 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U7 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U8 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U9 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U10 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U11 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U13 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U14 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U15 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U16 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U17 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U18 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U19 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U20 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U21 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U22 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U23 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U24 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U25 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U26 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U27 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U28 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U29 + AND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U30 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U31 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U32 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U33 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U34 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U35 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U36 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U37 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U38 + AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U40 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U42 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U43 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U44 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U45 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U46 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U47 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U48 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U49 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U50 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U51 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U52 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U53 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U54 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U55 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U56 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U57 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U58 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U59 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U60 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U61 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U62 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U63 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U64 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U65 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U66 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U67 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U68 + AOI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U69 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U70 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U71 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U72 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U73 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U74 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U75 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U76 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U77 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U78 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U79 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U80 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U81 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U82 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U83 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U84 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U85 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U86 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U87 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U88 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U89 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U90 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U91 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U92 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U93 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U94 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U95 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U96 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U97 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U98 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U99 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U100 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U101 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U102 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U103 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U104 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U105 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U106 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U107 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U108 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U109 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U110 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U111 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U112 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U113 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U114 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U115 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U116 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U117 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U119 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U120 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U121 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U122 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U123 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U124 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U126 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U127 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U128 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U129 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U130 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U131 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U133 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U134 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U135 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U137 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U138 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U139 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U140 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U141 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U142 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U143 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U144 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U145 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U146 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U147 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U148 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U149 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U150 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U151 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U152 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U154 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U155 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U156 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U157 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U158 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U160 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U161 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U162 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U163 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U164 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U165 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U167 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U168 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U169 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U170 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U171 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U172 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U173 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U174 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U175 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U176 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U177 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U178 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U179 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U180 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U181 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U182 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U183 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U184 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U185 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U186 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U187 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U188 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U189 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U190 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U191 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U192 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U193 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U194 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U195 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U196 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U197 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U198 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U199 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U200 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U201 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U202 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U203 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U204 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U205 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U206 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U207 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U208 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U209 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U210 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U211 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U212 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U213 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U214 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U215 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U216 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U217 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U218 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U219 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U220 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U221 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U222 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U223 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U225 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U228 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U232 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U233 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U235 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U236 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U238 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U239 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U240 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U241 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U242 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U243 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U244 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U245 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U246 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U247 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U248 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U249 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U250 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U251 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U252 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U253 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U254 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U255 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U256 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U257 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U258 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U259 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U260 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U261 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U262 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U263 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U264 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U265 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U266 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U267 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U268 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U269 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U270 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U271 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U272 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U273 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U274 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U275 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U276 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U277 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U278 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U279 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U280 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U281 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U282 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U283 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U284 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U285 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U286 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U287 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U288 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U289 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U290 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U291 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U292 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U293 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U294 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U295 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U296 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U297 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U298 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U299 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U300 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U301 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U302 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U303 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U304 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U305 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U317 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U327 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U338 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U339 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U340 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U341 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U342 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U343 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U344 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U345 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U346 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U347 + AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U348 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U351 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U352 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U353 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U354 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U355 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U357 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U358 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U359 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U360 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U361 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U362 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U363 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U364 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U365 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U366 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U367 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U368 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U369 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U370 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U371 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U372 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U373 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U374 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U375 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U376 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U377 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U378 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U379 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U380 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U381 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U382 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U383 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U384 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U385 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U386 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U387 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U388 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U389 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U390 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U391 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U392 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U393 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U394 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U395 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U396 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U397 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U398 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U399 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U400 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U401 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U402 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U403 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U404 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U405 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U406 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U407 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U408 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U409 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U410 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U411 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U412 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U413 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U414 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U415 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U416 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U417 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U418 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U419 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U420 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U421 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U422 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U423 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U424 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U425 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U426 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U427 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U428 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U429 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U430 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U431 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U432 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U433 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U434 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U435 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U436 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U437 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U438 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U439 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U440 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U441 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U442 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U443 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U444 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U445 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U446 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U447 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U448 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U449 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U450 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U451 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U452 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U453 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U454 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U455 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U456 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U457 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U458 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U459 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U460 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U461 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U462 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U463 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U464 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U465 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U466 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U467 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U468 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U469 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U470 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U471 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U472 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U474 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U475 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U476 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U477 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U478 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U479 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U480 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U481 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U484 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U485 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U486 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U487 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U488 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U489 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U490 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U491 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U494 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U501 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U505 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U506 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U516 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U517 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U518 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U519 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U520 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U521 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U527 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U528 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_U529 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U3 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U4 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U5 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U8 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U9 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U10 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U11 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U12 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U13 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U14 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U15 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U16 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U17 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U18 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U19 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U20 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U21 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U22 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U25 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U27 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U28 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U29 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U30 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U31 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U32 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U33 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U34 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U35 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U36 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U37 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U38 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U39 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U40 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U41 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U42 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U43 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U44 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U45 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U46 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U47 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U48 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U49 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U50 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U51 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U53 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U54 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_U55 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_data + rf2_256x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 21325.878906 + b, d +VX_dmem_controller_dcache_genblk3_7__bank_structure_data_structures_meta + rf2_256x19_wm0 USERLIB_ss_0p81v_0p81v_m40c + 5188.820801 + b, d +VX_dmem_controller_dcache_get_miss_index_U3 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_get_miss_index_U4 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U6 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U7 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U9 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_get_miss_index_U10 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_get_miss_index_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_get_miss_index_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_get_miss_index_U13 + OA21A1OI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_dcache_get_miss_index_U14 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_get_miss_index_U15 + OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_dcache_get_miss_index_U16 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_get_miss_index_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_get_miss_index_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_get_miss_index_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_miss_addr_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_miss_addr_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_multip_banks_U2 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U3 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U4 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U6 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U7 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U8 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U9 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U10 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U11 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U12 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U13 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U14 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U15 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U16 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U17 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U18 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U19 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U21 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U22 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U23 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U25 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U27 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U28 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U30 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U31 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U32 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U33 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U34 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U35 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U36 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U37 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U38 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U40 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U41 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U42 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U43 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U44 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_dcache_multip_banks_U45 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U46 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U47 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U50 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U51 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U52 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U53 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U54 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U55 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U56 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U57 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U58 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U59 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U60 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U61 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_dcache_multip_banks_U62 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U63 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U64 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_multip_banks_U65 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_dcache_state_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_state_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_1_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +VX_dmem_controller_dcache_stored_valid_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_dcache_stored_valid_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_U3 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U4 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U5 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U6 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U7 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U9 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U10 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U16 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U22 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U23 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U26 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U27 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U28 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U29 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U30 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U31 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U32 + INV_X1M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U213 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U214 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U215 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U218 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U219 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U228 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U229 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U231 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U233 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U237 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U238 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U240 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U244 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U245 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U247 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U248 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U250 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U251 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U252 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U254 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U255 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U256 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U257 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U258 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U259 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U260 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U261 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U262 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U263 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U264 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U265 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U266 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U267 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U268 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U269 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U270 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U271 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U272 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U273 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U274 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U275 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U276 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U277 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U278 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U279 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U280 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U281 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U282 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U283 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U284 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U285 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U286 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U287 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U288 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U289 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U290 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U291 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U292 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U293 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U294 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U295 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U296 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U297 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U298 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U299 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U300 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U301 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U302 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U303 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U304 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U305 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U306 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U307 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U308 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U309 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_U310 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U311 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U312 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U313 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U314 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U315 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U316 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U317 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U318 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U319 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U320 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U321 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U322 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U323 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U324 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U325 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U326 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U327 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U328 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U329 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U330 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U331 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U332 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U333 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U334 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U335 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U336 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U337 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U338 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U339 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U340 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U341 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U342 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U343 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U344 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U345 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U346 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U347 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U348 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U349 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U350 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U351 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U352 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U353 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U354 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U355 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U356 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U357 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U358 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U359 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U360 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U361 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U362 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U363 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U364 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U365 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U366 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U367 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U368 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U369 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U370 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U371 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U372 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U373 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U374 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U375 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U376 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U377 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U378 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U379 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U380 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U381 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U382 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U383 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U384 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U385 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U386 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U387 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U388 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U389 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U390 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U391 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U392 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U393 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U394 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U395 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U396 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U397 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U398 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U399 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U400 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U401 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U402 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U403 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U404 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U405 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U406 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U407 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U408 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U409 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U410 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U411 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U412 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U413 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U414 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U415 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U416 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U417 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U418 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U419 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U420 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U421 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U422 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U423 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U424 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U425 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U426 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U427 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U428 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U429 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U430 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U431 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U432 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U433 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U434 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U435 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U436 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U437 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U438 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U439 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U440 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U441 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U442 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U443 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U444 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U445 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U446 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U447 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U448 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U449 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U450 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U451 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U452 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U453 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U454 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U455 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U456 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U457 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U458 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U459 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U460 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U461 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U462 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U463 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U464 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U465 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U466 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U467 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U468 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U469 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U470 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U471 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U472 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U473 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U474 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U475 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U476 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U477 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U478 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U479 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U480 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U481 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U482 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U483 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U484 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U485 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U486 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U487 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U488 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U489 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U490 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U491 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U492 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U493 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U494 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U495 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U496 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U497 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U498 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U499 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U500 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U501 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U502 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U503 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U504 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U505 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U506 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U507 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U508 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U509 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U510 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U511 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U512 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U513 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U514 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U515 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U516 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U517 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U518 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U519 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U520 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U521 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U522 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U523 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U524 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U525 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U526 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U527 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U528 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U529 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U530 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U531 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U532 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U533 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U534 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U535 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U536 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U537 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U538 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U539 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U540 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U541 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U542 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U543 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U544 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U545 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U546 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U547 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U548 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U549 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U550 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U551 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U552 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U553 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U554 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U555 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U556 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U557 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U558 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U559 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U560 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U561 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U562 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U563 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U564 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U565 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U566 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U567 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U568 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U569 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U570 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U571 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U572 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U573 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U574 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U575 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U576 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U577 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U578 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U579 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U580 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U581 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U582 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U583 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U584 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U585 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U586 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U587 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U588 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U589 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U590 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U591 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U592 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U593 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U594 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U595 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U596 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U597 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U598 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U599 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U600 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U601 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U602 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U603 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U604 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U605 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U606 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U607 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U608 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U609 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U610 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U611 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U612 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U613 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U614 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U615 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U616 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U617 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U618 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U619 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U620 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U621 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U622 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U623 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U624 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U633 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U634 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U635 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U636 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U637 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U638 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U639 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U648 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U649 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U650 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U651 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U652 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U653 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U654 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U663 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U664 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U665 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U666 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U667 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U668 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U669 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U678 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U679 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U680 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U681 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U682 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U683 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U684 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U693 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U694 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U695 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U696 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U697 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U698 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U699 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U708 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U709 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U710 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U711 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U712 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U713 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U714 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U715 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U716 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U717 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U718 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U719 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U720 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U721 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U722 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U723 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U724 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U725 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U726 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U727 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U728 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U729 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U738 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U739 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U740 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U741 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U742 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U743 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U744 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U745 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U746 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U747 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U748 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U749 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U750 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U751 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U752 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U753 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U754 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U755 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U756 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U757 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U758 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U759 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U760 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U761 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U762 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U763 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U764 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U765 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U766 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U767 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U768 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U769 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U770 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U771 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U772 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U773 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U774 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U775 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U776 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U777 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U778 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U779 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U780 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U781 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U782 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U783 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U784 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U785 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U786 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U787 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U788 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U789 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U790 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U791 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U792 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U793 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U794 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U795 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U796 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U797 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U798 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U799 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U800 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U801 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U802 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U803 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U804 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U843 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U844 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U845 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U846 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U847 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U848 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U849 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U858 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U859 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U860 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U861 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U862 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U863 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U864 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U873 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U874 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U875 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U876 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U877 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U878 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U879 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U888 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U889 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U890 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U891 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U892 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U893 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U894 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U903 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U904 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U905 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U906 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U907 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U908 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U909 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U918 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U919 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U920 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U921 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U922 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U923 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U924 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U933 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U934 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U935 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U936 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U937 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U938 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U939 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U948 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U949 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U950 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U951 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U952 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U953 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U954 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U963 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U964 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U965 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U966 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U967 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U968 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U969 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U970 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U971 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U972 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U973 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U974 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U975 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U976 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U977 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U978 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U979 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U980 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U981 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U982 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U983 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U984 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U993 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U994 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U995 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U996 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U997 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U998 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U999 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1000 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1001 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1002 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1003 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1004 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1005 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1006 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1007 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1008 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1009 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1010 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1011 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1012 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1013 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1014 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1015 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1016 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1017 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1018 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1019 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1020 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1021 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1022 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1023 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1024 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1025 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1026 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1027 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1028 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1029 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1030 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1031 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1032 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1033 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1034 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1035 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1036 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1037 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1038 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1039 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1040 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1041 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1042 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1043 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1044 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1045 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1046 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1047 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1048 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1049 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1050 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1051 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1052 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1053 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1054 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1055 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1056 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1057 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1058 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1059 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1060 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1061 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1062 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1063 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1064 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1065 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1066 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1067 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1068 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1069 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1070 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1071 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1072 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1073 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1074 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1075 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1076 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1077 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1078 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1079 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1080 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1081 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1082 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1083 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1084 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1085 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1086 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1087 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1088 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1089 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1090 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1091 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1092 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1093 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1094 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1095 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1096 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1097 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1098 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1099 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1100 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1101 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1102 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1103 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1105 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1106 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1107 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1108 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1109 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1110 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1111 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1112 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1113 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1114 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1115 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1116 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1117 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1119 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1120 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1121 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1122 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1123 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1124 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1125 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1126 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1127 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1128 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1129 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1130 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1131 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1132 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1133 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1134 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1136 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1138 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1140 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1142 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1143 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1144 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1145 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1146 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1147 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1148 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1149 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1150 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1151 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1152 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1154 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1155 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1156 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1157 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1158 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1160 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1161 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1162 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1164 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1165 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1166 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1167 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1168 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1169 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1170 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1171 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1172 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1173 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1174 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1175 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1177 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1179 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1181 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1182 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1183 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1184 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1185 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1186 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1187 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1188 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1189 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1190 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1191 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1192 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1193 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1195 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1196 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1197 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1198 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1199 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1200 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1201 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1202 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1203 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1204 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1205 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1206 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1207 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1208 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1209 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1210 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1211 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1212 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1213 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1214 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1215 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1216 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1217 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1220 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1221 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1222 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1223 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1224 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1225 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1226 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1227 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1228 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1229 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1231 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1233 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1237 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1238 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1240 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1244 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1247 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1248 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1250 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1251 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1252 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1254 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1255 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1256 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1257 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1258 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1259 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1260 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1261 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1262 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1263 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1264 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1265 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1266 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1267 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1268 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1269 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1270 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1271 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1272 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1273 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1274 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1275 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1276 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1277 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1278 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1279 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1280 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1281 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1282 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1283 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1284 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1285 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1286 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1287 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1288 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1289 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1290 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1291 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1292 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1293 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1294 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1295 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1296 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1297 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1298 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1299 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1300 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1301 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1302 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1303 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1304 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1305 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1306 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1307 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1308 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1309 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1310 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1311 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1312 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1313 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +VX_dmem_controller_shared_memory_U1314 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1315 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1316 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1317 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1318 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1319 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1320 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1322 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1323 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1324 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1325 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1326 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1327 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1328 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1329 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1330 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1331 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1332 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1333 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1334 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1335 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1336 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1337 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1338 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1339 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1340 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1341 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1342 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1343 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1344 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1345 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1346 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1347 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1348 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1349 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1350 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1351 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1352 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1353 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1354 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1355 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1356 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1357 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1358 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1359 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1360 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1364 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1365 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1366 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1367 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1368 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1370 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1372 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1374 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1376 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1377 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1380 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1381 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1397 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1399 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1400 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1401 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1402 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1403 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1405 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1406 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1407 + NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U1408 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1409 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1410 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1419 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1420 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1421 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1422 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1423 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1424 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1425 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1434 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1435 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1436 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1437 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1438 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1439 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1440 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1449 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1450 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1451 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1452 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1453 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1454 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1455 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1539 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1540 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1541 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1542 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1543 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1544 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1545 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1659 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1660 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1661 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1662 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1663 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1664 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1665 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1674 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1675 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1676 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1677 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1678 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1680 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1682 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1683 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1684 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1685 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1686 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1687 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1689 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1690 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1691 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1692 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1693 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1695 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1696 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1697 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1698 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1699 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1700 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1703 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1705 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1707 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1708 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1709 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1710 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1712 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1713 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1714 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1715 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1716 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1718 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1719 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1720 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1721 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1722 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1724 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1725 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1726 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1727 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1728 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1729 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1730 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1731 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1732 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1733 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1734 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1735 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1736 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1737 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1738 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1739 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1740 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1741 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1742 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1743 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1744 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1745 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1746 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1747 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1748 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1750 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1751 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1752 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1753 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1754 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1755 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1757 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1758 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1759 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1760 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1761 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1762 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1763 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1764 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1765 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1766 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1767 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1769 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1770 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1771 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1772 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1773 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1774 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1775 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1776 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1777 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1778 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1779 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1780 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1781 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1782 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1783 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1784 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1785 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1786 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1787 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1788 + OAI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1789 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1790 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1791 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1792 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1793 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1794 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1795 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1796 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1797 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1798 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1799 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1800 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1801 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1802 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1803 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1804 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1805 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1806 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1807 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1808 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1809 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1810 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1811 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1812 + OAI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1813 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1814 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1815 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1816 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1817 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1818 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1819 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1820 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1821 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1822 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1823 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1824 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1825 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1826 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1827 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1828 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1829 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1830 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1831 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1832 + OAI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1833 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1834 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1843 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1844 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1845 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1846 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1847 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1848 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1849 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1850 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1851 + OAI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1852 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1853 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1854 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1856 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1857 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1858 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1859 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1860 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1861 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1862 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1863 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1864 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1865 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1866 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1867 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1868 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1869 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1870 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1871 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1872 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1873 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1874 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1875 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1876 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1877 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1878 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1879 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1880 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1881 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1882 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1884 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1885 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1886 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1887 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U1888 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1889 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1890 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1891 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1892 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1893 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1894 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1895 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1896 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1897 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1898 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1899 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1900 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1901 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1902 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1903 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1904 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1905 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1906 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1907 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1908 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1910 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1911 + NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1912 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1913 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1914 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1916 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1917 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1918 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1919 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1920 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1921 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1922 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1923 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1924 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1925 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1926 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1927 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1928 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1929 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1930 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1931 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1932 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1933 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1934 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1935 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1936 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1937 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U1938 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1939 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1940 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1941 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1942 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1943 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1944 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1945 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1946 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1947 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1948 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1949 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1950 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1951 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1952 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1953 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1954 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1955 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1956 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1957 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1958 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1959 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1960 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1961 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1962 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1963 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1964 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1965 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U1966 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1967 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1968 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1969 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1970 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1971 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1972 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1973 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1974 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1975 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U1976 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1977 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1978 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1980 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1981 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1982 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1983 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1984 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1986 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1987 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1988 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1990 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1991 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1992 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1993 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1994 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1995 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U1996 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U1997 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U1998 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U1999 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2000 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2001 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2003 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2004 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2005 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2007 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2008 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2009 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2010 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2011 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2012 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2013 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2014 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2015 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2016 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U2017 + OAI21_X0P5M_A12TUL_C35 + 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0.972000 +VX_dmem_controller_shared_memory_U2025 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2026 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2027 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2028 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2029 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2030 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2031 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2032 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2040 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2041 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2042 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2043 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2044 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2045 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2046 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2047 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U2048 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2049 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2050 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2051 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2052 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2053 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2054 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2062 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U2063 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2064 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2065 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2066 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2067 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2068 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2077 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2078 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2079 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2080 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2081 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2082 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2083 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2084 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2086 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2087 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2088 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2089 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2090 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U2091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2093 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2094 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2095 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2096 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2097 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2098 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2099 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2100 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2101 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U2102 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2103 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2104 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2105 + NOR4BB_X0P5M_A12TUL_C35 + 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+ 0.972000 +VX_dmem_controller_shared_memory_U2113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2116 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2117 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2118 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2121 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2122 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2123 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2126 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2127 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2130 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2131 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2132 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2133 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2135 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2136 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2137 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2141 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2142 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2143 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2144 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2147 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2149 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2150 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2151 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2152 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2153 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2154 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2155 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2156 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2157 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2158 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2159 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2160 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_U2161 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2162 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2163 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2164 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2165 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2167 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2168 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2169 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2170 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2171 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2172 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2173 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2174 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2175 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2176 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2177 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2179 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2180 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2181 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2182 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2184 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2185 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2186 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2187 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2189 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2190 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2191 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2194 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2195 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2196 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2200 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2203 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2207 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2210 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2213 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2214 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2215 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2216 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2217 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2218 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2220 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2221 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2222 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2232 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2235 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2253 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2254 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2255 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2257 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2258 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2259 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2261 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2264 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2266 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2267 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2268 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2271 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2273 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2274 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2275 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2276 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2279 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2280 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2282 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2283 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2284 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2286 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2287 + NAND2_X0P5B_A12TUL_C35 + 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0.648000 +VX_dmem_controller_shared_memory_U2309 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2310 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2313 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2314 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2317 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2318 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2320 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2321 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2322 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2323 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2324 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2325 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2326 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2327 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2328 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2329 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2330 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2331 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2332 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2333 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2334 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2335 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2336 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2337 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2338 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2339 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2341 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2342 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2343 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2344 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2345 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2346 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2347 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2348 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2349 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2351 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2352 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2353 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2354 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2355 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2357 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2359 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2360 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2361 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2362 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2363 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2364 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2365 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2366 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2368 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2369 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2370 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2371 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2372 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2374 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2376 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2377 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2378 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2379 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2380 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2381 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2382 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2384 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2385 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2386 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2388 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2389 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2391 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2392 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2393 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2394 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2395 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2397 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2399 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2400 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2401 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2402 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2403 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2405 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2406 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2407 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2408 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2409 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2410 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2411 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2412 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2413 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2414 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2415 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2416 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2417 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2418 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2419 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2420 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2421 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2422 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2423 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2424 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2426 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2428 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2430 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2431 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2432 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2433 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2434 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2435 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2436 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2437 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2438 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2439 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2440 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2441 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2442 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2443 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2444 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2445 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2446 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2447 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2449 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2450 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2451 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2452 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2453 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2454 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2455 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2456 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2457 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2458 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2459 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2460 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2463 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2464 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2466 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2467 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2468 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2469 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2471 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2472 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2473 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2474 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2475 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2476 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2477 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2478 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2479 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2480 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2481 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2482 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2483 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2484 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2485 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2486 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2487 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2488 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2489 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2490 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2491 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2492 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2493 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2494 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2495 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2497 + 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0.486000 +VX_dmem_controller_shared_memory_U2592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2593 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2595 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2596 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2597 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2598 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2600 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2601 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2602 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2603 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2604 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2605 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2606 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2607 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2608 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2610 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2611 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2612 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2613 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2614 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2616 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2617 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2618 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2619 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2621 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2622 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2623 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2624 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2625 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2626 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2627 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2628 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2629 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2630 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2631 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2632 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2634 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2636 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2637 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2638 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2639 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2640 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2641 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2642 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2643 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2644 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2645 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2647 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2648 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2649 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2650 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2651 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2652 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2653 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2654 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2655 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2656 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2657 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2658 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2659 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2660 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2661 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2662 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2663 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2664 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2665 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2666 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2667 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2670 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2671 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2672 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2674 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2675 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2676 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2677 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2678 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2679 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2680 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2681 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2682 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2683 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2684 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2685 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2686 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2687 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2688 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2689 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2690 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2691 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2692 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2693 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2694 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2695 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2696 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2697 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2698 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2700 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2701 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2702 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2703 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2704 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2705 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2706 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2707 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2708 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2709 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2710 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2711 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2712 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2713 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2714 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2715 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2716 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2717 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2718 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2719 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2720 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2721 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2722 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2723 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2724 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2725 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2726 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2728 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2729 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2730 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2731 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2732 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2733 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2734 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2735 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2736 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2737 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2738 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2739 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2740 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2741 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2742 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2743 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2744 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2745 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2746 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2747 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2748 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2749 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2750 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2751 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2752 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2753 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2754 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2755 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2756 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2757 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2758 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2759 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2760 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2761 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2762 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2763 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2764 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2765 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2766 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2767 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2769 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2770 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2771 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2772 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2773 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2774 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2775 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2777 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2778 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2779 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2780 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2782 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2783 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2785 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2786 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2787 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2788 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2789 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2790 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2791 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2793 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2794 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2818 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2819 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2820 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2821 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2822 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2823 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2824 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2825 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2826 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2827 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2828 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2829 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2830 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2831 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2840 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2841 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2842 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2843 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2845 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2846 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2847 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2848 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2849 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2850 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2851 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2852 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2853 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2855 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2856 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2857 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2859 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2860 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2861 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2862 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2864 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2865 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2866 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2867 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2868 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2871 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2872 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2873 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2874 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2875 + 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0.972000 +VX_dmem_controller_shared_memory_U2890 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2891 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2892 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2893 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2894 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2895 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2896 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2897 + 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0.486000 +VX_dmem_controller_shared_memory_U2941 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2942 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2943 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2944 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2945 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2946 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2947 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U2948 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2970 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2971 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2972 + OA22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_U2973 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2974 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2975 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2977 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2978 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2979 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2980 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2981 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2982 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2983 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2984 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2985 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2986 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2987 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2988 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2989 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2990 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2991 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2992 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2993 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U2994 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2995 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U2997 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2998 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U2999 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3001 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3002 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3003 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3004 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3005 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3006 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3007 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3008 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3009 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3010 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3011 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3012 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3013 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3014 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3015 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3016 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3017 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3018 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3019 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3020 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3021 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3022 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3023 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3024 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3025 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3026 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3027 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3028 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3029 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3030 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3031 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3032 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3033 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3034 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3035 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3036 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3037 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3038 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3039 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3040 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3041 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3042 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3043 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3045 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3046 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3047 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3048 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3049 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3050 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3051 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3052 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3053 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3054 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3055 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3056 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3057 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3058 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3061 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3062 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3063 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3064 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3065 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3066 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3067 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3068 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3069 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3070 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3071 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3072 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3073 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3074 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3075 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3076 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3077 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3078 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3079 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3080 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3081 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3082 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3083 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3084 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3085 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3086 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3087 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3088 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3089 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3090 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3093 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3094 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3095 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3096 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3097 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3098 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3099 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3100 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3103 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3106 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3107 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3108 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3110 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3111 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3112 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3114 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3116 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3118 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3120 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3121 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3122 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3124 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3125 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3126 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3129 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3130 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3132 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3133 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3134 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3137 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3138 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3139 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3143 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3148 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3149 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3150 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3151 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3153 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3155 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3156 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3157 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3158 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3159 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3160 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3161 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3162 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3164 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3165 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3166 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3167 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3168 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3170 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3172 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3173 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3174 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3175 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3178 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3179 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3180 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3182 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3183 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3186 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3189 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3190 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3191 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3193 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3194 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3195 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3198 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3202 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3203 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3204 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3205 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3206 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3207 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3208 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3209 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3210 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3211 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3212 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3213 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3214 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3215 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3217 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3218 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3220 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3222 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3223 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3224 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3225 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3226 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3227 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3228 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3230 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3231 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3232 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3233 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3234 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3235 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3236 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3237 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3238 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3239 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3240 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3242 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3244 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3247 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3248 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3249 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3251 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3252 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3253 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3254 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3257 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3258 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3259 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3262 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3263 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3266 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3267 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3270 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3272 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3273 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3274 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3275 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3277 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3278 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3279 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3280 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3282 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3283 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3284 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3285 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3286 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3288 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3289 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3292 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3295 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3296 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3297 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3299 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3300 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3301 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3303 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3304 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3307 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3308 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3309 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3310 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3312 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3313 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3314 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3316 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3318 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3319 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3320 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3322 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3323 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3324 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3325 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3327 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3328 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3330 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3331 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3333 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3334 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3335 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3336 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3337 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3339 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3341 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3342 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3343 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3344 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3345 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3346 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3347 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3348 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3349 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3350 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3351 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3352 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3353 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3354 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3355 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3357 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3358 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3359 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3360 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3361 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3362 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3363 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3364 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3365 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3366 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3368 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3369 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3370 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3371 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3372 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3373 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3374 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3375 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3376 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3377 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3378 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3379 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3380 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3381 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3382 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3383 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3384 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3385 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3387 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3389 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3390 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3391 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3394 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3395 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3396 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3397 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3398 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3399 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3400 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3401 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3402 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3403 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3404 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3405 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3406 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3407 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3409 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3411 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3412 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3415 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3417 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3418 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3419 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3420 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3421 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3422 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3423 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3424 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3425 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3426 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3427 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3428 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3429 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3430 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3431 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3432 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3433 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3434 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3435 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3436 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3437 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3438 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3439 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3440 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3441 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3442 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3443 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3444 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3445 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3446 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3447 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3448 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3449 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3450 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3451 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3452 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3453 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3454 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3455 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3457 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3460 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3462 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3463 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3464 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3466 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3467 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3468 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3469 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3471 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3472 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3473 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3474 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3475 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3476 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3477 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3478 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3479 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3480 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3481 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3482 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3483 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3484 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3485 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3486 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3487 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3488 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3489 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3490 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3491 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3492 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3493 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3494 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3495 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3496 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3497 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3498 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3499 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3500 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3501 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3503 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3504 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3505 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3506 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3508 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3509 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3511 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3512 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3513 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3514 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3515 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3516 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3517 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3518 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3519 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3520 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3521 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3522 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3523 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3524 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3525 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3526 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3528 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3529 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3530 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3532 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3534 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3535 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3536 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3537 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3540 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3541 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3542 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3544 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3545 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3546 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3547 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3549 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3550 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3551 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3552 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3553 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3554 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3555 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3556 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3557 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3558 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3559 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3560 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3561 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3562 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3563 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3564 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3565 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3566 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3567 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3568 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3569 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3570 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3571 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3572 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3573 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3574 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3575 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3576 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3577 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3578 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3579 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3580 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3588 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3589 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3590 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3591 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3592 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3593 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3594 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3595 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3596 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3597 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3599 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3600 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3601 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3602 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_U3604 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3605 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_U3606 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_U3607 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3608 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3609 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3610 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3611 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3612 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_U3613 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U6 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_0__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U6 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_1__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U7 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_2__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U6 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_3__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U8 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_4__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U7 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_5__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U5 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_6__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U5 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U8 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U9 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_U10 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_genblk2_7__vx_shared_memory_block_first_ram + rf2_128x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 14157.097656 + b, d +VX_dmem_controller_shared_memory_shm_write_reg + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_0__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_1__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_2__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__0_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__1_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__2_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__3_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__4_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__5_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__6_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__7_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__8_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__9_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__10_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__11_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__12_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__13_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__14_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__15_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__16_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__17_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__18_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__19_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__20_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__21_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__22_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__23_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__24_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__25_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__26_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__27_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__28_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__29_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__30_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_temp_out_data_reg_3__31_ + LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U3 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U4 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U5 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U6 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U7 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U8 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U9 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U10 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U11 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U12 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U13 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U14 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U15 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U16 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U17 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U18 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U19 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U20 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U21 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U22 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U23 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U24 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U25 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U26 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U27 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U28 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U29 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U30 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U31 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U32 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U33 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U34 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U35 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U36 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U37 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U38 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U39 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U40 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U41 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U42 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U43 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U44 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U45 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U46 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U47 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U48 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U49 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U50 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U51 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U52 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U53 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U54 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U55 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U56 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U57 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U58 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U59 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U60 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U61 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U62 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U63 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U64 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U65 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U66 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U67 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U68 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U69 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U70 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U71 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U72 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U73 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U74 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U75 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U76 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U77 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U78 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U79 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U80 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U81 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U82 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U83 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U84 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U85 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U86 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U87 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U88 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U89 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U90 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U91 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U92 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U93 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U94 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U95 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U96 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U97 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U98 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U99 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U100 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U101 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U102 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U103 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U104 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U105 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U106 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U107 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U108 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U109 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U110 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U111 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U112 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U113 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U114 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U115 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U116 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U117 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U118 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U119 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U120 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U121 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U122 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U123 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U124 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U125 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U126 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U127 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U128 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U129 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U130 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U131 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U132 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U133 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U134 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U135 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U136 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U137 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U138 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U139 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U140 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U141 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U142 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U143 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U144 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U145 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U146 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U147 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U148 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U149 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U150 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U151 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U152 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U153 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U154 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U155 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U156 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U157 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U158 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U159 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U160 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U161 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U162 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U163 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U164 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U165 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U166 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U167 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U168 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U169 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U170 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U171 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U172 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U173 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U174 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U175 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U176 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U177 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U178 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U179 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U180 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U181 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U182 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U183 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U184 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U185 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U186 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U187 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U188 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U189 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U190 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U191 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U192 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U193 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U194 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U195 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U196 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U197 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U198 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U199 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U200 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U201 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U202 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U203 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U204 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U205 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U206 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U207 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U208 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U209 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U210 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U211 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U212 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U213 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U214 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U215 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U216 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U217 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U218 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U219 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U220 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U221 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U222 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U223 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U224 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U225 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U226 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U227 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U228 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U229 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U231 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U232 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U233 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U234 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U235 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U236 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U237 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U238 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U239 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U240 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U241 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U242 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U243 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U244 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U245 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U246 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U247 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U248 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U249 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U250 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U251 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U252 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U253 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U254 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U255 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U256 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U257 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U258 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U259 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U260 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U261 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U262 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U263 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U264 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U265 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U266 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U267 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U268 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U269 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U270 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U271 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U272 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U273 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U274 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U275 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U276 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U277 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U278 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U279 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U280 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U281 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U282 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U283 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U284 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U285 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U286 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U287 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U288 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U289 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U290 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U291 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U292 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U293 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U294 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U295 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U296 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U297 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U298 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U299 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U300 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U301 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U302 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U303 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U304 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U305 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U306 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U307 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U308 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U309 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U310 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U311 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U312 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U313 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U314 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U315 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U316 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U317 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U318 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U319 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U320 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U321 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U322 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U323 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U324 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U325 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U326 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U327 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U328 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U329 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U330 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U331 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U332 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U333 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U334 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U335 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U336 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U337 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U338 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U339 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U340 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U341 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U342 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U343 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U344 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U345 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U346 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U347 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U348 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U349 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U350 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U351 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U352 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U353 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U354 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U355 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U356 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U357 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U358 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U359 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U360 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U361 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U362 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U363 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U364 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U365 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U366 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U367 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U368 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U369 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U370 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U371 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U372 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U373 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U374 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U375 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U376 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U377 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U378 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U379 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U380 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U381 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U382 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U383 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U384 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U385 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U386 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U387 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U388 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U389 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U390 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U391 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U392 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U393 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U394 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U395 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U396 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U397 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U398 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U399 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U400 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U401 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U402 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U403 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U404 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U405 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U406 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U407 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U408 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U409 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U410 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U411 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U412 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U413 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U414 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U415 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U416 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U417 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U418 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U419 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U420 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U421 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U422 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U423 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U424 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U425 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U426 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U427 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U428 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U429 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U430 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U431 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U432 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U433 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U434 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U435 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U436 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U437 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U438 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U439 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U440 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U441 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U442 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U443 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U444 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U445 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U446 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U447 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U448 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U449 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U450 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U451 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U452 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U453 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U454 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U455 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U456 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U457 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U458 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U459 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U460 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U461 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U462 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U463 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U464 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U465 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U466 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U467 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U468 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U469 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U470 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U471 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U472 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U473 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U474 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U475 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U476 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U477 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U478 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U479 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U480 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U481 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U482 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U483 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U484 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U485 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U486 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U487 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U488 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U489 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U490 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U491 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U492 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U493 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U494 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U495 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U496 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U497 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U498 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U499 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U500 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U501 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U502 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U503 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U504 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U505 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U506 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U507 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U508 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U509 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U510 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U511 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U512 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U513 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U514 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U515 + OAI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U516 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U517 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U518 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U519 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U520 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U521 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U522 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U523 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U524 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U525 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U526 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U527 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U528 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U529 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U530 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U531 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U532 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U533 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U534 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U535 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U536 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U537 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U538 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U539 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U540 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U541 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U542 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U543 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U544 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U545 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U546 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U547 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U548 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U549 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U550 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U551 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U552 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U553 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U554 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U555 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U556 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U557 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U558 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U559 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U560 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U561 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U562 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U563 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U564 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U565 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U566 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U567 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U568 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U569 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U570 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U571 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U572 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U573 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U574 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U575 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U576 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U577 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U578 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U579 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U580 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U581 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U583 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U584 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U585 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U586 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U587 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U588 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U589 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U590 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U591 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U592 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U593 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U594 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U595 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U596 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U597 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U598 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U599 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U600 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U601 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U602 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U603 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U604 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U605 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U606 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U607 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U608 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U609 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U610 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U611 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U612 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U613 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U614 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U615 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U616 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U617 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U618 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U619 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U620 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U621 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U622 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U623 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U624 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U625 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U626 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U627 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U628 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U629 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U630 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U631 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U632 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U633 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U634 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U636 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U637 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U638 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U639 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U640 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U641 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U642 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U643 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U644 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U645 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U646 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U647 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U648 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U649 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U650 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U651 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U652 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U653 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U654 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U655 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U656 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U657 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U658 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U659 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U660 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U661 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U662 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U663 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U664 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U665 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U666 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U667 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U668 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U669 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U670 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U671 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U672 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U673 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U674 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U675 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U676 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U677 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U678 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U679 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U680 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U681 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U682 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U683 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U684 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U685 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U686 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U687 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U688 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U689 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U690 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U691 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U692 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U693 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U694 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U695 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U696 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U697 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U698 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U699 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U700 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U701 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U702 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U703 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U704 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U705 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U706 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U707 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U708 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U709 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U710 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U711 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U712 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U713 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U714 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U715 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U716 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U717 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U718 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U719 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U720 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U721 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U722 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U723 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U724 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U725 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U726 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U727 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U728 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U729 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U730 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U731 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U732 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U733 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U734 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U735 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U736 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U737 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U738 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U739 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U740 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U741 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U742 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U743 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U744 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U745 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U746 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U747 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U748 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U749 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U750 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U751 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U752 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U753 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U754 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U755 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U756 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U757 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U758 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U759 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U760 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U761 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U762 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U763 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U764 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U765 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U766 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U767 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U769 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U770 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U771 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U772 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U773 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U774 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U775 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U776 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U777 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U778 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U779 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U780 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U781 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U782 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U783 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U784 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U785 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U786 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U787 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U788 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U789 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U790 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U791 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U792 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U793 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U794 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U795 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U796 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U797 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U798 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U799 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U800 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U801 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U802 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U803 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U804 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U805 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U806 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U807 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U808 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U809 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U810 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U811 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U812 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U813 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U814 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U815 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U816 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U817 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U818 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U819 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U820 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U821 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U822 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U823 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U824 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U825 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U826 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U827 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U828 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U829 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U830 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U831 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U832 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U833 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U834 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U835 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U836 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U837 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U838 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U839 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U840 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U841 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U842 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U843 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U844 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U845 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U846 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U847 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U848 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U849 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U850 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U851 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U852 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U853 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U854 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U855 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U856 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U857 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U858 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U859 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U860 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U861 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U862 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U863 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U864 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U865 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U866 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U867 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U868 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U869 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U870 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U871 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U872 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U873 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U874 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U875 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U876 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U877 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U878 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U879 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U880 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U881 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U882 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U883 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U884 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U885 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U886 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U887 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U888 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U889 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U890 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U891 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U892 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U893 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U894 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U895 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U896 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U897 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U898 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U899 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U900 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U901 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U902 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U903 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U904 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U905 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U906 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U907 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U926 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U927 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U928 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U929 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U930 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U931 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U950 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U951 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U952 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U953 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U954 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U955 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U956 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U957 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U958 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U959 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U960 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U961 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U962 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U963 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U964 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U965 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U966 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U967 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U968 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U969 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U970 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U971 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U972 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U973 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U974 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U975 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U976 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U977 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U978 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U979 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U980 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U981 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U982 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U983 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U984 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U985 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U986 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U987 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U988 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U989 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U990 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U991 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U992 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U993 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U994 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U995 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U996 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U997 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U998 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U999 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1000 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1001 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1002 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1003 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1004 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1005 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1006 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1007 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1008 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1009 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1010 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1011 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1012 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1013 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1014 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1015 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1016 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1017 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1018 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1019 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1020 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1021 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1022 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1023 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1024 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1025 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1026 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1027 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1028 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1029 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1030 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1031 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1032 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1033 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1034 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1035 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1036 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1037 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1038 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1039 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1040 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1041 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1042 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1043 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1044 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1045 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1046 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1047 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1048 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1049 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1050 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1051 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1052 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1053 + NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1054 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1055 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1056 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1057 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1058 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1059 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1060 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1061 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1062 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1063 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1064 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1065 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1066 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1067 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1068 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1069 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1070 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1071 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1072 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1073 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1074 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1075 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1076 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1077 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1078 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1079 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1080 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1081 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1082 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1083 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1084 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1085 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1086 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1087 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1088 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1089 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1090 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1091 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1092 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1093 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1094 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1095 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1096 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1097 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1098 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1099 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1100 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1101 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1102 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1103 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1104 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1105 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1106 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1107 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1108 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1109 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1110 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1111 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1112 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1113 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1114 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1115 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1116 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1117 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1118 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1119 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1120 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1121 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1122 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1123 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1124 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1125 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1126 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1127 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1128 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1129 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1130 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1131 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1132 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1133 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1134 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1135 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1136 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1137 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1138 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1139 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1140 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1141 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1142 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1143 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1144 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1145 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1146 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1147 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1148 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1149 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1150 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1151 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1152 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1153 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1154 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1155 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1156 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1157 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1158 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1159 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1160 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1161 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1162 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1163 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1164 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1165 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1166 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1167 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1168 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1169 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1170 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1171 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1172 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1173 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1174 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1175 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1176 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1177 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1178 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1179 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1180 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1181 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1182 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1183 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1184 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1185 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1186 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1187 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1188 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1189 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1190 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1191 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1192 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1193 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1194 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1195 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1196 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1197 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1198 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1199 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1200 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1201 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1202 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1203 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1204 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1205 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1206 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1207 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1208 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1209 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1210 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1211 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1212 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1213 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1214 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1215 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1216 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1217 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1218 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1219 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1220 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1221 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1222 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1223 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1224 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1225 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1226 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1227 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1228 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1229 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1230 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1231 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1232 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1233 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1234 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1235 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1236 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1237 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1238 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1239 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1240 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1241 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1242 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1243 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1244 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1245 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1246 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1247 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1248 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1249 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1250 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1251 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1252 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1253 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1254 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1255 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1256 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1257 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1258 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1259 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1260 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1261 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1262 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1263 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1264 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1265 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1266 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1267 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1268 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1269 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1270 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1271 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1272 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1273 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1274 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1275 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1276 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1277 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1278 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1279 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1280 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1281 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1282 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1283 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1286 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1290 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1291 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1292 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1293 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1294 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1296 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1297 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1298 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1299 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1300 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1301 + OAI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1302 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1304 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1305 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1306 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1307 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_U1308 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U4 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_0__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U4 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_1__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U4 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_2__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U4 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_3__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U4 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_4__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U4 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_5__valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U2 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U4 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_6__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U1 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U2 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk1_7__valids_counter_U5 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U3 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U4 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U7 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_0__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U3 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U4 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U5 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_1__vx_priority_encoder_U8 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U3 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U4 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U7 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_2__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U3 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U5 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U7 + AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_3__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U3 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U5 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U7 + AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_4__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U3 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U4 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U7 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_5__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U3 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U4 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U7 + AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_6__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U3 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U4 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U7 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_genblk2_7__vx_priority_encoder_U8 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_left_requests_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U2 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U3 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U4 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U6 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U7 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U8 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U9 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U10 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U11 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U12 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U13 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U14 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U15 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U16 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U17 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U18 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U19 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U20 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U21 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U22 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U23 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U24 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U25 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U26 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U27 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U28 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U29 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U30 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U31 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U32 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U33 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U34 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U35 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U36 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U37 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U38 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U39 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U40 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U41 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U42 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U44 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U45 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U46 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U47 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U49 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U50 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U51 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U52 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U53 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U54 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U55 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U56 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U57 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U58 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U59 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U60 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +VX_dmem_controller_shared_memory_vx_priority_encoder_sm_vx_bank_valid_U61 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U3 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U4 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U5 NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U6 NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U7 NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U8 NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U9 NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U10 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U11 NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U12 NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U13 NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U14 NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U15 INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U16 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U17 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U18 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U19 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U20 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U21 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +schedule_U22 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U23 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U24 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U25 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U26 NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U27 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U28 NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U29 NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U30 NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U31 NAND3XXB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U32 NAND3XXB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U33 NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U34 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U35 NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U36 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U37 NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U38 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U39 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U40 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U41 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U42 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U43 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U44 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U45 NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U46 NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U47 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U48 NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U49 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U50 NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +schedule_U51 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U52 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U53 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U54 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U55 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U56 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U57 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U58 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U59 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U60 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U61 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U62 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U63 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U64 NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U65 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U66 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U67 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U68 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U69 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U70 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U71 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U72 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U73 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U74 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U75 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U76 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U77 AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U78 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U79 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U80 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U81 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U82 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U83 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U84 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U85 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U86 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U87 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U88 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U89 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U90 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U91 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U92 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U93 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U94 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U95 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U96 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U97 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U98 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U99 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U100 NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U101 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U102 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U103 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U104 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U105 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U106 NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U107 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U108 NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U109 AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U110 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U111 OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U112 OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U113 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U114 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U115 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U116 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U117 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U118 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U119 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U120 AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U121 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U122 OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U123 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U124 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U125 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U126 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U127 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U128 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U129 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U130 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U131 NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U132 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U133 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U134 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U135 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U136 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U137 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U138 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U139 NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +schedule_U140 NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +schedule_U141 NAND3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +schedule_U142 NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U143 AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +schedule_U144 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U145 NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U146 OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U147 OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U148 NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U149 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U150 OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U151 AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U152 OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U153 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U154 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U155 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U156 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U157 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U158 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U159 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U160 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U161 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U162 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U163 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U164 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U165 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U166 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U167 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U168 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U169 BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U170 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U171 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U172 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U173 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U174 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U175 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U176 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U177 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U178 NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U179 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U180 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U181 NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +schedule_U182 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U183 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U184 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U185 AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U186 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U187 AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U188 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U189 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U190 OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U191 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U192 AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U193 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +schedule_U194 NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U195 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U196 NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +schedule_U197 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_U198 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +schedule_rename_table_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +schedule_rename_table_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_U1 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_csr_wrapper_U3 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_csr_wrapper_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U5 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_csr_wrapper_U6 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U7 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U8 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_csr_wrapper_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U10 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_csr_wrapper_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U12 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_csr_wrapper_U13 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U2 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U3 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_U4 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U5 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U6 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U7 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U8 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U9 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U10 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U11 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U12 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U13 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U14 + NOR3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U15 + NAND3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U16 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U17 + OR4_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_U18 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U19 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U20 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U21 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U22 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U23 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U24 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U25 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U26 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U27 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U28 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U29 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U30 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U31 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U32 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U33 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U34 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U35 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U36 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U37 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U38 + OR2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U39 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U40 + NOR3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U41 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U42 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U43 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U44 + NOR3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_U45 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U46 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U47 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U48 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U49 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U50 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U51 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U52 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U53 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U54 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U55 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U56 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U57 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U58 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U59 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U60 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U61 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U62 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U63 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U64 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U65 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_back_end_VX_execUnit_U66 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U67 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U68 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U69 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U70 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U71 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U72 + NAND4BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_U73 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U74 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U75 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U76 + NOR3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U77 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U78 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U79 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U80 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U81 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U82 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U83 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U84 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U85 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U86 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U87 + OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_back_end_VX_execUnit_U88 + AOI31_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_U89 + OAI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_U90 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U91 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U92 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U93 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U94 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U95 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U96 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U97 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U98 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U99 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U100 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U101 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U102 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U103 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U104 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U105 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U106 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U107 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U108 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U109 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U110 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U111 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U112 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U113 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U114 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U115 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U116 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U117 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U118 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U119 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U120 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U121 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U122 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U123 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U124 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U125 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U126 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U127 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U128 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U129 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U130 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U131 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U132 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U133 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U134 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U135 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U136 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U137 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U138 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U139 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U140 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_U141 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U142 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U143 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U144 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U145 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U146 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U147 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U148 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U149 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U150 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U151 + XOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_U152 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U154 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U155 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U156 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U157 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U158 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U159 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U160 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U161 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U162 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U163 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U164 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U165 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U166 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U167 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U168 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U169 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U170 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U171 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U172 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U173 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U174 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U175 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U176 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U177 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U178 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U179 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U180 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U181 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U182 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U183 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U184 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U185 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U186 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U187 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U188 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U189 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U190 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U191 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U192 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_U193 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U194 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_U195 + NOR3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U196 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U197 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U198 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U199 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U200 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U201 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_U202 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U203 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U205 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U206 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U207 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U208 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_U209 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U210 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U211 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U212 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U213 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U214 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U215 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U216 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U217 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_U218 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U219 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_U220 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U221 + NAND4BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_U222 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U223 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U224 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U225 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U226 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U227 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U228 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U229 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U230 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U231 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U232 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U233 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U234 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U235 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U236 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U237 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U238 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U239 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U240 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U241 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U242 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U243 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_U244 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U245 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U246 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U247 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U248 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U249 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U250 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U251 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U252 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U253 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U254 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U255 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U256 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U257 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U258 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U259 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U260 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U261 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U262 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U263 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U264 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U265 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_U266 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_U267 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_U268 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_U269 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_U270 + XOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_U271 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U272 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U273 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U274 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U275 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U276 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U277 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U278 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U279 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_U280 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_add_x_3_U3 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U6 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_3_U33 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_add_x_4_U3 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U5 + ADDF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U6 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U7 + ADDF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U14 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U18 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U19 + ADDF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_add_x_4_U31 + ADDF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_add_x_4_U32 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_choose_alu_result_U3 + OA21A1OI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_choose_alu_result_U4 + AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_choose_alu_result_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_choose_alu_result_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_choose_alu_result_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U3 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U4 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U6 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U7 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U8 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U9 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U10 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12 + OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U14 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U16 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U18 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U19 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U20 + OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U21 + OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U22 + OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U23 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U24 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U25 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U26 + NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U27 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U28 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U29 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U30 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+ 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5231 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5232 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5233 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5234 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5235 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5236 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5237 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5238 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5239 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5240 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5241 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5242 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5243 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5244 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5245 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5246 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5247 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5249 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5250 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5251 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5252 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5253 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5254 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5255 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5256 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5257 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5258 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5259 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5260 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5261 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5262 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5263 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5264 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5265 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5266 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5267 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5268 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5269 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5270 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5271 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5272 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5273 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5274 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5275 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5276 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5277 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5278 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5279 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5280 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5281 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5282 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5283 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5284 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5285 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5286 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5287 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5288 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5289 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5290 + MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5291 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5292 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U5293 + INV_X0P6M_A12TUL_C35 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11372 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11373 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11374 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11375 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11376 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11377 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11378 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11379 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11380 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11381 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11382 + XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11383 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11384 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11385 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11386 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11387 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11388 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11389 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11390 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11391 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11392 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11393 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11394 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11395 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11396 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11397 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11398 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11399 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11400 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11401 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11402 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11403 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11405 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11406 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11407 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11408 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11409 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11410 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11411 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11412 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11413 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11414 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11415 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11416 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11417 + CGENI_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11418 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11419 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11420 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11421 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11422 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11423 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11424 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11425 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11426 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11427 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11428 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11429 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11430 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11431 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11432 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11433 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11434 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11435 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11436 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11437 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11438 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11439 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11440 + INV_X1P2M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11448 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11449 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11450 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11451 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11452 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11453 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11454 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11676 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11677 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11678 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11679 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11680 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11681 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U11682 + NAND2B_X0P7M_A12TUL_C35 + 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+ NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12271 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12272 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12273 + OAI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12274 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12275 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12276 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12277 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0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12769 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12770 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12771 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12772 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12773 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12774 + NAND4_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12775 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12824 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12825 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12826 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12827 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12828 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12829 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12830 + 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+ OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12838 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12839 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12840 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12841 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12842 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12843 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12844 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12845 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12846 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12847 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12848 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12849 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12850 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12851 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12852 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12853 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12854 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12855 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12856 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12857 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12858 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12859 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12860 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12861 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12862 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12863 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12864 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12865 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12866 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12867 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12868 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12869 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12870 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12871 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12872 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12873 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12874 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12875 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12876 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12877 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12878 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12879 + OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12880 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12881 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12882 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12883 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12884 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12885 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12886 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12887 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12888 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12889 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12890 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12891 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12892 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12893 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12894 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12895 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12896 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12897 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12898 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12899 + INV_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12900 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12901 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12902 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12903 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12904 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12905 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12906 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12907 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12908 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12910 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12911 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12912 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12913 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12914 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12915 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12916 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12917 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12918 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12919 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12920 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12921 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12922 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12923 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12924 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12925 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12926 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12927 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12928 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12929 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12930 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12931 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12932 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12933 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12941 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12942 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12943 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12944 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12945 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12946 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U12947 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13758 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13759 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13760 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13761 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13762 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13763 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13764 + 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+ NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13772 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13773 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13774 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13775 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13776 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13777 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13799 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13800 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13801 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13802 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13803 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13804 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13805 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13806 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13807 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13808 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13809 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13810 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U13811 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15712 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15713 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15714 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15715 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15716 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15717 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15718 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15719 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15720 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15721 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15722 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15723 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15724 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U15725 + 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+ NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17142 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17143 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17144 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17145 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17146 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17147 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17442 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17443 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17444 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17445 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17446 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17447 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17448 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17449 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17450 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17451 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17452 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17453 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17454 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17462 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17463 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17464 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17465 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17466 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17467 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17468 + XNOR2_X0P5M_A12TUL_C35 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17489 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17490 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17491 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17492 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17493 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17494 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U17495 + OR2_X2M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31371 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31372 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31373 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31374 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31375 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31376 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31377 + INV_X7P5M_A12TUL_C35 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+ OAI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31406 + NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31407 + OAI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31408 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31409 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31410 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31411 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31426 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31427 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31428 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31429 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31430 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31431 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31432 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31433 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31434 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31435 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31436 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31437 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31438 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31439 + AOI21_X8M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31447 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31448 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31449 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31450 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31451 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31452 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31453 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31454 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31455 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31456 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31457 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31458 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31459 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31460 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31461 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31462 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31463 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31464 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31465 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31466 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31467 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31468 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31469 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31470 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31471 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31472 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31473 + AOI2XB1_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31474 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31475 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31476 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31477 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31478 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31479 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31480 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31481 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31482 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31483 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31484 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31485 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31486 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31487 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31488 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31489 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31490 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31491 + OAI22BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31492 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31493 + OAI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31494 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31495 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31496 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31497 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31498 + OAI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31499 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31500 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31501 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31502 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31503 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31504 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31505 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31506 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31507 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31508 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31509 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31510 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31511 + NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31512 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31513 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31514 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31515 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31516 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31517 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31518 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31519 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31520 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31521 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31522 + BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31523 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31524 + AOI22BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31525 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31526 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31527 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31528 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31529 + NAND2_X1A_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31537 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31538 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31539 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31540 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31541 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31542 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31543 + AOI21_X6M_A12TUL_C35 + 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4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31795 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31796 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31797 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31798 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31799 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31800 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31801 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31802 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31803 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31804 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31805 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31806 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31807 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31808 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31809 + NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31810 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31811 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31812 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31813 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31814 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31815 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31816 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31817 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31818 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31819 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31820 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31821 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31822 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31823 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31824 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31825 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31826 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31827 + NOR3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31828 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31829 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31830 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31831 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31832 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31833 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31834 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31835 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31836 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31837 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31838 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31839 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31840 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31841 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31842 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31843 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+ INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31858 + OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31859 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31860 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31861 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31862 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31863 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 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+vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31885 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31886 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31887 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31888 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31889 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31890 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31891 + NOR3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 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3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31899 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31900 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31901 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31902 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31903 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31904 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31905 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31906 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31907 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31908 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31909 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31910 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31911 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31912 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31913 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31914 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31915 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31916 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31917 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31918 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31919 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31920 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31921 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31922 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31923 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31924 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31925 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31926 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31927 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31928 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31929 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31930 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31931 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31932 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31933 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31934 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31935 + OAI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31936 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31937 + NAND3XXB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31938 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31939 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31940 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31941 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31942 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31943 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31944 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31945 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31946 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31947 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31948 + OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31949 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31950 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31951 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31952 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31953 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31954 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31955 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31956 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31957 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31958 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31959 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31960 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U31961 + MXIT2_X4M_A12TUL_C35 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32247 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32248 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32249 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32250 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32251 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32252 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U32253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33616 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33617 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33618 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33619 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33620 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33621 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33622 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33623 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33624 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33625 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33626 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33627 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33628 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33629 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33630 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33631 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33632 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33633 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33634 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33635 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33636 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33658 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33659 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33660 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33661 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33662 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33663 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33664 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33665 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33666 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33667 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33668 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33669 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33670 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U33671 + 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+ 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34530 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34531 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34535 + INV_X0P6B_A12TUL_C35 + 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+ AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34555 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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+ 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34570 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34571 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34572 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34573 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34574 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34575 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34576 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34687 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34688 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34689 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34690 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34691 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34692 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34693 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34694 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34695 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34696 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34697 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34698 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34699 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34700 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34701 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34702 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34703 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34704 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34705 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34706 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34707 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34708 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34709 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34710 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34711 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34712 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34713 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34714 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34729 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34730 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34731 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34732 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34733 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34734 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34735 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34736 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34737 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34738 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34739 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34740 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34741 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34742 + 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+vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34749 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34750 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34751 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34752 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34753 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34754 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34755 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34854 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34855 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34856 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34857 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34858 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34859 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34860 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34861 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34862 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34863 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34864 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34865 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34866 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34867 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34868 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34869 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34870 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34871 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34872 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34873 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34874 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34875 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34876 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34877 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34878 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34879 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34880 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34909 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34910 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34911 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34912 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34913 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34914 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U34915 + INV_X0P6B_A12TUL_C35 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35899 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35900 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35901 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35902 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35903 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35904 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U35905 + ADDF_X1M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36149 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36150 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36151 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36152 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36153 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36154 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36155 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36156 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36157 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36158 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36159 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36160 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36161 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36169 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36170 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36171 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36172 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36173 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36174 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36175 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36176 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36177 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36178 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36179 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36181 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36182 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36183 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36184 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36185 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36186 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36187 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36188 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36196 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36197 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36198 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36199 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36200 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36202 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36203 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36204 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36205 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36206 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36207 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36208 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36209 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36210 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36211 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36212 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36213 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36214 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36215 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36223 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36224 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36225 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36226 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36227 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36228 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36229 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36230 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36231 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36232 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36233 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36234 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36235 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36237 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36238 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36239 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36240 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36241 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36242 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36264 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36265 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36266 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36267 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36269 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36277 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36278 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36279 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36280 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36281 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36282 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36283 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36284 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36286 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36287 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36288 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36289 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36290 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36291 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36292 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36293 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36294 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36295 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36296 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36304 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36305 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36306 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36307 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36308 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36309 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36310 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36311 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36312 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36313 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36314 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36315 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36316 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U36317 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37099 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37100 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37102 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37105 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37106 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37107 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37108 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37109 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37110 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37133 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37134 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37135 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37136 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37137 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37138 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37139 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37894 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37895 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37896 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37897 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37898 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37899 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37900 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37901 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37902 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37903 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37904 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37905 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37906 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37907 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37908 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37909 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37910 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37911 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37912 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37913 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37921 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37922 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37923 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37924 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37925 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37926 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37927 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37928 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37929 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37930 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37931 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37932 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37933 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37941 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37942 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37943 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37944 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37945 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37946 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37947 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37948 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37949 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37950 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37951 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37952 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37953 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37954 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37955 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37956 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37957 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37958 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37959 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37960 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37968 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37969 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37970 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37971 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37972 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37973 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37974 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37975 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37976 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37977 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37978 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37979 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37980 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37981 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37982 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37983 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37984 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37985 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37986 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U37987 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38002 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38003 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38004 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38005 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38006 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38007 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38022 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38023 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38024 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38025 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38026 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38027 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38035 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38036 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38037 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38038 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38039 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_0__vx_alu_U38040 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U3 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5583 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5584 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5585 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5586 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5587 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5588 + AOI22_X1P4M_A12TUL_C35 + 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+ OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5617 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5618 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5619 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5620 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5621 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U5622 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6900 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6901 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6902 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6903 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6904 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6905 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U6906 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9701 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9702 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9703 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9704 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9705 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9706 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9707 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9722 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9723 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9724 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9725 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9726 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9727 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U9728 + NOR2_X1M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11041 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11042 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11043 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11044 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11045 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11046 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11047 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11048 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11049 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11050 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11051 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11052 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11053 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11054 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11055 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11056 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11057 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11058 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11059 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11060 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11061 + 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1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11089 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11090 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11091 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11092 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11093 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11094 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11095 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11096 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11097 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11098 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11099 + OA1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11100 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11101 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11102 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11103 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11104 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11105 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11106 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11107 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11108 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11109 + 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NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11117 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11118 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11119 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11120 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11121 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11122 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11123 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11172 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11173 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11174 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11175 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11176 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11177 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11178 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11179 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11180 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11181 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11182 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11183 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11184 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U11185 + NOR2_X6A_A12TUL_C35 + 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+ NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12192 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12193 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12194 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12195 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12196 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12197 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12267 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12268 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12269 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12270 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12271 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12272 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12273 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12274 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12275 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12276 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12277 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12278 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12279 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12280 + 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INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12308 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12309 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12310 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12311 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12312 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12313 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12321 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12322 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12323 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12324 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12325 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12326 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12327 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12328 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12329 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12330 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12331 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12332 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12333 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12772 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12773 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12774 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12775 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12776 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12777 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12778 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12779 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12780 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12781 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12782 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12783 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12784 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12785 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12786 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12787 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12788 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12789 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12790 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12791 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12799 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12800 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12801 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12802 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12803 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12804 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12805 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12806 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12807 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12808 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12809 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12810 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12811 + BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12812 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12813 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12814 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12815 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12816 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12817 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12818 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12826 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12827 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12828 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12829 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12830 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12831 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U12832 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13501 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13502 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13503 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13504 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13505 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13506 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13507 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13508 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13509 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13510 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13511 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13512 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13513 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13514 + 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+ OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13522 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13523 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13524 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13525 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13526 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13527 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13536 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13537 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13538 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13539 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13540 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13541 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13542 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13543 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13544 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13545 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13546 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13547 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13548 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13549 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13550 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13551 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13552 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13553 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13554 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13555 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13556 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13557 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13558 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13559 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13560 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13561 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13562 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13576 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13577 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13578 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13579 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13580 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13581 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13582 + NOR2_X2M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13610 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13611 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13612 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13613 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13614 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13615 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13616 + 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MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13624 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13625 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13626 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13627 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13628 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13629 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13637 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13638 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13639 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13640 + BUF_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13641 + BUF_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13642 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13643 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13644 + NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13645 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13646 + NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13647 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13648 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13649 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13650 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13828 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13829 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13830 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13831 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13832 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13833 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13834 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13835 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13836 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13837 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13838 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13839 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13840 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13841 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13842 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13843 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13844 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13845 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13846 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13847 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13848 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13849 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13850 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13851 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13852 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13853 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13854 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13855 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13856 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13857 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13858 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13859 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13860 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13861 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13862 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13863 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13864 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13865 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13866 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13867 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13868 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13869 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13870 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13871 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13872 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13873 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13874 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13875 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13876 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13877 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13878 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13879 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13880 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13881 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13882 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13883 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13884 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13885 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13886 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13887 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13888 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13889 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13890 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13891 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13892 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13893 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13894 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13895 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13896 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13897 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13898 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13899 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13900 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13901 + OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13902 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13903 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13904 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13905 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13906 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13907 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13908 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13909 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13910 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13939 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13940 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13941 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13942 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13943 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13944 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13945 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13946 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13947 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13948 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13949 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13950 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13951 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13952 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13953 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13954 + AOI22BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13955 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13956 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13957 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13958 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13959 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13960 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13961 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13962 + AOI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13963 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13964 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13965 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13966 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13967 + OA1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13968 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13969 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13970 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13971 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13972 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13973 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13974 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13975 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13976 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13977 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13978 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U13979 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19774 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19775 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19776 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19777 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19778 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19779 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U19780 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21886 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21887 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21888 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21889 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21890 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21891 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21892 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21893 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21894 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21895 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21896 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21897 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21898 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21899 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21900 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21901 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21902 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21903 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21904 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21905 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21906 + 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+ AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21914 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21915 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21916 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21917 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21918 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21919 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21927 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21928 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21929 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21930 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21931 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21932 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21933 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21934 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21935 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21936 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21937 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21938 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21939 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U21940 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28942 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28943 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28944 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28945 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28946 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28947 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28948 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28962 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28963 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28964 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28965 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28966 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28967 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28968 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28969 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28970 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28971 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28972 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28973 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28974 + AO21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28975 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28976 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28977 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28978 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28979 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28980 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28981 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28982 + NAND2_X6M_A12TUL_C35 + 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XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28990 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28991 + AO21A1AI2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28992 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28993 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28994 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U28995 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+ OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31181 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31182 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31183 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31184 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31185 + OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31186 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31187 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31188 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31189 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31190 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31191 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31192 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31193 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31194 + 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MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31418 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31419 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31420 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31421 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31422 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31423 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31424 + 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+ NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31432 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31433 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31434 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31435 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31436 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31437 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31438 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31473 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31474 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31475 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31476 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31477 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31478 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31479 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31487 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31488 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31489 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31490 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31491 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31492 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31493 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31494 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31495 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31496 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31497 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31498 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31499 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31500 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31501 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31502 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31503 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31504 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31505 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31506 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31507 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31508 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31509 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31510 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31511 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31512 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31513 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31514 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31515 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31516 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31517 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31518 + OAI21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31519 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31520 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31521 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31522 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31523 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31524 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31525 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31526 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31527 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31528 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31697 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31698 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31699 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31700 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31701 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31702 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31703 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31704 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31705 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31706 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31707 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31708 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31709 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31710 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31711 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31712 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31713 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31714 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31715 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31716 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31717 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31718 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31719 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31720 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31721 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31722 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31723 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31724 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31725 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31726 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31727 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31728 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31729 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31730 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31731 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31732 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31733 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31734 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31735 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31736 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31737 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 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+vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31745 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31746 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31747 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31748 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31749 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31750 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31751 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31752 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31753 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31754 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31755 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31756 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31757 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31758 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31759 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31760 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31761 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31762 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31763 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31764 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31765 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31766 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31767 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31768 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31769 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31770 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31771 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31772 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31773 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31774 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31775 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31776 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31777 + NOR2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31778 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U31779 + OAI21_X4M_A12TUL_C35 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33032 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33033 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33034 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33035 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33036 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33037 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33038 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33039 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33040 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33041 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33042 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33043 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33044 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33045 + XNOR2_X1M_A12TUL_C35 + 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XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33053 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33054 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33055 + AOI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33056 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33057 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33058 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33059 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33060 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33061 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33062 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33063 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33064 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33065 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33073 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33074 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33075 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33076 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33077 + AOI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33078 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33079 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33080 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33081 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33082 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33083 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33084 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33085 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33086 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33087 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33088 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33089 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33090 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33091 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33092 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33093 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33094 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33095 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33096 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33097 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33098 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33099 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33322 + AOI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33323 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33324 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33325 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33326 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33327 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33328 + NAND4BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33329 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33330 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33331 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33332 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33333 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33334 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33335 + NOR2_X8A_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33564 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33565 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33566 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33567 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33568 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33569 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33570 + XOR2_X4M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33578 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33579 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33580 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33581 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33582 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33583 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33584 + MXIT2_X4M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33606 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33607 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33608 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33609 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33610 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33611 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33612 + XOR2_X4M_A12TUL_C35 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33744 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33745 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33746 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33747 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33748 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33749 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U33750 + OAI21_X0P5M_A12TUL_C35 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34345 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34348 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34350 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34354 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34357 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34395 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34397 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34398 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34399 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34400 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34408 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34409 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34410 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34411 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34412 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34413 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34414 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34415 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34416 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34417 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34418 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34419 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34420 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34421 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34422 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34423 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34424 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34425 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34426 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U34427 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36219 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36221 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36223 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36224 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36225 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36226 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36227 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36228 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36229 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36231 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36233 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36234 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36235 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36236 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36237 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36238 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36239 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36241 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36243 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36244 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36259 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36260 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36261 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36263 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36265 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36266 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36267 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36268 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36270 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36271 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36272 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36273 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36274 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36275 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36276 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36277 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36278 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36279 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36280 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36281 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36282 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36283 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36284 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36285 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36286 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36287 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36288 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36289 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36290 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36291 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36292 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36293 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36294 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36295 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36296 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36297 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36298 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36299 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36300 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36301 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36302 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36303 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36304 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36305 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36306 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36307 + 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+ NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36315 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36316 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36317 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36318 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36319 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36320 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U36321 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INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37306 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37314 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37317 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37324 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37333 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37337 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37339 + INV_X0P6B_A12TUL_C35 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37360 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37361 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37364 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37366 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37796 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37797 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37798 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37799 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37800 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37801 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37802 + MXIT2_X0P5M_A12TUL_C35 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37810 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37811 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37812 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37813 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37814 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37815 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37823 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37824 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37825 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37826 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37827 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37828 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37829 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37830 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37831 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37832 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37833 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37834 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37835 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37836 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37837 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37838 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37839 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37840 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37841 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37842 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37843 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37857 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37858 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37859 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37860 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37861 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37862 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37863 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37864 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37865 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37866 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37867 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37868 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37869 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 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1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37877 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37878 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37879 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37880 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37881 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37882 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37883 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37884 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37885 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37886 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37887 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37888 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37889 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37890 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37891 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37892 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37893 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37894 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37895 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37896 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37904 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37905 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37906 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37907 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37908 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37909 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37910 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37911 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37912 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37913 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37914 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37915 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37916 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37924 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37925 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37926 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37927 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37928 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37929 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37930 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37931 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37932 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37933 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37934 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37935 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37936 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37937 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37938 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37939 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37940 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37941 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37942 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37943 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_1__vx_alu_U37944 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6252 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6253 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6254 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6255 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6256 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6257 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U6258 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9224 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9225 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9226 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9227 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9228 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9229 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9230 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9231 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9232 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9233 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9234 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9235 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9236 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9238 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9239 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9240 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9241 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9242 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9243 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9244 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9245 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9246 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9247 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9248 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9249 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9250 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9251 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9252 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9253 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9254 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9255 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9256 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9257 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9258 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9684 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9685 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9686 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9687 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9688 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9689 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9690 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9691 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9692 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9693 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9694 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9695 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9696 + AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9697 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9698 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9699 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9700 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9701 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9702 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9703 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9704 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9712 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9713 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9714 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9715 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9716 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9717 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U9718 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11101 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11102 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11103 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11105 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11106 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11107 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11108 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11109 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11110 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11111 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11112 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11113 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11114 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11115 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11116 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11117 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11118 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11119 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11120 + OAI21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11121 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11122 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11123 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11124 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11125 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11126 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11127 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11135 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11136 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11137 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11138 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11139 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11140 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11141 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11142 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11143 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11145 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11146 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11147 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11148 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11149 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11150 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11151 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11153 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11154 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11155 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11156 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11157 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11158 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11159 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11160 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11161 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11162 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11163 + NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11164 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11165 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11166 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11167 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11168 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11169 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11170 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11171 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11172 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11173 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11174 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11175 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11176 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11177 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11178 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11179 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11180 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11181 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11182 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11327 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11328 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11329 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11330 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11331 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11332 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11333 + NAND2_X0P5B_A12TUL_C35 + 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XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11890 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11891 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11892 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11893 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11894 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U11895 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12555 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12556 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12557 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12558 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12559 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12560 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12561 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12562 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12563 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12564 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12565 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12566 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12567 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12568 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12569 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12570 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12571 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12572 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12573 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12574 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U12575 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13155 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13156 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13157 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13158 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13159 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13160 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13161 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13162 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13163 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13164 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13165 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13166 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13167 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13168 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13169 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13170 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13171 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13172 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13173 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13174 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13175 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13176 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13177 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13178 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13179 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13180 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13181 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13182 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13183 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13184 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13185 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13186 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13187 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13188 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13189 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13190 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13191 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13192 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13193 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13194 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13195 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13196 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13197 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13198 + NAND3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13200 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13201 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13202 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13203 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13204 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13205 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13206 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13207 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13208 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13209 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13210 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13211 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13212 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13213 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13214 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13215 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13216 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13217 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13218 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13219 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13220 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13221 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13222 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13223 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13224 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13225 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13226 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13227 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13228 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13229 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13399 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13400 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13401 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13402 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13403 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13404 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13405 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13406 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13407 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13408 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13409 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13410 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13411 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13412 + NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13413 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13414 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13415 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13416 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13417 + AO21A1AI2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13418 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+ 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13433 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13434 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13435 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13436 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13437 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13438 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13439 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13440 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13441 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13442 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13443 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13444 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13445 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13446 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13460 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13461 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13462 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13463 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13464 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13465 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13466 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13467 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13468 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13469 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13470 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13471 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13472 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+ 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13480 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13481 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13482 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13483 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13484 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13485 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13486 + OAI21_X2M_A12TUL_C35 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13781 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13782 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13783 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13784 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13785 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13786 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13787 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13788 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13789 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13790 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13791 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13792 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13793 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13794 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13809 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13810 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13811 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13812 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13813 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13814 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13815 + AOI22_X1M_A12TUL_C35 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1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13871 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13872 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13873 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13874 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13875 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13876 + XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13877 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13878 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13879 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13880 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13881 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13882 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13883 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13884 + AOI21_X1P4M_A12TUL_C35 + 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13968 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13969 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13970 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13971 + OAI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13972 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13973 + BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13974 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13975 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13976 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13977 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13978 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13979 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13980 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13981 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13982 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13983 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13984 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13985 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13986 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13987 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13988 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13989 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13990 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13991 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13992 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13993 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13994 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13995 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13996 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13997 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13998 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U13999 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14000 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14001 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14002 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14003 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14004 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14005 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14006 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14007 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14008 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14009 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14010 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14011 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14012 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14013 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14014 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14015 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14016 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14017 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14018 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14019 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14020 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14021 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14022 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14023 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14024 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14025 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14026 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14027 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14028 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14029 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14030 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14031 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14032 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14033 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14034 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14035 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14036 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14037 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14038 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14039 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14040 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14041 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14042 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14043 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14044 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14045 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14046 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14047 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14048 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14049 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14050 + 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+ INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14058 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14059 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14060 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14061 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14062 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14063 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14064 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14961 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14962 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14963 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14964 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14965 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14966 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14967 + NAND2_X2A_A12TUL_C35 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+ NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14996 + NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14997 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14998 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U14999 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15000 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15001 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15175 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15176 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15177 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15178 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15179 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15180 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15181 + NAND2_X1B_A12TUL_C35 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15265 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15266 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15267 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15268 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15269 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15270 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U15271 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16265 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16266 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16267 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16268 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16269 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16270 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16271 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16272 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16273 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16274 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16275 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16276 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16277 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16278 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16279 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16280 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16281 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16282 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16283 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16284 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16285 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16286 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16287 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16288 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16289 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16290 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16291 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16292 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16293 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16295 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16296 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16297 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16298 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16299 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16300 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16301 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16302 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16303 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16304 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16305 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16306 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16307 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16308 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16309 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16310 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16311 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16312 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16314 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16315 + INV_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16316 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16317 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16319 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16320 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16321 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16323 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16324 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16325 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16326 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16327 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16328 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16329 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16330 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16331 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16332 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16333 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16334 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16335 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16336 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16337 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16338 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16339 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16340 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16844 + AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16845 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16846 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16847 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16848 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16849 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16850 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16858 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16859 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16860 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16861 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16862 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16863 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U16864 + 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+ NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17021 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17022 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17023 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17024 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17025 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17026 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+ 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17658 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17659 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17660 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17661 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17662 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17663 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17664 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17665 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17666 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17667 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17668 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17669 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17670 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17671 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17672 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17673 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17674 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17675 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17676 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17677 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17678 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17679 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17680 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17681 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17682 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17683 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17684 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17685 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17686 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17687 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17688 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17689 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17690 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17691 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17692 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17693 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17694 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17695 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17696 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17697 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17698 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17699 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17700 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17701 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17702 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17703 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17704 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17705 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17706 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17707 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17708 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17709 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17710 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17711 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17712 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17713 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17714 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17715 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17716 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17717 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17718 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17719 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17720 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17721 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17722 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17723 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17724 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U17725 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29113 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29114 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29115 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29116 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29117 + NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29118 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29126 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29127 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29128 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29129 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29130 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29131 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29132 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29133 + NOR2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29134 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29135 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29136 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29137 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29138 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29139 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29289 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29290 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29291 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29292 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29293 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29294 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U29295 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31033 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31034 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31035 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31036 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31037 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31038 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31039 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31040 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31041 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31042 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31043 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31044 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31045 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31046 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31047 + AOI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31048 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31049 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31050 + AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31051 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31052 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31053 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31054 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31055 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31056 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31057 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31058 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31059 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31060 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31061 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31062 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31063 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31064 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31065 + AOI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31066 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31067 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31068 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31069 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31070 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31071 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31072 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31073 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31074 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31075 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31076 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31077 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31078 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31079 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31080 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31081 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31082 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31083 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31084 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31085 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31086 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31087 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31088 + OA21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31089 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31090 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31091 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31092 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31093 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31094 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31095 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31096 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31097 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31098 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31099 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31100 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31101 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31102 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31103 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31104 + OAI2XB1_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31105 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31106 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31107 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31108 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31109 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31110 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31111 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31112 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31113 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31114 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31115 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31116 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31117 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31118 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31119 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31120 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31121 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31122 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31123 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31124 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31125 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31126 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31127 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31128 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31129 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31130 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31131 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31132 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31133 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31134 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 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+vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31142 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31143 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31144 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31145 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31146 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31147 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31148 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31149 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31150 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31151 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31152 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31153 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31154 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31155 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31156 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31157 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31158 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31159 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31160 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31161 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31162 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31163 + NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31164 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31165 + BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31166 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31167 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31168 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31169 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31170 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31171 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31172 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31173 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31174 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31175 + BUF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31176 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31177 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31178 + OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31179 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31180 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31181 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31182 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31183 + NOR2_X2A_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31191 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31192 + OAI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31193 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31194 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31195 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31196 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31197 + 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+ AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31393 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31394 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31395 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31396 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31397 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31398 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31399 + 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+ AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31442 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31443 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31444 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31445 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31446 + NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31447 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31448 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31449 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31450 + NAND2B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31451 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31452 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31453 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31454 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31455 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31456 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31457 + NOR2B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31458 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31459 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31460 + AOI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31461 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31462 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31463 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31464 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31465 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31466 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31467 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31468 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 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2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31476 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31477 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31478 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31479 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31480 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31481 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31482 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31483 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31484 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31485 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31486 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31487 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31488 + OAI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31489 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31490 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31491 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31492 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31493 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31494 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31495 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31496 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31497 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31498 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31499 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31500 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31501 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31502 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31503 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31504 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31505 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31506 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31507 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31508 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31509 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31510 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31511 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31512 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31513 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31514 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31515 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31516 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31517 + OR2_X6M_A12TUL_C35 + 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NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31616 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31617 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31618 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31619 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31620 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31621 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31622 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31623 + OA1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31624 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31625 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31626 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31627 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31628 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31629 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NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31665 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31666 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31667 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31668 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31669 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31670 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31671 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31672 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31673 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31674 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31675 + OR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31676 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31677 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31678 + 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NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31693 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31694 + OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31695 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31696 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31697 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31698 + NAND2B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31699 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31700 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31701 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31702 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31703 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31704 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31705 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31706 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31707 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31708 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31709 + OAI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31710 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31711 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31712 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31713 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31714 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31715 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31716 + OA22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31717 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31718 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31719 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31720 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31721 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31722 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31723 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31724 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31725 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31726 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 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2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31762 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31763 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31764 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31765 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31766 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31767 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31768 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31769 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31770 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31771 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31772 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31773 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31774 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31775 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31776 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31777 + NOR2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31778 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31779 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31780 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31781 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31782 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31783 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31784 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31785 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31786 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31787 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31788 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31789 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31790 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31791 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31792 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31793 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31794 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31795 + NAND3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31796 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31797 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31798 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31799 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31800 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31801 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31802 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31803 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31804 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31805 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31806 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31807 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31808 + OA1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31809 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31810 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31811 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31812 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31813 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31814 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31815 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31816 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31817 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31818 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31819 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31820 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31821 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31822 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31823 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31824 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31825 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31826 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31827 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31828 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31829 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31830 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31831 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31832 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31833 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31834 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31835 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31836 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31837 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31838 + OR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31839 + OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31840 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31841 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31842 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31843 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31844 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31845 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31846 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31847 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31848 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31849 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31850 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U31851 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 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2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33194 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33195 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33196 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33197 + INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33198 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33199 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33200 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33222 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33223 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33224 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33225 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33226 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33227 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33228 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33229 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33230 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33231 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33232 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33233 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33234 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33235 + AND2_X6M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33243 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33244 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33245 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33246 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33247 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33248 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33249 + AOI21_X3M_A12TUL_C35 + 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+ INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33347 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33348 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33349 + NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33350 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33351 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33352 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33353 + 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1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33402 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33403 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33404 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33405 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33406 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33407 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33408 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33409 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33410 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33411 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33412 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33413 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33414 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33415 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33520 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33521 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33522 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33523 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33524 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33525 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33526 + OA21A1OI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33527 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33528 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33529 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33530 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33531 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33532 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33533 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33534 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33535 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33536 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33537 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33538 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33539 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33540 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33541 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33542 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33543 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33544 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33545 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33546 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33547 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33548 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33549 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33550 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33551 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33552 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33553 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33554 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33555 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33556 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33557 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33558 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33559 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33560 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33561 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33562 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33563 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33564 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33565 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33566 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33567 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33568 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33569 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33570 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33571 + AOI2XB1_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33572 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33573 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33574 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33575 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33576 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33577 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33578 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33579 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33580 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33581 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33582 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33583 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33584 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33585 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33586 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33587 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33588 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33589 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33590 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33591 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33592 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33593 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33594 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33595 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33596 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33597 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33598 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33599 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33600 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33601 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33602 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33603 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33604 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33605 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33606 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33607 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33608 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33609 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33610 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33611 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33612 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33613 + NOR2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33614 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33615 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33616 + NAND2_X3A_A12TUL_C35 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33624 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33625 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33626 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33627 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33628 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33629 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33630 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33631 + NOR3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33632 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33633 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33634 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33635 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33636 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33637 + AOI22_X3M_A12TUL_C35 + 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OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33645 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33646 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33647 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33648 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33649 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33650 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33651 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33652 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33653 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33654 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33655 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33656 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33657 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33658 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33659 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33660 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33661 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33662 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33663 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33664 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33665 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33666 + OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33667 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33668 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33669 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33670 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33671 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33672 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33673 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33674 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33675 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33676 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33677 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33678 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33679 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33680 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33681 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33682 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33683 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33684 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33685 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33686 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33687 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33688 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33689 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33690 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33691 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33692 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33693 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33694 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33695 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33696 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33697 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33698 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33699 + CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33700 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33701 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33702 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33703 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33704 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33705 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33706 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33707 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33708 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33709 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33710 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33711 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33712 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33713 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33714 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33715 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33716 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33717 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33718 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33719 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33720 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33721 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33722 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33723 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33724 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33725 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33726 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33727 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33728 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33729 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33730 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33731 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33732 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33733 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33734 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33735 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33736 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33737 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33738 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33739 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33740 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33741 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33742 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33743 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33744 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33745 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33746 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33747 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33748 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33749 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33750 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33751 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33752 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33753 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33754 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U33755 + INV_X0P6B_A12TUL_C35 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34259 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34261 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34263 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34265 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34266 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34267 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34268 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34269 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34270 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34271 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34272 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34273 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34274 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34275 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34276 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34277 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34278 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34279 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34280 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34281 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34282 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34283 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34284 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34285 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34286 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34287 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34288 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34289 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34290 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34292 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34293 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34294 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34295 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34296 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34297 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34300 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34302 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34304 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34305 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34307 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34311 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34315 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34317 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34318 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34322 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34324 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34325 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34327 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34328 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34332 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34335 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34337 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34339 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34342 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34343 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34344 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34347 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34350 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34352 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34356 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34357 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34358 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34360 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34364 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34365 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34366 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34367 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34368 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34369 + NAND2_X1A_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34377 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34378 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34379 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34381 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34387 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34389 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34391 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34395 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34397 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34405 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34406 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34407 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34408 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34409 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34410 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+ NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34998 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U34999 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35000 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35001 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35002 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35003 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35004 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35005 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35006 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35007 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35008 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35009 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35010 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35011 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35012 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35013 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35014 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35015 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35016 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35017 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35018 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35019 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35020 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35021 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35022 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35023 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35024 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35025 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35026 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35027 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35028 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35029 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35030 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35031 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35032 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35033 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35034 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35035 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35036 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35037 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35038 + BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35039 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35040 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35041 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35042 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35043 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35044 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35045 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35046 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35047 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35048 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35049 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35050 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35051 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35052 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35053 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35054 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35055 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35056 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35057 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35058 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35059 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35060 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35061 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35062 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35063 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35064 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35065 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35066 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35067 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35068 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35069 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35070 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35071 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35072 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35073 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35074 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35075 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35076 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35077 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35078 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35079 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35080 + AOI22_X2M_A12TUL_C35 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35236 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35238 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35239 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35241 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35243 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35244 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U35246 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36074 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36075 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36076 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36077 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36078 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36079 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36094 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36095 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36096 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36097 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36098 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36099 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36100 + 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2.754000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36114 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36115 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36116 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36117 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36118 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36119 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U36120 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37565 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37566 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37567 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37568 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37569 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37570 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37571 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37572 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37573 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37574 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37575 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37576 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37577 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37578 + CGENI_X1M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37586 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37587 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37588 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37589 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37590 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37591 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37592 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37593 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37594 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37595 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37596 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37597 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37598 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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+ 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37606 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37607 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37608 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37609 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37610 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37611 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37612 + ADDF_X1M_A12TUL_C35 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37620 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37621 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37622 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37623 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37624 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37625 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37633 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37634 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37635 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37636 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37637 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37638 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37639 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37640 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37641 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37642 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37643 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37644 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37645 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37646 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37674 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37675 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37676 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37677 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37678 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37679 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37694 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37695 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37696 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37697 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37698 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37699 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37700 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37701 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37702 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37703 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37704 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37705 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_2__vx_alu_U37706 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6191 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6192 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6193 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6194 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6195 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6196 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6197 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6198 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6199 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6200 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6201 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6202 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6203 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6204 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6205 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6206 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6207 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6208 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6209 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6210 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U6211 + NAND3_X3A_A12TUL_C35 + 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0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7588 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7589 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7590 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7591 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7592 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7593 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7594 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7595 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7596 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7597 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7598 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7599 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7600 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7601 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7602 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7603 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7604 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7605 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7607 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7608 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7609 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7610 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7611 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7612 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7613 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7614 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7615 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7616 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7617 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7618 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7619 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7620 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7621 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7622 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7623 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7624 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7625 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7626 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7627 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7628 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7629 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7630 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7631 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7632 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7633 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7634 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7635 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7636 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7637 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7638 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7639 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7640 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7641 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7642 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U7643 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8971 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8972 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8973 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8974 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8975 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8976 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8977 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8978 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8979 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8980 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8981 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8982 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8983 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8984 + 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+ NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8992 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8993 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8994 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8995 + AOI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8996 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U8997 + AOI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9639 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9640 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9641 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9642 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9643 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9644 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U9645 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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+ 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10492 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10493 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10494 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10495 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10496 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10497 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10498 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10499 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10500 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10501 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10502 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10503 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10504 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10505 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10506 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10507 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10508 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10509 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10510 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10511 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10512 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10513 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10514 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10515 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10516 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10517 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10518 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 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1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10526 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10527 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10528 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10529 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10530 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10531 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10532 + NAND2_X1B_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10874 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10875 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10876 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10877 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10878 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10879 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10880 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10881 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10882 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10883 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10884 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10885 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10886 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10887 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10888 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10889 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10890 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10891 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10892 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10893 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10894 + 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AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10902 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10903 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10904 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10905 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10906 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10907 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10908 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10909 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10910 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10911 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10912 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10913 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10914 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10922 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10923 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10924 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10925 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10926 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10927 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10928 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10929 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10930 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10931 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10932 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10933 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10934 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10935 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10936 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10937 + AOI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10938 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10939 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10940 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10941 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10942 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10943 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10944 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10945 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10946 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10947 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10948 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10949 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10950 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10951 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10952 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10953 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10954 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10955 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10956 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10957 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10958 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10959 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10960 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10961 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10962 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10963 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10964 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10965 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10966 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10967 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10968 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10969 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10970 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10971 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10972 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10973 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10974 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10975 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10976 + OR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10977 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10978 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10979 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10980 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10981 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10982 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10983 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10984 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10985 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10986 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10987 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10988 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10989 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10990 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10991 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10992 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10993 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10994 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10995 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10996 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10997 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10998 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U10999 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11000 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11001 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11002 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11003 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11004 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11005 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11006 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11007 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11008 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11009 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11010 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11011 + INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11012 + BUF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11013 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11014 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11015 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11016 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11017 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11018 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11019 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11020 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11021 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11022 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11023 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11024 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11025 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11033 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11034 + XNOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11035 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11036 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11037 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11038 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11039 + XNOR2_X1M_A12TUL_C35 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+ NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11294 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11295 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11296 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11297 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11298 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11299 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U11300 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12185 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12186 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12187 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12188 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12189 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12190 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12191 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12192 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12193 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12194 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12195 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12196 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12197 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12198 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12199 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12200 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12201 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12202 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12203 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12204 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12226 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12227 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12228 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12229 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12230 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12231 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12232 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12233 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12234 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12235 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12236 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12237 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12238 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12239 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12240 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12241 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12242 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12243 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U12245 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13155 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13156 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13157 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13158 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13159 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13160 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13161 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13162 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13163 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13164 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13168 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13170 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13171 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13172 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13173 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13174 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13175 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13176 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13177 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13178 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13180 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13181 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13182 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13183 + OAI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13184 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13185 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13186 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13187 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13188 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13189 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13190 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13191 + OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13192 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13193 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13194 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13195 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13196 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13197 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13198 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13199 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13200 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13202 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13203 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13204 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13205 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13206 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13207 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13208 + OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13209 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13210 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13211 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13213 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13214 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13215 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13216 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13217 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13218 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13219 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13220 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13221 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13222 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13223 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13224 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13225 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13226 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13228 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13229 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13230 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INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13238 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13239 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13240 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13241 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13242 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13243 + XOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U13244 + 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0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14197 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14198 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14199 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14200 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14202 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14203 + INV_X0P6B_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14306 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14307 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14308 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14309 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14310 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14311 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14312 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14313 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14314 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14315 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14316 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14317 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14318 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14326 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14327 + XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14328 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14329 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14330 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14331 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14332 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14333 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14334 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14335 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14336 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14337 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14338 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14339 + NAND2_X6M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14348 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14349 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14350 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14351 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14352 + CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14353 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14354 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14355 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14356 + OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14357 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14358 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14359 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14367 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14368 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14369 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14370 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14371 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14372 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U14373 + INV_X3M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17176 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17177 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17178 + AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17179 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17180 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17181 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17182 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17203 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17204 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17205 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17206 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17207 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17208 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17209 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17210 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17211 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17212 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17213 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17214 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17215 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17216 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17217 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17218 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17219 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17220 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17221 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17222 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17223 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17224 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17225 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17226 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17227 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17228 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17229 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U17230 + 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0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23518 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23519 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23520 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23521 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23522 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23523 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23524 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23525 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23526 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23527 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23528 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23529 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23530 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23538 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23539 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23540 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23541 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23542 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23543 + NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U23544 + OAI21_X3M_A12TUL_C35 + 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+ 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28771 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28772 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28773 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28774 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28775 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28776 + NOR4BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28777 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28778 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28779 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28780 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28781 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28782 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28783 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28784 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28785 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28786 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28787 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28788 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28789 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28790 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28791 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28792 + OAI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28793 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28794 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28795 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28796 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28797 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 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1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28805 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28806 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28807 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28808 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28809 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28810 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28811 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28812 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28813 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28814 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28815 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28816 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28817 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28818 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28819 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28820 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28821 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28822 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28823 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28824 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28825 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28826 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28827 + XNOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28828 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28829 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28830 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U28831 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31413 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31414 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31415 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31416 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31417 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31418 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31419 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31420 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31421 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31422 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31423 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31424 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31425 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31426 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31427 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31428 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31429 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31430 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31431 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31432 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31433 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31434 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31435 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31436 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31437 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31438 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31439 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31440 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31441 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31442 + XOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31443 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31444 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31445 + BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31446 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31447 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31448 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31449 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31450 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31451 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31452 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31453 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31454 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31455 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31456 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31457 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31458 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31459 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31460 + OAI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31461 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31462 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31463 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31464 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31465 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31466 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31467 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31468 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31469 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31470 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31471 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31472 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31473 + XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31474 + AOI2XB1_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31475 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31476 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31477 + NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31478 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31479 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31480 + AOI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31481 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31482 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31483 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31484 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31485 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31486 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31487 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31488 + NOR3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31489 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31490 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31491 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31492 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31493 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31494 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31495 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31496 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31497 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31498 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31499 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31500 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31501 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31502 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31503 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31504 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31505 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31506 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31507 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31508 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31509 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 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OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31768 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31769 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31770 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31771 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31772 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31773 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31774 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31775 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31776 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31777 + MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31778 + AOI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31779 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31780 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31781 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31782 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31783 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31784 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31785 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31786 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31787 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31788 + MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31789 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31790 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31791 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31792 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31793 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31794 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31795 + 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AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31810 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31811 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31812 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31813 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31814 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31815 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31816 + BUF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31817 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31818 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31819 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31820 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31821 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31822 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31823 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31824 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31825 + MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31826 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31827 + AOI2XB1_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31828 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31829 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 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3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31858 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31859 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31860 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31861 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31862 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31863 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31864 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31865 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31866 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31867 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31868 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31869 + OAI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31870 + NOR2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31871 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31872 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31873 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31874 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31875 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31876 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31877 + NAND2B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31878 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31879 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31880 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31881 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31882 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31883 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31884 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31885 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31886 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31887 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31888 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31889 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31890 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31891 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31892 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31893 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31894 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31895 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31896 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31897 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31898 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31899 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31900 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31901 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31902 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31903 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31904 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31905 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31906 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31907 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31908 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31909 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31910 + NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31911 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31912 + NOR2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31913 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31914 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31915 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31916 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31917 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31918 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31919 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31920 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31921 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31922 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31923 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31924 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31925 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31926 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U31927 + MXIT2_X3M_A12TUL_C35 + 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INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32143 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32144 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32145 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32146 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32147 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32148 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U32149 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33597 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33598 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33599 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33600 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33601 + OA1B2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33602 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33603 + MX2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.346000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33604 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33605 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33606 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33607 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33608 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33609 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33610 + NAND3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33611 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33612 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33613 + OA21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33614 + XOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33615 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33616 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33617 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33618 + CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33619 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33620 + OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33621 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33622 + AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33623 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33624 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33625 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33626 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33627 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33628 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33629 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33630 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33631 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33632 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33633 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33634 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33635 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33636 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33637 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33638 + XNOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33639 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33640 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33641 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33642 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33643 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33644 + MX2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.346000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33645 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33646 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33647 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33648 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33649 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33650 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33651 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33652 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33653 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33654 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33655 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33656 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33657 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33658 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33659 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33660 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33661 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33662 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33663 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33664 + AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33665 + OAI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33666 + 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4.698000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33847 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33848 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33849 + XNOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33850 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33851 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33852 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33853 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33854 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33855 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33856 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33857 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33858 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33859 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33860 + AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33861 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33862 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33863 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33864 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33865 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33866 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33867 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33868 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33869 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33870 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33871 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33872 + AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33873 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33874 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33875 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33876 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33877 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33878 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33879 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33880 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33881 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33882 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33883 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33884 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33885 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33886 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33887 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33888 + NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c 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1.944000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33896 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33897 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33898 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33899 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33900 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33901 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33902 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33903 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33904 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33905 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33906 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33907 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33908 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33909 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33910 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33911 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33912 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33913 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33914 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33915 + NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33916 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33917 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33918 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33919 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33920 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33921 + XOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33922 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33923 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33924 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33925 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33926 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33927 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33928 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33929 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33930 + 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+ NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33987 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33988 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33989 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33990 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33991 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33992 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U33993 + 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+ AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34582 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34583 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34584 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34585 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34586 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34587 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34588 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34589 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34590 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34592 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34596 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34597 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34599 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34602 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34612 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34614 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34615 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34616 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34617 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34618 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34619 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34620 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34621 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34622 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34624 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34625 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34626 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34627 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34628 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34629 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34630 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34631 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34632 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34633 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34635 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34638 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34639 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34640 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34641 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34642 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34643 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34645 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34646 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34647 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34648 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34649 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34650 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34651 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34652 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34653 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34654 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34655 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34656 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34657 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34658 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34659 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34660 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34661 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34662 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U34663 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35321 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35324 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35326 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35327 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35328 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35330 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35341 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35342 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35343 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35344 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35345 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35346 + AOI2XB1_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35347 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35348 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35349 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35350 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35351 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35352 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35353 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35354 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35355 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35356 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35357 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35360 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35361 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35364 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35366 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35367 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35368 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35370 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35372 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35374 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35376 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35377 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35381 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35383 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35386 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35389 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35391 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35395 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35397 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35399 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35400 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35401 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35402 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35403 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35404 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35405 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35406 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35407 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35408 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35409 + OAI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35410 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35411 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35412 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35413 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35414 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35415 + 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+ INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35430 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35431 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35432 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35433 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35434 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35435 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35436 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35437 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35438 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35439 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35440 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35441 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35442 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35494 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35497 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35498 + 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INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35506 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35508 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35510 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35512 + 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+vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35521 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35526 + NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35539 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35540 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35543 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35546 + OAI21_X0P5M_A12TUL_C35 + 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+ sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35555 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35556 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35557 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35558 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35559 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35560 + MXIT2_X4M_A12TUL_C35 + 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35826 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35827 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35828 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35829 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35830 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35831 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35832 + ADDF_X1M_A12TUL_C35 + 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35853 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35854 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35855 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35856 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35857 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35858 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U35859 + ADDF_X1M_A12TUL_C35 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36164 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36165 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36166 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36167 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36168 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36169 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36177 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36178 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36179 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36180 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36181 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36182 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36183 + ADDF_X1M_A12TUL_C35 + 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36204 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36205 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36206 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36207 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36208 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36209 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36210 + ADDF_X1M_A12TUL_C35 + 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36231 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36232 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36233 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36234 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36235 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36236 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36237 + ADDF_X1M_A12TUL_C35 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36245 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36246 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36247 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36248 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36249 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36250 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36258 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36259 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36260 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36261 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36262 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36263 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36264 + ADDF_X1M_A12TUL_C35 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36272 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36273 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36274 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36275 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36276 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36277 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36285 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36286 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36287 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36288 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36289 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36290 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36291 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36292 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36293 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36294 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36295 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36296 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36297 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36298 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36299 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36300 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36301 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36302 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36303 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36304 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36312 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36313 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36314 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36315 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36316 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36317 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36318 + ADDF_X1M_A12TUL_C35 + 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2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36339 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36340 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36341 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36342 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36343 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36344 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U36345 + ADDH_X1M_A12TUL_C35 + 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37887 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37888 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37889 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37890 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37891 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37892 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37914 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37915 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37916 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37917 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37918 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37919 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37934 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37935 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37936 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37937 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37938 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37939 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37940 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37941 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37942 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37943 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37944 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37945 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37946 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U37947 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38030 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38031 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38032 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38033 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38034 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38035 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38036 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38037 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38038 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38039 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38040 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38041 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38042 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38043 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38044 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38045 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38046 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38047 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38048 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38049 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38050 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38051 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38052 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38053 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38054 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38055 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38056 + XNOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38057 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38058 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38059 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38060 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38061 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_execUnit_genblk1_3__vx_alu_U38062 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_gpgpu_inst_U3 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U4 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U5 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U6 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U7 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U8 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U9 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U10 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U11 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U12 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U13 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U14 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U15 + NAND4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U16 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U17 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U18 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U19 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U21 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U22 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U23 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U24 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U25 + AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U27 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U28 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U29 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U30 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U31 + NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U32 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U33 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U34 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U35 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U36 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U37 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U38 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U39 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U40 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U41 + NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U42 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U44 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U45 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U46 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U47 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U48 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U49 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U50 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U53 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U54 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U55 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U56 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U57 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U58 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U59 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U60 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U61 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U62 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U63 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U64 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U66 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U67 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U68 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U69 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U70 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U71 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U72 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U73 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U74 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U75 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U76 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U77 + NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U78 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U79 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U80 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U81 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U82 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U83 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U84 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U85 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U86 + NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U87 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_U88 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U89 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U90 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U91 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U92 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U93 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U94 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U95 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U96 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U97 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U98 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U99 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U100 + NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U101 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U102 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U103 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U104 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U105 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U106 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpgpu_inst_U107 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U108 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U110 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U111 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U112 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U113 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U114 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U115 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U116 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U117 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U118 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U119 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U120 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U121 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U122 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U123 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_U124 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U125 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U126 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U127 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U128 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U129 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U130 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_U131 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U132 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U133 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U134 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U135 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U136 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U138 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U139 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U140 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U141 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U142 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_U143 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U144 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_U145 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U1 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U2 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U4 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpgpu_inst_sub_x_6_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpgpu_inst_valids_counter_U1 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpgpu_inst_valids_counter_U2 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_valids_counter_U3 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpgpu_inst_valids_counter_U4 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpgpu_inst_valids_counter_U5 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_U2 + BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_gpr_stage_U3 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_gpr_stage_U4 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_U5 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U1 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U2 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U3 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U4 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U5 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U6 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U7 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U8 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U9 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U10 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U11 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U12 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U13 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U14 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U15 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U16 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U17 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U18 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U19 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_VX_inst_mult_U20 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_csr_reg_U3 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U6 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U7 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U11 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U12 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U13 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U15 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U16 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U19 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U22 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U25 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U27 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U28 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U30 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U31 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_csr_reg_U32 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U33 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U34 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U35 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U36 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U37 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U38 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U39 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U40 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U41 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U42 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U44 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U45 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U46 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U47 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U50 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U52 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U53 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U54 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U55 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U56 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U57 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U58 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_U59 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_csr_reg_value_reg_32_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_33_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_34_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_35_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_36_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_37_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_38_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_39_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_40_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_41_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_42_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_43_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_44_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_45_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_46_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_47_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_48_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_49_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_50_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_51_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_52_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_53_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_54_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_55_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_56_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_57_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_58_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_csr_reg_value_reg_59_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_U3 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U6 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U7 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U8 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U9 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U10 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U11 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U12 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U13 + BUF_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U15 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U16 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U19 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U22 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U25 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U27 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U28 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U30 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U31 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U32 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U33 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U34 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U35 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U36 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U37 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U38 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U40 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U42 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U43 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U44 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U45 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U46 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U47 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U48 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U49 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U50 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U51 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U52 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U53 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U54 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U55 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U56 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U57 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U58 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U59 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U60 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U61 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U62 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U63 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U64 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U65 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U66 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U67 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U68 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U69 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U70 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U71 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U72 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U73 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U74 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U75 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U76 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U77 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U78 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U79 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U80 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U81 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U82 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U83 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U84 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U85 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U86 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U87 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U88 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U89 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U90 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U91 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U92 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U93 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U94 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U95 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U96 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U97 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U98 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U99 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U100 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U101 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U102 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U103 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U105 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U106 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U107 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U108 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U109 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U110 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U111 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U112 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U113 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U114 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U115 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U116 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U117 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U119 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U120 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U121 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U122 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U123 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U124 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U125 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U126 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U127 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U128 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U129 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U130 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U131 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U132 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U133 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U134 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U136 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U138 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U140 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U142 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U143 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U144 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U145 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U146 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U147 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U148 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U149 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U150 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U151 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U152 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U154 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U155 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U156 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U157 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U158 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U160 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U161 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U162 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U164 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U165 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U166 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U167 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U168 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U169 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U170 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U171 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U172 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U173 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U174 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U175 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U177 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U179 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U181 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U182 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U183 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U184 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U185 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U186 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U187 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U188 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U189 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U190 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U191 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U192 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U193 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U195 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U196 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U197 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U198 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U199 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U200 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U201 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U202 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U203 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U204 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U205 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U206 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U207 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U208 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U209 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U210 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U211 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U212 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U213 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U214 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U215 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U216 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U217 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U218 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U219 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U220 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U221 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U222 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U223 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U224 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U225 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U226 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U227 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U228 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U229 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U230 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U231 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U232 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U233 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U234 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U235 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U236 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U237 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U238 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U239 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U240 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U241 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U242 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U243 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U244 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U245 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U246 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U247 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U248 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U249 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U250 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U251 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U252 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U253 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U254 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U255 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U256 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U257 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U258 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U259 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U260 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U261 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U262 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U263 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U264 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U265 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U266 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U267 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U268 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U269 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U270 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U271 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U272 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U273 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U274 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U275 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U276 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U277 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U278 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U279 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U280 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U281 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U282 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U283 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U284 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U285 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U286 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U287 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U288 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U289 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U290 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U291 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U292 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U293 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U294 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U295 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U296 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U297 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U298 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U299 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U300 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U301 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U302 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U303 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U304 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U305 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U306 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U307 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U308 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U309 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U310 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U311 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U312 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U313 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U314 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U315 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U316 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U317 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U318 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U319 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U320 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U321 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U322 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U323 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U324 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U325 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U326 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U327 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U328 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U329 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U330 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U331 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U332 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U333 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U334 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U335 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U336 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U337 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U338 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U339 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U340 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U341 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U342 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U343 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U344 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U345 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U346 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U347 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U348 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U349 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U350 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U351 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U352 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U353 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U354 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U355 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U356 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U357 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U358 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U359 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U360 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U361 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U362 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U363 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U364 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U365 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U366 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U367 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U368 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U369 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U370 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U371 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U372 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U373 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U374 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U375 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U376 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U377 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U378 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U379 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U380 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U381 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U382 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U383 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U384 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U385 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U386 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U387 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U388 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U389 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U390 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U391 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U392 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U393 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U394 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U395 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U396 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U397 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U398 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U399 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U400 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U401 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U402 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U403 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U404 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U405 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U406 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U407 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U408 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U409 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U410 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U411 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U412 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U413 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U414 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U415 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U416 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U417 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U418 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U419 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U420 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U421 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U422 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U423 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U424 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U425 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U426 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U427 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U428 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U429 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U430 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U431 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U432 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U433 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U434 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U435 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U436 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U437 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U438 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U439 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U440 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U441 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U442 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U443 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U444 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U445 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U446 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U447 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U448 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U449 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U450 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U451 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U452 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U453 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U454 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U455 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U456 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U457 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U458 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U459 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U460 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U461 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U462 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U463 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U464 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U465 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U466 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U467 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U468 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U469 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U470 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U471 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U474 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U475 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U476 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U477 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U478 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U479 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U480 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U481 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U484 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U485 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U486 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U487 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U488 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U489 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U490 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U491 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U494 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U501 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U505 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U506 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U555 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U557 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U559 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U560 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U561 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U562 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U563 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U564 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U565 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U566 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U567 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U568 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U569 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U570 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U572 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U573 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U574 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U575 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U576 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U577 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U578 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U579 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U580 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U581 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U582 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U583 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U584 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U585 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U586 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U587 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U588 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U589 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U590 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U596 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U597 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U630 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U635 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U638 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U639 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U640 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U641 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U642 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U643 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U645 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U647 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U648 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U649 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U650 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U651 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U652 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U653 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U654 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U655 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U656 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U657 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U658 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U659 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U660 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U661 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U662 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U663 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U664 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U665 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U666 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U667 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U668 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U669 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U670 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U671 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U672 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U673 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U674 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U675 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U676 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U677 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U678 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U679 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U680 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U681 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U682 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U683 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U684 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U685 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U686 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U687 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U688 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U689 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U690 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U691 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U692 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U693 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U694 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U695 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U696 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U697 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U698 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U699 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U700 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U701 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U702 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U703 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U704 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U705 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U706 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U707 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U708 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U709 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U710 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U711 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U712 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U713 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U714 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U715 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U716 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U717 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U718 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U719 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U720 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U721 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U722 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U723 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U724 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U725 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U726 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U727 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U728 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U729 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U730 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U731 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U732 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U733 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U734 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U735 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U736 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U737 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U738 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U739 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U740 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U741 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U742 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U743 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U744 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U745 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U746 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U747 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U748 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U749 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U750 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U751 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U752 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U753 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U754 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U755 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U756 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U757 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U758 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U759 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U760 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U761 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U762 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U763 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U764 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U765 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U766 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U767 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U768 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U769 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U770 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U771 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U772 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U773 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U774 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U775 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U776 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U777 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U778 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U779 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U780 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U781 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U782 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U783 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U784 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U785 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U786 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U787 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U788 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U789 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U790 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U791 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U792 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U793 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U794 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U795 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U796 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U797 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U798 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U799 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U800 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U801 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U802 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U803 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U804 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U805 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U806 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U807 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U808 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U809 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U810 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U811 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U812 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U813 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U814 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U815 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U816 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U817 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U818 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U819 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U820 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U821 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U822 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U823 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U824 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U825 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U826 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U827 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U828 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U829 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U830 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U831 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U832 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U833 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U834 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U835 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U836 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U837 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U838 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U839 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U840 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U841 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U842 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U843 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U844 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U845 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U846 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U847 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U848 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U849 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U850 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U851 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U852 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U853 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U854 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U855 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U856 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U857 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U858 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U859 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U860 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U861 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U862 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U863 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U864 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U865 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U866 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U867 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U868 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U869 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U870 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U871 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U872 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U873 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U874 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U875 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U876 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U877 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U878 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U879 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U880 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U881 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U882 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U883 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U884 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U885 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U886 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U887 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U888 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U889 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U890 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U891 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U892 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U893 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U894 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U895 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U896 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U897 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U898 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U899 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U900 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U901 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U902 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U903 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_U904 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_47_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_48_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_49_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_50_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_51_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_52_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_53_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_54_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_55_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_56_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_57_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_58_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_59_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_60_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_61_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_62_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_63_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_64_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_65_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_66_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_67_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_68_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_69_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_70_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_71_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_72_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_73_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_74_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_75_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_76_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_77_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_78_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_79_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_80_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_81_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_82_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_83_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_84_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_85_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_86_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_87_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_88_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_89_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_90_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_91_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_92_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_93_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_94_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_95_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_96_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_97_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_98_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_99_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_100_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_101_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_102_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_103_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_104_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_105_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_106_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_107_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_108_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_109_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_110_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_111_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_112_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_113_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_114_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_115_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_116_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_117_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_118_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_119_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_120_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_121_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_122_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_123_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_124_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_125_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_126_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_127_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_128_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_129_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_130_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_131_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_132_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_133_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_134_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_135_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_136_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_137_ + DFFSQN_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_138_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_139_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_140_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_141_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_142_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_143_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_144_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_145_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_146_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_147_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_148_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_149_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_150_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_151_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_152_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_153_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_154_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_155_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_156_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_157_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_158_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_159_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_160_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_161_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_162_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_163_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_164_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_165_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_166_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_167_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_168_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_169_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_170_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_171_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_172_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_173_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_174_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_175_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_176_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_177_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_178_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_179_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_180_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_181_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_182_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_183_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_184_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_185_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_186_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_187_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_188_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_189_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_190_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_191_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_192_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_193_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_194_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_195_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_196_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_197_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_198_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_199_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_200_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_201_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_202_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_203_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_204_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_205_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_206_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_207_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_208_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_209_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_210_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_211_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_212_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_213_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_214_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_215_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_216_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_217_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_218_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_219_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_220_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_221_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_222_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_223_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_224_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_225_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_226_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_227_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_228_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_229_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_230_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_231_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_232_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_233_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_234_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_235_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_236_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_237_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_238_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_239_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_240_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_241_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_242_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_243_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_244_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_245_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_246_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_247_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_248_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_249_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_250_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_251_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_252_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_253_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_254_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_255_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_256_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_257_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_258_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_259_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_260_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_261_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_262_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_263_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_264_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_265_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_266_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_267_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_268_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_269_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_270_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_271_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_272_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_273_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_274_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_275_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_276_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_277_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_278_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_279_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_280_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_281_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_282_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_283_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_284_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_285_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_286_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_287_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_288_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_289_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_290_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_291_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_292_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_293_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_294_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_295_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_296_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_297_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_298_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_299_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_300_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_301_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_302_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_303_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_304_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_305_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_306_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_307_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_308_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_309_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_310_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_311_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_312_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_313_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_314_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_315_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_316_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_317_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_318_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_319_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_320_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_321_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_322_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_323_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_324_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_325_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_326_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_327_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_328_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_329_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_330_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_331_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_332_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_333_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_334_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_335_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_336_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_337_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_338_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_339_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_340_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_341_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_342_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_343_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_344_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_345_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_346_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_347_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_348_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_349_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_350_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_351_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_352_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_353_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_354_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_355_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_356_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_357_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_358_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_359_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_360_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_361_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_362_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_363_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_364_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_365_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_366_ + DFFSQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_367_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_368_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_369_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_370_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_371_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_372_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_373_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_374_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_375_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_376_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_377_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_378_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_379_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_380_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_381_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_382_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_383_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_384_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_385_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_386_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_387_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_388_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_389_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_390_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_391_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_392_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_393_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_394_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_395_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_396_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_397_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_398_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_399_ + DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_400_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_401_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_402_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_403_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_404_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_405_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_406_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_407_ + DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_408_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_409_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_410_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_411_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_412_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_413_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_414_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_415_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_416_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_417_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_418_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_419_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_420_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_421_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_422_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_423_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_424_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_425_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_426_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_427_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_428_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_429_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_430_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_431_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_432_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_433_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_434_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_435_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_436_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_437_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_438_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_439_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_440_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_441_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_442_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_443_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_444_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_445_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_446_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_447_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_448_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_449_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_450_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_451_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_452_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_453_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_454_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_455_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_456_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_457_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_458_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_459_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_460_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_461_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_462_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_463_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_464_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_465_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_466_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_467_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_468_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_469_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_470_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_471_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_472_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_473_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_474_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_475_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_476_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_477_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_478_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_479_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_480_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_481_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_482_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_483_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_484_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_485_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_exec_unit_reg_value_reg_486_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_U3 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U4 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U5 + BUF_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U6 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U7 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U8 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U9 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U10 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U11 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U12 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U13 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U15 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U16 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U18 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U19 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U20 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U21 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U22 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U23 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U24 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U25 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U26 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U27 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U28 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U30 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U31 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U32 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U33 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U34 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U35 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U36 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U37 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U38 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U40 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U42 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U43 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U44 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U45 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U46 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U47 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U48 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U49 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U50 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U51 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U52 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U53 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U54 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U55 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U56 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U57 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U58 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U59 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U60 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U61 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U62 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U63 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U64 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U65 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U66 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U67 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U68 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U69 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U70 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U71 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U72 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U73 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U74 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U75 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U76 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U77 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U78 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U79 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U80 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U81 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U82 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U83 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U84 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U85 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U86 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U87 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U88 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U89 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U90 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U91 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U92 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U93 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U94 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U95 + NOR2_X0P5B_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U103 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U104 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U105 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U106 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U107 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U108 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U109 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U110 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U111 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U112 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U113 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U114 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U115 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U116 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U117 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U118 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U119 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U120 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U121 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U122 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U123 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U124 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U125 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U126 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U127 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U128 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U129 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U130 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U131 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U132 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U133 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U134 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U135 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U136 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U137 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U138 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U139 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U140 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U141 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U142 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U143 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U144 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U145 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U146 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U147 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U148 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U149 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U150 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U151 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U152 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U154 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U155 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U156 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U157 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U158 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U159 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U160 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U161 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U162 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U163 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U164 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U165 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U166 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U167 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U168 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U169 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U170 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U171 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U172 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U173 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U174 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U175 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U176 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U177 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U178 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U179 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U180 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U181 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U182 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U183 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U184 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U185 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U186 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U187 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U188 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U189 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U190 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U191 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U192 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U193 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U194 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U195 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U196 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U197 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U198 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U199 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U200 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U201 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U202 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U203 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U204 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U205 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U206 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U207 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U208 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U209 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U210 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U211 + BUF_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U212 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U213 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U214 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U215 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U216 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U217 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U219 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U224 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U227 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U228 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U229 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U230 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U231 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U232 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U236 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U238 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U239 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U241 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U243 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U249 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U250 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U251 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U252 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U253 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U254 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U255 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U256 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U257 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U259 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U261 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U263 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U265 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U266 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U267 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U268 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U270 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U271 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U272 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U273 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U274 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U275 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U276 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U277 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U278 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U279 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U280 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U281 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U282 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U283 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U284 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U285 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U286 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U287 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U288 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U289 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U290 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U292 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U293 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U295 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U296 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U297 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U300 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U302 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U304 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U305 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U317 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U327 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U342 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U344 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U350 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U357 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U360 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U364 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U366 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U367 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U368 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U370 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U372 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U374 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U376 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U377 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U381 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U389 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U391 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U395 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U397 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U399 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U400 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U401 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U402 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U403 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U405 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U406 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U407 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U408 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U409 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U410 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U411 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U412 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U413 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_U414 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_32_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_33_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_34_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_35_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_36_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_37_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_38_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_39_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_40_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_41_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_42_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_43_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_44_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_45_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_46_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_47_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_48_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_49_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_50_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_51_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_52_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_53_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_54_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_55_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_56_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_57_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_58_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_59_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_60_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_61_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_62_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_63_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_64_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_65_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_66_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_67_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_68_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_69_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_70_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_71_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_72_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_73_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_74_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_75_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_76_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_77_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_78_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_79_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_80_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_81_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_82_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_83_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_84_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_85_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_86_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_87_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_88_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_89_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_90_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_91_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_92_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_93_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_94_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_95_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_96_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_97_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_98_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_99_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_100_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_101_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_102_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_103_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_104_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_105_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_106_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_107_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_108_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_109_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_110_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_111_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_112_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_113_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_114_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_115_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_116_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_117_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_118_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_119_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_120_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_121_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_122_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_123_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_124_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_125_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_126_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_127_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_128_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_129_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_130_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_131_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_132_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_133_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_134_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_135_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_136_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_137_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_138_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_139_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_140_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_141_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_142_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_143_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_144_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_145_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_146_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_147_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_148_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_149_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_150_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_151_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_152_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_153_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_154_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_155_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_156_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_157_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_158_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_159_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_160_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_161_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_162_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_163_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_164_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_165_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_166_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_167_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_168_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_169_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_170_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_171_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_172_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_173_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_174_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_175_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_176_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_177_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_178_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_179_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_180_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_181_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_182_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_183_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_184_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_185_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_186_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_187_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_188_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_189_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_190_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_191_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_192_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_193_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_194_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_195_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_196_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_197_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_198_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_199_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_200_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_201_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_gpu_inst_reg_value_reg_202_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_U3 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_lsu_reg_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_lsu_reg_U5 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_lsu_reg_U7 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U8 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U9 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U10 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U11 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_lsu_reg_U12 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U13 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U14 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U15 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_lsu_reg_U16 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_lsu_reg_U17 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U18 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_lsu_reg_U19 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_lsu_reg_U20 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U21 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U22 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U23 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U24 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U25 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U26 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U27 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U28 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U29 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U30 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U31 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U32 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U33 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U34 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U35 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U36 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U37 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U38 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U39 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U40 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U41 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U42 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U43 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U44 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U45 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U46 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U47 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U48 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U49 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U50 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U51 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U52 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U53 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_back_end_VX_gpr_stage_lsu_reg_U54 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U55 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U56 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U57 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U58 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U59 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U60 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U61 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U62 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U63 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U64 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U65 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U66 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U67 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U68 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U69 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U70 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U71 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U72 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U73 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U74 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U75 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U76 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U77 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U78 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U79 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U80 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U81 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U82 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U83 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U84 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U85 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U86 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U87 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U88 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U89 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U90 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U91 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U92 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U93 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U94 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U95 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U96 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U97 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U98 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U99 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U100 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U101 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U102 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U103 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U104 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U105 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U106 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U107 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U108 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U109 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U110 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U111 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U112 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U113 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U114 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U115 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U116 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U117 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U118 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U119 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U120 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U121 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U122 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U123 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U124 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U125 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U126 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U127 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U128 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U129 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U130 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U131 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U132 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U133 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U134 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U135 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U136 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U137 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U138 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U139 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U140 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U141 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U142 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U143 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U144 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U145 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U146 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U147 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U148 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U149 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U150 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U151 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U152 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U153 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U154 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U155 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U156 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U157 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U158 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U159 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U160 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U161 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U162 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U163 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U164 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U165 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U166 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U167 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U168 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U169 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U170 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U171 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U172 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U173 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U174 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U175 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U176 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U177 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U178 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U179 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U180 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U181 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U182 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U183 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U184 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U185 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U186 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U187 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U188 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U189 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U190 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U191 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U192 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U193 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U194 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U195 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U196 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U197 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U198 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U199 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U200 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U201 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U202 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U203 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U204 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U205 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U206 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U207 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U208 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U209 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U210 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U211 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U212 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U213 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U214 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U215 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U216 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U217 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U218 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U219 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U220 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U221 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U222 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U223 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U224 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U225 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U226 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U227 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U228 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U229 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U230 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U231 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U232 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U233 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U234 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U235 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U236 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U237 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U238 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U239 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U240 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U241 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U242 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U243 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U244 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U245 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U246 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U247 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U248 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U249 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U250 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U251 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U252 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U253 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U254 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U255 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U256 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U257 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U258 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U259 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U260 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U261 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U262 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U263 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U264 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U265 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U266 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U267 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U268 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U269 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U270 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U271 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U272 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U273 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U274 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U275 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U276 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U277 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U278 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U279 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U280 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U281 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U282 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U283 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U284 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U285 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U286 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U287 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U288 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U289 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U290 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U291 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U292 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U293 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U294 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U295 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U296 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U297 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U298 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U299 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U300 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U301 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U302 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U303 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U304 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U305 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U306 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U307 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U308 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U309 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U310 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U311 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U312 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U313 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U314 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U315 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U316 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U317 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U318 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U319 + OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U320 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U321 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U322 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U323 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U324 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U325 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U326 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U327 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U328 + OAI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_lsu_reg_U329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U342 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U344 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U350 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U357 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U360 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U364 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U366 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U367 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U368 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U370 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U372 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U374 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U376 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U377 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U381 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U389 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U391 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U395 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U397 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U399 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U400 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U401 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U402 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U403 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U405 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U406 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U407 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U408 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U409 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U410 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U411 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U412 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U413 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U414 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U415 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U416 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U417 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U418 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U419 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U420 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U421 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U422 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U423 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U424 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U425 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U426 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U427 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U428 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U429 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U430 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U431 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U432 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U433 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U434 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U435 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U436 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U437 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U438 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U439 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U440 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U441 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U442 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U443 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U444 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U445 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U446 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U447 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U448 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U449 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U450 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U451 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U452 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U453 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U454 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U455 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U456 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U457 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U458 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U459 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U460 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U461 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U462 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U463 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U464 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U465 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U466 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U467 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U468 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U469 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U470 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U471 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U474 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U475 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U476 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U477 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U478 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U479 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U480 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U481 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U484 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U485 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U486 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U487 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U488 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U489 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U490 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U491 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U494 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U501 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U505 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U506 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U555 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U557 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U559 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U560 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U561 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U562 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U563 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U564 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U565 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U566 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U567 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U568 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U569 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U570 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U572 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U573 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U574 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U575 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U576 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U577 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U578 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U579 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U580 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U581 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U582 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U583 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U584 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U585 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U586 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U587 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U588 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U589 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U590 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U597 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U630 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U635 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_U636 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_13_ + DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_32_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_33_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_34_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_35_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_36_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_37_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_38_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_39_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_40_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_41_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_42_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_43_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_44_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_45_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_46_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_47_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_48_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_49_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_50_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_51_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_52_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_53_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_54_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_55_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_56_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_57_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_58_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_59_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_60_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_61_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_62_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_63_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_64_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_65_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_66_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_67_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_68_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_69_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_70_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_71_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_72_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_73_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_74_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_75_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_76_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_77_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_78_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_79_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_80_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_81_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_82_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_83_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_84_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_85_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_86_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_87_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_88_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_89_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_90_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_91_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_92_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_93_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_94_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_95_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_96_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_97_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_98_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_99_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_100_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_101_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_102_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_103_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_104_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_105_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_106_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_107_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_108_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_109_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_110_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_111_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_112_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_113_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_114_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_115_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_116_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_117_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_118_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_119_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_120_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_121_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_122_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_123_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_124_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_125_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_126_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_127_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_128_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_129_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_130_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_131_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_132_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_133_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_134_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_135_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_136_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_137_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_138_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_139_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_140_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_141_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_142_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_143_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_144_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_145_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_146_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_147_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_148_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_149_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_150_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_151_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_152_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_153_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_154_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_155_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_156_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_157_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_158_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_159_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_160_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_161_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_162_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_163_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_164_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_165_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_166_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_167_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_168_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_169_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_170_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_171_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_172_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_173_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_174_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_175_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_176_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_177_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_178_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_179_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_180_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_181_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_182_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_183_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_184_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_185_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_186_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_187_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_188_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_189_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_190_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_191_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_192_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_193_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_194_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_195_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_196_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_197_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_198_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_199_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_200_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_201_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_202_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_203_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_204_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_205_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_206_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_207_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_208_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_209_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_210_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_211_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_212_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_213_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_214_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_215_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_216_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_217_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_218_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_219_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_220_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_221_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_222_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_223_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_224_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_225_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_226_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_227_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_228_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_229_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_230_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_231_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_232_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_233_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_234_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_235_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_236_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_237_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_238_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_239_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_240_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_241_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_242_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_243_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_244_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_245_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_246_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_247_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_248_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_249_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_250_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_251_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_252_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_253_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_254_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_255_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_256_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_257_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_258_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_259_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_260_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_261_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_262_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_263_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_264_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_265_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_266_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_267_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_268_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_269_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_270_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_271_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_272_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_273_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_274_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_275_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_276_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_277_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_278_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_279_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_280_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_281_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_282_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_283_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_284_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_285_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_286_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_287_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_288_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_289_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_290_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_291_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_292_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_293_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_294_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_295_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_296_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_297_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_298_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_299_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_300_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_301_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_302_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_303_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_304_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_305_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_306_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_lsu_reg_value_reg_307_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U2 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U3 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U4 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U5 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U6 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U7 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U8 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U9 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U10 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U11 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U12 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U13 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U14 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U15 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U16 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U17 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U18 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U19 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U20 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U21 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U22 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U23 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U24 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U25 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U26 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U27 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U28 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U29 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U30 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U31 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U32 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U33 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U39 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U40 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U41 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U46 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U47 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U48 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U49 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U50 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U51 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U52 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U53 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U54 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U55 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U56 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U57 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U58 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U59 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U60 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U61 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U62 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U63 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U64 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U65 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U66 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U67 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U68 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U69 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U70 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U71 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U72 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U73 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U74 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U75 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U76 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U77 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U78 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U79 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U80 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U81 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U82 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U83 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U84 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U85 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U86 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U87 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U88 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U89 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U90 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U91 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U92 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U93 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U94 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U95 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U96 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U97 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U98 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U99 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U100 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U101 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U102 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U103 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U104 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U105 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U106 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U107 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U108 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U109 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U110 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U111 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U112 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U113 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U114 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U115 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U116 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U117 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U119 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U120 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U122 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U129 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U134 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U136 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U141 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U142 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U143 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U153 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U159 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U185 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U186 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U192 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U199 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U201 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U220 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U221 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U248 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U251 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U254 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U257 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U258 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U273 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U275 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U279 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U280 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U282 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U283 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U286 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U292 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U293 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U294 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U295 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U296 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U297 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U298 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U299 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U300 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U301 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U302 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U303 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U304 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U305 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U306 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U307 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U308 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U309 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U310 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U311 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U312 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U313 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U314 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U315 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U316 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U317 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U318 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U319 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U320 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U321 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U322 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U323 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U324 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U325 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U326 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U327 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U328 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U329 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U330 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U331 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U332 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U333 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U334 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U335 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U336 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U337 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U338 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U339 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U340 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U341 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U342 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U343 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U344 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U345 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U346 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U347 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U348 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U349 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U350 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U351 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U352 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U353 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U354 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U355 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U356 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U357 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U358 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U359 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U360 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U361 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U362 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U363 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U364 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U365 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U366 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U367 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U368 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U369 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U370 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U371 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U372 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U373 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U374 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U375 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U376 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U377 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U378 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U379 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U380 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U381 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U382 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U383 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U384 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U385 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U386 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U387 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U388 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U389 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U390 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U391 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U392 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U393 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U394 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U395 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U396 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U397 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U398 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U399 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U400 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U401 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U402 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U403 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U404 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U405 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U406 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U407 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U408 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U409 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U410 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U411 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U412 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U413 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U414 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U415 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U416 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U417 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U418 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U419 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U420 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U421 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U422 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U423 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U424 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U425 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U426 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U427 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U428 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U429 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U430 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U431 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U432 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U433 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U434 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U435 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U436 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U437 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U438 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U439 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U440 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U441 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U442 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U443 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U444 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U445 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U446 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U447 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U448 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U449 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U450 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U451 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U452 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U453 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U454 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U455 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U456 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U457 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U458 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U459 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U460 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U461 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U462 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U463 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U464 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U465 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U466 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U467 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U468 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U469 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U470 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U471 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U472 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U473 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U474 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U475 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U476 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U477 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U478 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U479 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U480 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U481 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U482 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U483 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U484 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U485 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U486 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U487 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U488 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U489 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U490 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U491 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U492 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U493 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U494 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U495 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U496 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U497 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U498 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U499 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U500 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U501 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U502 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U503 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U504 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U505 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U506 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U507 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U508 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U509 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U510 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U511 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U512 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U513 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U514 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U515 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U516 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U517 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U518 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U519 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U520 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U521 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U522 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U523 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U524 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U525 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U526 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U527 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U528 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U529 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U530 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U531 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U532 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U533 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U534 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U535 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U536 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U537 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U538 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U539 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U540 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U541 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U542 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U543 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U544 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U545 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U546 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U547 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U548 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U549 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U550 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U551 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U552 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U553 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U554 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U555 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U556 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U557 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U558 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U559 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U560 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U561 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U562 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U563 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U564 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U565 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U566 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U567 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U568 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U569 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U570 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U571 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U572 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U573 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U574 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U575 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U576 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U577 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U578 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U579 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U580 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U581 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U582 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U583 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U584 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U585 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U586 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U587 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U588 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U589 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U590 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U591 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U592 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U593 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U594 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U595 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U596 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U597 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U598 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U599 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U600 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U601 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U602 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U603 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U604 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U605 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U606 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U607 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U608 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U609 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U610 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U611 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U612 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U613 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U614 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U615 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U616 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U617 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U618 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U619 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U620 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U621 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U622 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U623 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U624 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U625 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U626 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U627 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U628 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U629 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U630 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U631 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U632 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U633 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U634 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U635 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U636 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U637 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U638 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U639 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U640 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U641 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U642 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U643 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U644 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U645 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U646 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U647 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U648 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U649 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U650 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U651 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U652 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U653 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U654 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U655 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U656 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U657 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U658 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U659 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U660 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U661 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U662 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U663 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U664 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U665 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U666 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U667 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U668 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U669 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U670 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U671 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U672 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U673 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U674 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U675 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U677 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U678 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U679 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U680 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U681 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U682 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U683 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U684 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U685 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U686 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U687 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U688 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U689 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U690 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U691 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U692 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U693 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U694 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U695 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U696 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U697 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U698 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U699 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U700 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U703 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U704 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U705 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U707 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U708 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U710 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U712 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U713 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U714 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U715 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U716 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U717 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U718 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U719 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U720 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U721 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U722 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U723 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U724 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U725 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U726 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U727 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U728 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U729 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U730 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U731 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U733 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U734 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U735 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U736 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U737 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U738 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U739 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U740 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U742 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U743 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U744 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U745 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U746 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U747 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U748 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U749 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U750 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U751 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U752 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U754 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U755 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U756 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U759 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U760 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U761 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U762 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U763 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U764 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U765 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U766 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U767 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U768 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U769 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U770 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U771 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U772 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U773 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U774 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U777 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U779 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U780 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U782 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U783 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U785 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U786 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U788 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U789 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U791 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U792 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U793 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U794 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U795 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U796 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U797 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U798 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U799 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U800 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U801 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U802 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U804 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U805 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U806 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U807 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U808 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U809 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U810 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U811 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U812 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U813 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U814 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U815 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U816 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U817 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U818 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U819 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U820 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U823 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U824 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U825 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U826 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U827 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U828 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U829 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U830 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U831 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U832 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U833 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U834 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U835 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U836 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U838 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U839 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U840 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U841 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U842 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U843 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U844 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U845 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U846 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U847 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U848 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U849 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U850 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U851 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U852 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U853 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U855 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U856 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U857 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U858 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U859 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U861 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U862 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U864 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U865 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U866 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U867 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U868 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U869 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U871 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U872 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U873 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U874 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U875 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U876 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U877 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U878 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U879 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U880 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U881 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U882 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U884 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U885 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U886 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U887 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U888 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U889 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U890 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U891 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U892 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U893 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U894 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U895 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U896 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U897 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U898 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U899 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U900 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U901 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U902 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U903 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U904 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U905 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U906 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U907 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U908 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U909 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U910 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U911 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U912 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U913 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U914 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U915 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U916 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U917 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U918 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U919 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U920 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U921 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U922 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U923 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U924 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U925 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U926 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U927 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U928 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U929 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U930 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U931 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U932 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U933 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U934 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U935 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U936 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U937 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U938 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U939 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U940 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U941 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U942 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U943 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U944 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U945 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U946 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U947 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U948 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U949 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U950 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U951 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U952 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U953 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U954 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U955 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U956 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U957 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U958 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U959 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U960 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U961 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U962 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U963 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U964 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U965 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U966 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U967 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U968 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U969 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U970 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U971 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U972 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U973 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U974 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U975 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U976 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U977 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U978 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U979 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U980 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U981 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U982 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U983 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U984 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U985 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U986 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U987 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U988 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U989 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U990 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U991 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U992 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U993 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U994 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U995 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U996 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U997 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U998 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U999 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1000 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1001 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1002 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1003 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1004 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1005 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1006 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1007 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1008 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1009 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1010 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1011 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1012 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1013 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1014 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1015 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1016 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1017 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1018 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1019 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1020 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1021 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1022 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1023 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1024 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1025 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1026 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1027 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1028 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1029 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1030 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1031 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1032 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1033 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1034 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1035 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1036 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1037 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1038 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1039 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1040 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1041 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1042 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1043 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1044 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1045 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1046 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1047 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1048 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1049 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1050 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1051 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1052 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1053 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1054 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1055 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1056 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1057 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1058 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1059 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1060 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1061 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1062 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1063 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1064 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1065 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1066 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1067 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1068 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1069 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1070 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1071 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1072 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1073 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1074 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1075 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1076 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1077 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1078 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1079 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1080 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1081 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1082 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1083 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1084 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1085 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1086 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1087 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1088 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1089 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1090 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1091 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1092 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1093 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1094 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1095 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1096 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1097 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1098 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1099 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1100 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1101 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1102 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1103 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1104 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1105 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1106 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1107 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1108 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1109 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1110 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1111 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1112 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1113 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1114 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1115 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1116 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1117 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1118 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1119 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1120 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1121 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1122 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1123 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1124 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1125 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1126 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1127 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1128 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1129 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1130 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1131 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1132 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1133 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1134 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1135 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1136 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1137 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1138 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1139 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1140 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1141 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1142 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1143 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1144 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1145 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1146 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1147 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1149 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1150 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1151 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1152 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1153 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1154 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1155 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1156 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1157 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1158 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1159 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1160 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1161 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1162 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1163 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1164 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1165 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1166 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1167 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1168 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1169 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1170 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1171 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1174 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1178 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1183 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1186 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1188 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1191 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1194 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1197 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1199 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1201 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1202 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1203 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1204 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1205 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1206 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1207 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1208 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1209 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1210 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1211 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1212 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1213 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1214 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1215 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1216 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1217 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1218 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1219 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1220 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1221 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1222 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1223 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1224 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1225 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1226 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1227 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1228 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1229 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1230 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1231 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1232 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1233 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1234 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1235 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1236 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1237 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1238 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1239 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1240 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1241 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1242 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1248 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1251 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1254 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1257 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1258 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1259 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1263 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1264 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1265 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1266 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1267 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1268 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1269 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1270 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1271 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1273 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1274 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1275 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1276 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1277 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1278 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1279 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1280 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1281 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1282 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1283 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1284 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1285 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1286 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1287 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1288 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1289 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1290 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1291 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1292 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1293 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1294 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1295 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1296 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1297 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1298 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1299 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1300 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1301 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1302 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1303 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1304 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1305 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1306 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1307 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1308 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1309 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1310 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1311 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1312 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1313 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1314 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1315 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1316 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1317 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1318 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1319 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1320 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1321 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1322 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1323 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1324 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1325 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1326 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1327 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1328 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1329 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1330 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1331 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1332 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1333 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1334 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1335 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1336 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1337 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1338 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1339 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1340 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1341 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1342 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1343 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1344 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1345 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1346 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1347 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1348 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1349 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1350 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1351 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1352 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1353 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1354 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1355 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1356 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1357 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1358 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1359 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1360 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1361 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1362 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1363 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1364 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1365 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1366 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1367 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1368 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1369 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1370 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1371 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1372 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1373 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1374 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1375 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1376 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1377 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1378 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1379 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1380 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1381 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1382 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1383 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1384 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1385 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1387 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1388 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1389 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1390 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1391 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1392 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1393 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1394 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1395 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1396 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1397 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1398 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1399 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1400 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1401 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1402 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1403 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1404 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1405 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1406 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1407 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1408 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1409 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1410 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1411 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1412 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1413 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1414 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1415 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1416 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1417 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1418 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1419 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1420 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1421 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1422 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1423 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1424 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1425 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1426 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1427 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1428 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1429 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1430 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1431 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1432 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1433 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1434 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1435 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1436 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1437 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1438 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1439 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1440 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1441 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1442 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1443 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1444 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1445 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1446 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1447 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1448 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1449 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1450 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1451 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1452 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1453 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1454 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1455 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1456 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1457 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1458 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1459 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1460 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1461 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1462 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1463 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1464 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1465 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1466 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1467 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1468 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1469 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1470 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1471 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1472 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1473 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1474 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1475 + NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1476 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1477 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1478 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1479 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1480 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1481 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_U1483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U15 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U17 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U18 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U19 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U20 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U22 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U23 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_0__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U12 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U15 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U17 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U18 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U19 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U20 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U21 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U23 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_1__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U11 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U12 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U15 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U19 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U20 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U21 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U23 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_2__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U3 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U4 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U5 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U6 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U8 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U9 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U10 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U12 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U13 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U15 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U17 + AOI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U18 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U19 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U20 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U21 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U22 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U23 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_U24 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_3__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U11 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U12 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U15 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U19 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U20 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U21 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U23 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_4__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U11 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U15 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U18 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U19 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U20 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U22 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U23 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_5__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U11 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U18 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U19 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U20 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U23 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_6__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U3 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U4 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U5 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U6 + BUF_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U7 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U8 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U9 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U10 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U11 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U12 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U13 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U14 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U16 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U17 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U18 + OAI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U19 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U20 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U22 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U23 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U24 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U25 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U26 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_U27 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_first_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_gpr_stage_vx_grp_wrapper_genblk2_7__vx_gpr_second_ram + rf2_32x128_wm1 USERLIB_ss_0p81v_0p81v_m40c + 8780.511719 + b, d +vx_back_end_VX_wb_U2 BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U3 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U4 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U5 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U6 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U7 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U8 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U9 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U10 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U11 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U12 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U13 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U14 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U15 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U16 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U17 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U18 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U19 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U20 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U21 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U22 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U23 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U24 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U25 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U26 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U27 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U28 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U29 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U30 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U31 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U32 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U33 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U34 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U35 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U36 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U37 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U38 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U39 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U40 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U41 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U42 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U43 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U44 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U45 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U46 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U47 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U48 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U49 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U50 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U51 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U52 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U53 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U54 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U55 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U56 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U57 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U58 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U59 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U60 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U61 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U62 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U63 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U64 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U65 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U66 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U67 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U68 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U69 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U70 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U71 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U72 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U73 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U74 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U75 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U76 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U77 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U78 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U79 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U80 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U81 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U82 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U83 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U84 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U85 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U86 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U87 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U88 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U89 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U90 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U91 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U92 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U93 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U94 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U95 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U96 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U97 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U98 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U99 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U100 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U101 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U102 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U103 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U104 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U105 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U106 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U107 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U108 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U109 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U110 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U111 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U112 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U113 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U114 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U115 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U116 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U117 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U118 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U119 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U120 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U121 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U122 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U123 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U124 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U125 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U126 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U127 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U128 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U129 INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U130 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U131 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U132 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U133 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U134 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U135 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U136 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U137 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U138 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U139 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U140 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U141 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U142 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U143 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U144 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U145 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U146 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U147 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U148 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U149 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U150 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U151 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U152 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U153 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U154 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U155 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U156 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U157 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U158 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U159 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U160 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U161 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U162 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U163 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U164 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U165 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U166 BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U167 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U168 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U169 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U170 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U171 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U172 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U173 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U174 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U175 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U176 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U177 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U178 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U179 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U180 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U181 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U182 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U183 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U184 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U185 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U186 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U187 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U188 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U189 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U190 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U191 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U192 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U193 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U194 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U195 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U196 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U197 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U198 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U199 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U200 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U201 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U202 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U203 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U204 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U205 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U206 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U207 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U208 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U209 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U210 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U211 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U212 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U213 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U214 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U215 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U216 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U217 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U218 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U219 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U220 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U221 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U222 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U223 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U224 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U225 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U226 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U227 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U228 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U229 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U230 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U231 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U232 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U233 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U234 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U235 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U236 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U237 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U238 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U239 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U240 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U241 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U242 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U243 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U244 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U245 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U246 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U247 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U248 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U249 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U250 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U251 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U252 NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U253 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U254 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U255 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U256 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U257 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U258 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U259 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U260 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U261 OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U262 BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U263 NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U264 AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U265 AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U266 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U267 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U268 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U269 NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U270 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U271 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U272 AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_back_end_VX_wb_U273 AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U274 AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U275 AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U276 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U277 AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U278 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U279 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U280 AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_back_end_VX_wb_U281 OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U282 OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_back_end_VX_wb_U283 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U284 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U285 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U286 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U287 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U288 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U289 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U290 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U291 AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U292 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U293 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U294 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U295 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U296 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U297 AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U298 NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U299 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_VX_wb_U300 NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U301 AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U302 AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_back_end_VX_wb_U303 OAI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_back_end_VX_wb_U304 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_VX_wb_U305 NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_load_store_unit_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_load_store_unit_U2 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_back_end_load_store_unit_U3 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_back_end_load_store_unit_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_load_store_unit_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_load_store_unit_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U1 + XOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U2 + XOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U3 + XOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U4 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U5 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U6 + XOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_back_end_load_store_unit_VX_lsu_addr_gen_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U10 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U11 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U12 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U13 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U14 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U15 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U16 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U17 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U18 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U19 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U20 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U21 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U22 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U23 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U24 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U25 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U26 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U27 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U28 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U29 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U30 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U31 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U32 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U33 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U34 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U35 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U36 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U37 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U38 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U39 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U40 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U41 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U42 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U43 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U44 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U45 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U46 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U47 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U48 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U49 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U50 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U51 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U52 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U53 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U54 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U55 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U56 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U57 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U58 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U59 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U60 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U61 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U62 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U63 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U64 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U65 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U66 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U67 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U68 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U69 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U70 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U71 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U72 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U73 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U74 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U75 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U76 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U77 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U78 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U79 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U80 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U81 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U82 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U83 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U84 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U85 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U86 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U87 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U88 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U89 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U90 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U91 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U92 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U93 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U94 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U95 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U96 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U97 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U98 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U99 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U100 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U101 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U102 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U103 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U104 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U105 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U106 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U107 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U108 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U109 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U110 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U111 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U112 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U113 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U114 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U115 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U116 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U117 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U118 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U119 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U120 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U121 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U122 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U123 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U124 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U125 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U126 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U127 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_back_end_load_store_unit_VX_lsu_addr_gen_U128 + ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 r +vx_front_end_U2 BUF_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_U3 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_U1 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U5 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_d_e_reg_d_e_reg_U6 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_d_e_reg_d_e_reg_U7 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U8 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U9 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_d_e_reg_d_e_reg_U10 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U11 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_d_e_reg_d_e_reg_U12 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_d_e_reg_d_e_reg_U13 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U14 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U15 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U16 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U17 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U18 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U19 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U20 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U21 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U22 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U23 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U24 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U25 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U26 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U27 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U28 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U29 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U30 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U31 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U32 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U33 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U34 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U35 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U36 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U37 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U38 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U39 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U40 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U41 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U42 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U43 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U44 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U45 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U46 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U47 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U48 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U49 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U50 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U51 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U52 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U53 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U54 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U55 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U56 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U57 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U58 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U59 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U60 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U61 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U62 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U63 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U64 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U65 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U66 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U67 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U68 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U69 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U70 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U71 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U72 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U73 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U74 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U75 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U76 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U77 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U78 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U79 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U80 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U81 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U82 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U83 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U84 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U85 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U86 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U87 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U88 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U89 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U90 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U91 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U92 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U93 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U94 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U95 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U96 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U97 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U98 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U99 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U100 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U102 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U105 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U106 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U107 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U108 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U109 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U110 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U111 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U112 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U113 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U114 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U115 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U116 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U117 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U118 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U119 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U120 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U121 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U122 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U123 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U124 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U125 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U126 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U127 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U128 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U129 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U130 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U131 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U132 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U133 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U134 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U135 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U136 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U137 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U138 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U139 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U140 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U141 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U142 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U143 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U144 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U145 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U146 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U147 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U148 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U149 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U150 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U151 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U152 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U153 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U154 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U155 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U156 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U157 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U158 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U159 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U160 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U161 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U162 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U163 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U164 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U165 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U166 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U167 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U168 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U169 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U170 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U171 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U172 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U173 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U174 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U175 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U176 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U177 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U178 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U179 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U180 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U181 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U182 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U183 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U184 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U185 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U186 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U187 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U188 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U189 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U190 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U191 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U192 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U193 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U194 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U195 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U196 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U197 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U198 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U199 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U200 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U201 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U202 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U203 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U204 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U205 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U206 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U207 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U208 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U209 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U210 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U211 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U212 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U213 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U214 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U215 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U216 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U217 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U218 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U219 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U220 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U223 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U224 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_d_e_reg_d_e_reg_U225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U227 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U228 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U229 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U230 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U231 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U232 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U236 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U238 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U239 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U240 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U241 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U243 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U245 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U246 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U247 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U248 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U249 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U250 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U251 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U252 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U253 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U254 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U255 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U256 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U257 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U258 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U259 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U260 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U261 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U262 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U263 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U264 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U265 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U266 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U267 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U268 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U269 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U270 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U271 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U272 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U273 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U274 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U275 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U276 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U277 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_d_e_reg_d_e_reg_U278 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U279 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U280 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U281 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U282 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U283 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U284 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U285 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U286 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U287 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U288 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U289 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U290 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U292 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U293 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U295 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U296 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U297 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U298 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U300 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U301 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U302 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U303 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U304 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U305 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U317 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U319 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U321 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U322 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U323 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U325 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U327 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U328 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U329 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U330 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U331 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U342 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U344 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U350 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U357 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U358 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U360 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U361 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U362 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U363 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U364 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U366 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U367 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U368 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U369 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U370 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U371 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U372 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U373 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U374 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U376 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U377 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U380 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U381 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U382 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U386 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U388 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U389 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U390 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U391 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U392 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U393 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U394 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U395 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U396 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U397 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U398 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U399 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U400 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U401 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U402 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U403 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U405 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U406 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U407 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U408 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U409 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U410 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U411 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U412 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U413 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U414 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U415 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U416 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U417 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U418 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U419 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U420 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U421 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U422 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U423 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U424 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U425 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U426 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U427 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U428 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U429 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U430 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U431 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U432 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U433 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U434 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U435 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U436 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U437 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U438 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U439 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U440 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U441 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U442 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U443 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U444 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U445 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U446 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U447 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U448 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U449 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U450 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U451 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U452 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U453 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U454 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U455 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U456 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U457 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U458 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U459 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U460 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U461 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U462 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U463 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U464 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U465 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U466 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U467 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U468 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U469 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U470 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U471 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U472 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U473 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U474 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U475 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U476 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U477 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U478 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U479 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U480 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U481 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U482 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U483 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U484 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U485 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U486 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U487 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U488 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U489 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U490 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U491 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U492 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U493 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U494 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U495 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U496 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U501 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U505 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U506 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U513 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U517 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U518 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U519 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U522 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U526 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U527 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U528 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U529 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U530 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U532 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U533 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U534 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U535 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U536 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U537 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U538 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U540 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U542 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U543 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U544 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U545 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U547 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U548 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U549 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U550 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U552 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U554 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U555 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U556 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U557 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U558 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U559 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U560 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U561 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U562 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U563 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U564 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U565 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U566 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U567 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U568 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U569 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U570 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U571 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U572 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U573 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U574 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U575 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U576 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U577 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U578 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U579 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U580 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U581 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U582 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U583 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U584 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U585 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U586 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U587 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U588 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U589 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U590 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U597 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U604 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U605 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U609 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U610 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U611 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U612 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U614 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U615 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U617 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U618 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U619 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U620 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U626 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U627 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U628 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U630 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U631 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U632 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U633 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_U635 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_32_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_33_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_34_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_35_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_36_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_37_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_38_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_39_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_40_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_41_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_42_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_43_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_44_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_45_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_46_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_47_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_48_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_49_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_50_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_51_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_52_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_53_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_54_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_55_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_56_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_57_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_58_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_59_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_60_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_61_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_62_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_63_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_64_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_65_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_66_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_67_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_68_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_69_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_70_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_71_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_72_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_73_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_74_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_75_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_76_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_77_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_78_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_79_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_80_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_81_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_82_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_83_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_84_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_85_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_86_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_87_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_88_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_89_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_90_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_91_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_92_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_93_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_94_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_95_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_96_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_97_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_98_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_99_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_100_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_101_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_102_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_103_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_104_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_105_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_106_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_107_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_108_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_109_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_110_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_111_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_112_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_113_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_114_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_115_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_116_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_117_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_118_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_119_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_120_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_121_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_122_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_123_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_124_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_125_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_126_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_127_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_128_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_129_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_130_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_131_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_132_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_133_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_134_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_135_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_136_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_137_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_138_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_139_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_140_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_141_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_142_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_143_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_144_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_145_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_146_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_147_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_148_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_149_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_150_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_151_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_152_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_153_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_154_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_155_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_156_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_157_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_158_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_159_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_160_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_161_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_162_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_163_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_164_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_165_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_166_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_167_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_168_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_169_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_170_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_171_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_172_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_173_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_174_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_175_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_176_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_177_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_178_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_179_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_180_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_181_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_182_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_183_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_184_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_185_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_186_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_187_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_188_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_189_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_190_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_191_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_224_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_225_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_226_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_227_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_228_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_229_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_230_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_231_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_232_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_233_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_234_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_235_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_236_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_237_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_238_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_d_e_reg_d_e_reg_value_reg_239_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_decode_U3 NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U4 INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U5 AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U6 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U7 NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_decode_U8 INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U9 NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U10 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U12 + AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U13 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U14 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U17 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U18 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U19 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U20 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U21 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U22 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U23 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U24 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U26 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U27 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U28 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U29 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U30 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U31 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U32 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U33 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U34 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U35 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U36 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U37 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U38 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U39 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U40 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U41 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U42 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U43 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U44 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U45 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U46 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U47 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U48 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U49 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U50 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U51 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U52 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U53 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U54 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U55 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U56 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U57 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U58 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U59 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U60 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U61 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U62 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U63 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U64 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U65 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U66 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U67 + AND3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U68 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U69 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U70 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U71 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U72 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U73 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U74 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U75 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U76 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U77 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U78 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U79 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U80 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U81 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U82 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U83 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U84 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U85 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U86 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U87 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U88 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_decode_U89 + AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_decode_U90 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U91 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U92 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U93 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U94 + NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U95 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U96 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U97 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U98 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U99 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U100 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U101 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U102 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U103 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U104 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U105 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U106 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U107 + AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U108 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U109 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U110 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U111 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U112 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U113 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U114 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_decode_U115 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U116 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U117 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U118 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U119 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U120 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U121 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U122 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U123 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U124 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U125 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U126 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U127 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U128 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U129 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U130 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U131 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U132 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U133 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U134 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U135 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U136 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U137 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U138 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U139 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U140 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U141 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U142 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U143 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U144 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U145 + OAI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U146 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U147 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U148 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U149 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U150 + OA21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U151 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U152 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U153 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U154 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U155 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U156 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U157 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U158 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U159 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U160 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U161 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U162 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U163 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U164 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U165 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U166 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U167 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U168 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U169 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U170 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U171 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U172 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U173 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U174 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U175 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U176 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U177 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U178 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U179 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_decode_U180 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U181 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U182 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U183 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U184 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U185 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U186 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U187 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U188 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U189 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U190 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U191 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U192 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U193 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U194 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U195 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U196 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U197 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U198 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U199 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U200 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U201 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U202 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U203 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U204 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U205 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U206 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U207 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U208 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_decode_U209 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U210 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U211 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U212 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U213 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U214 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U215 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U216 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U217 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U218 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U219 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U220 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U221 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U222 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U223 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U224 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_decode_U227 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U228 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U229 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U230 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U231 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U232 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U233 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U234 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U235 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U236 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U237 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U238 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U239 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U240 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U241 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U242 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U243 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U244 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U245 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U246 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U247 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_decode_U248 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U250 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U252 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U273 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U274 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U275 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U276 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U277 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_U278 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_decode_add_x_1_U2 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U3 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U4 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U5 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U6 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U7 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U8 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U9 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U10 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U11 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U12 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U13 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U14 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U15 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U16 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U17 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U18 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U19 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U20 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U21 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U22 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U23 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U24 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U25 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U26 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U27 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U28 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_decode_add_x_1_U29 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_f_d_reg_U2 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_U3 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U3 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U4 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U5 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U6 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U7 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U8 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U9 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_f_d_reg_f_d_reg_U10 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U11 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U12 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U13 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U14 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U15 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U16 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U17 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U18 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U19 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U20 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U21 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U22 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U23 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U24 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U25 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U26 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U27 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U28 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U29 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U30 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U31 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U32 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U33 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U34 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_f_d_reg_f_d_reg_U35 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U36 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U37 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U38 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U39 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U40 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_f_d_reg_f_d_reg_U41 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_f_d_reg_f_d_reg_U42 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_f_d_reg_f_d_reg_U43 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_f_d_reg_f_d_reg_U44 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U45 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_f_d_reg_f_d_reg_U46 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_f_d_reg_f_d_reg_U47 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U48 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U49 + MX2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U50 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U51 + MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_f_d_reg_f_d_reg_U52 + MX2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U53 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U54 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U55 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U56 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U57 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_f_d_reg_f_d_reg_U58 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_f_d_reg_f_d_reg_U59 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_f_d_reg_f_d_reg_U60 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_f_d_reg_f_d_reg_U61 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U62 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U63 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_f_d_reg_f_d_reg_U64 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U65 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U66 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U67 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U68 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U69 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U70 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U71 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U72 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U73 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U74 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U75 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_f_d_reg_f_d_reg_U76 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U77 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U78 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U79 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U80 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U81 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U82 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U83 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U84 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U85 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_f_d_reg_f_d_reg_U86 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_f_d_reg_f_d_reg_U87 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_f_d_reg_f_d_reg_U88 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_f_d_reg_f_d_reg_U89 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_f_d_reg_f_d_reg_U90 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_f_d_reg_f_d_reg_U91 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U92 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U93 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U94 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U95 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U96 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U97 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U98 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U99 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U100 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U101 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U102 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U103 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U104 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U105 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U106 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U107 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U108 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U109 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U110 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U112 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U114 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U115 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U116 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U117 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U118 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U119 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U120 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U121 + MX2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U122 + MXT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_f_d_reg_f_d_reg_U123 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U124 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U125 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U126 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U127 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U128 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U129 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U130 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U131 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U132 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U133 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U134 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U135 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U136 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U137 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U138 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U139 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U140 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U141 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U142 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U143 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U144 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U145 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U146 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U147 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U148 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U149 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U150 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U151 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U152 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U153 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U154 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U155 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U156 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U157 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U158 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U159 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_f_d_reg_f_d_reg_U160 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U161 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U162 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U163 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U164 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U165 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_f_d_reg_f_d_reg_U166 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U167 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U168 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U170 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U171 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U172 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U173 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U174 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U175 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U176 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U177 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U178 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U179 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U180 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U181 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U182 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U183 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U184 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U185 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U186 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U187 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U188 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U189 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_U190 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_32_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_33_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_34_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_35_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_36_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_37_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_38_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_39_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_40_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_41_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_42_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_43_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_44_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_45_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_46_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_47_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_48_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_49_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_50_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_51_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_52_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_53_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_54_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_55_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_56_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_57_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_58_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_59_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_60_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_61_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_62_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_63_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_64_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_65_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_66_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_67_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_68_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_69_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_f_d_reg_f_d_reg_value_reg_70_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_U2 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U3 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U4 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U5 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U6 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U7 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U8 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U9 INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_U10 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U11 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U12 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U13 AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_U14 AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_U15 INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_U16 BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_U17 OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_front_end_vx_fetch_U18 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U19 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U20 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U21 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U22 AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_U23 OR4_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 +vx_front_end_vx_fetch_U24 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U25 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U26 AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_U27 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U28 TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_U29 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U30 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U31 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U32 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U33 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U34 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U35 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U36 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U37 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U38 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_U39 AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U3 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U4 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U5 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U6 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U7 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U8 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U9 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U10 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U11 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U12 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U13 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U14 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U15 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U16 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U17 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U18 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U19 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U20 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U21 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U22 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U23 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U24 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U25 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U26 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U27 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U28 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U29 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U30 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U31 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U32 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U33 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U34 + NAND3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U35 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U36 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U37 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U38 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U39 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U40 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U41 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U42 + NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U43 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U44 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U45 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U46 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U47 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U48 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U49 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U50 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U51 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U52 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U53 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U54 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U55 + OR2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U56 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U57 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U58 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U59 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U60 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U61 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U62 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U63 + AOI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U64 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U65 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U66 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U67 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U68 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U69 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U70 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U71 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U72 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U73 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U74 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U75 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U76 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U77 + AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U78 + OAI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U79 + MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U80 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U81 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U82 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U83 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U84 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U85 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U86 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U87 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U88 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U89 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U90 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U91 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U92 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U93 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U94 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U95 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U96 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U97 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U98 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U99 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U100 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U101 + OR2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U102 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U103 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U104 + OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U105 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U106 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U107 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U108 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U109 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U110 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U111 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U112 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U113 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U114 + NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U115 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U116 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U117 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U118 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U119 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U120 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U121 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U122 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U123 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U124 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U125 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U126 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U127 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U128 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U129 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U130 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U131 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U132 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U133 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U134 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U135 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U136 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U137 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U138 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U139 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U140 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U141 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U142 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U143 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U144 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U145 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U146 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U147 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U148 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U149 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U150 + NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U151 + NAND3_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U152 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U153 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U154 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U155 + INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U156 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U157 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U158 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U159 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U160 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U161 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U162 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U163 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U164 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U165 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U166 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U167 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U168 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U169 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U170 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U171 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U172 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U173 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U174 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U175 + NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U176 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U177 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U178 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U179 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U180 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U181 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U182 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U183 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U184 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U185 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U186 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U187 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U188 + BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U189 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U190 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U191 + OA21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U192 + OAI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U193 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U194 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U195 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U196 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U197 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U198 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U199 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U200 + NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U201 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U202 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U203 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U204 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U205 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U206 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U207 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U208 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U209 + OR2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U210 + OR2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U211 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U212 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U213 + NOR3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U214 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U215 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U216 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U217 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U218 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U219 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U220 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U221 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U222 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U223 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U224 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U225 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U226 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U227 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U228 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U229 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U230 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U231 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U232 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U233 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U234 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U235 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U236 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U237 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U238 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U239 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U240 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U241 + NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U242 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U243 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U244 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U245 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U246 + BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U247 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U248 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U249 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U250 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U251 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U252 + OAI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U253 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U254 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U255 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U256 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U257 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U258 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U259 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U260 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U261 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U262 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U263 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U264 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U265 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U266 + NOR2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U267 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U268 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U269 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U270 + OAI22BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U271 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U272 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U273 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U274 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U275 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U276 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U277 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U278 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U279 + AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U280 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U281 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U282 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U283 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U284 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U285 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U286 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U287 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U288 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U289 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U290 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U291 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U292 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U293 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U295 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U296 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U297 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U298 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U299 + OAI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U300 + BUF_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U301 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U302 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U303 + BUF_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U304 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U305 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U306 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U307 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U308 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U309 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U310 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U311 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U312 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U313 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U314 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U315 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U316 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U317 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U318 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U319 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U320 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U321 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U322 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U323 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U324 + OAI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U325 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U326 + NOR3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U327 + AOI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U328 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U329 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U330 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U331 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U332 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U333 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U334 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U336 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U337 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U338 + AND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U339 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U340 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U341 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U342 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U343 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U344 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U345 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U346 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U347 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U348 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U349 + AOI21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U350 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U351 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U352 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U353 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U354 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U355 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U356 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U357 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U358 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U359 + AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U360 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U361 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U362 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U363 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U364 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U365 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U366 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U367 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U368 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U369 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U370 + OAI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U371 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U372 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U373 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U374 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U375 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U376 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U377 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U378 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U379 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U380 + OAI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U381 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U382 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U383 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U384 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U385 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U386 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U387 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U388 + AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U389 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U390 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U391 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U392 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U393 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U394 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U395 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U396 + OAI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U397 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U398 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U399 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U400 + BUFH_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U401 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U402 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U403 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U404 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U405 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U406 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U407 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U408 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U409 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U410 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U411 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U412 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U413 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U414 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U415 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U416 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U417 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U418 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U419 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U420 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U421 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U422 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U423 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U424 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U425 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U426 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U427 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U428 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U429 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U430 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U431 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U432 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U433 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U434 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U435 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U436 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U437 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U438 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U439 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U440 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U441 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U442 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U443 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U444 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U445 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U446 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U447 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U448 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U449 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U450 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U451 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U452 + AOI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U453 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U454 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U455 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U456 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U457 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U458 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U459 + OR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 +vx_front_end_vx_fetch_warp_scheduler_U460 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U461 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U462 + OAI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U463 + AOI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U464 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U465 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U466 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U467 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U468 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U469 + INV_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U470 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U471 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U472 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U473 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U474 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U475 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U476 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U477 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U478 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U479 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U480 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U481 + OAI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U482 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U483 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U484 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U485 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U486 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U487 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U488 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U489 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U490 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U491 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U492 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U493 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U494 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U495 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U496 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U497 + INV_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U498 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U499 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U500 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U501 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U502 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U503 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U504 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U505 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U506 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U507 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U508 + NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U509 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U510 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U511 + NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U512 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U513 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U514 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U515 + AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U516 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U517 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U518 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U519 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U520 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U521 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U522 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U523 + OR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U524 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U525 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U526 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U527 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U528 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U529 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U530 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U531 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U532 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U533 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U534 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U535 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U536 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U537 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U538 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U539 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U540 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U541 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U542 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U543 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U544 + BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U545 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U546 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U547 + NOR2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U548 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U549 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U550 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U551 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U552 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U553 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U554 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U555 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U556 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U557 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U558 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U559 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U560 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U561 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U562 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U563 + INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U564 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U565 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U566 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U567 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U568 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U569 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U570 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U571 + NOR2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U572 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U573 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U574 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U575 + BUFH_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U576 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U577 + BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U578 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U579 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U580 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U581 + BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U582 + BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U583 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U584 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U585 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U586 + NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U587 + NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U588 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U589 + BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U590 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U593 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U597 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U598 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U599 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U600 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U601 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U602 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U603 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U604 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U605 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U606 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U607 + BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U608 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U609 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U610 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U611 + BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U612 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U614 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U615 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U616 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U617 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U618 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U619 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U620 + INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U621 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U622 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U623 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U625 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U626 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U627 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U628 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U629 + OR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 +vx_front_end_vx_fetch_warp_scheduler_U630 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U631 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U632 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U633 + NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U634 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U635 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U636 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U637 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U638 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U639 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U640 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U641 + NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U642 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U643 + BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U644 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U645 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U646 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U647 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U648 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U649 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U650 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U651 + INV_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U652 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U653 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U654 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U655 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U656 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U657 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U658 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U659 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U660 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U661 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U662 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U663 + OAI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U664 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U665 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U666 + OAI31_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U667 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U668 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U669 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U670 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U671 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U672 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U673 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U674 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U675 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U676 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U677 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U678 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U679 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U680 + AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U681 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U682 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U683 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U684 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U685 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U686 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U687 + NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U688 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U689 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U690 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U691 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U692 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U693 + MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U694 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U695 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U696 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U697 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U698 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U699 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U700 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U701 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U702 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U703 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U704 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U705 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U706 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U707 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U708 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U709 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U710 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U711 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U712 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U713 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U714 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U715 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U716 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U717 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U718 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U719 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U720 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U721 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U722 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U723 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U724 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U725 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U726 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U727 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U728 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U729 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U730 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U731 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U732 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U733 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U734 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U735 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U736 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U737 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U738 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U739 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U740 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U741 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U742 + OAI21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U743 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U744 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U745 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U746 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U747 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U748 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U749 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U750 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U751 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U752 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U753 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U754 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U755 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U756 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U757 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U758 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U759 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U760 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U761 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U762 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U763 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U764 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U765 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U766 + AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U767 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U768 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U769 + NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U770 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U771 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U772 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U773 + AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U774 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U775 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U776 + NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U777 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U778 + OA1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U779 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U780 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U781 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U782 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U783 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U784 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U785 + OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U786 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U787 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U788 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U789 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U790 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U791 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U792 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U793 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U794 + AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U795 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U796 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U797 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U798 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U799 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U800 + BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U801 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U802 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U803 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U804 + AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U805 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U806 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U807 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U808 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U809 + NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U810 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U811 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U812 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U813 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U814 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U815 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U816 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U817 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U818 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U819 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U820 + OAI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U821 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U822 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U823 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U824 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U825 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U826 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U827 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U828 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U829 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U830 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U831 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U832 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U833 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U834 + OA21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U835 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U836 + NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U837 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U838 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U839 + NAND3_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U840 + NAND3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U841 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U842 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U843 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U844 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U845 + INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U846 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U847 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U848 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U849 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U850 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U851 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U852 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U853 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U854 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U855 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U856 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U857 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U858 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U859 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U860 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U861 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U862 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U863 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U864 + NOR3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U865 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U866 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U867 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U868 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U869 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U870 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U871 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U872 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U873 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U874 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U875 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U876 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U877 + INV_X9M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U878 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U879 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U880 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U881 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U882 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U883 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U884 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U885 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U886 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U887 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U888 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U889 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U890 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U891 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U892 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U893 + NOR3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U894 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U895 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U896 + NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U897 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U898 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U899 + NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U900 + NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U901 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U902 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U903 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U904 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U905 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U906 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U907 + NAND3B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_front_end_vx_fetch_warp_scheduler_U908 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U909 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U910 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U911 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U912 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U913 + BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U914 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U915 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U916 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U917 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U918 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U919 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U920 + AO22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 +vx_front_end_vx_fetch_warp_scheduler_U921 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U922 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U923 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U924 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U925 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U926 + AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U927 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U928 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U929 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U930 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U931 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U932 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U933 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U934 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U935 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U936 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U937 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U938 + NAND3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U939 + AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U940 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U941 + AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U942 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U943 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U944 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U945 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U946 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U947 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U948 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U949 + NAND3XXB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_front_end_vx_fetch_warp_scheduler_U950 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U951 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U952 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U953 + AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U954 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U955 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U956 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U957 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U958 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U959 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U960 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U961 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U962 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U963 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U964 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U965 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U966 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U967 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U968 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U969 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U970 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U971 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U972 + NOR2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U973 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U974 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U975 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U976 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U977 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U978 + AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U979 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U980 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U981 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U982 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U983 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U984 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U985 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U986 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U987 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U988 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U989 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U990 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U991 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U992 + AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U993 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U994 + AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U995 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U996 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U997 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U998 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U999 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1000 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1001 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1002 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1003 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1004 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1005 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1006 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1007 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1008 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1009 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1010 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1011 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1012 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1013 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1014 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1015 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1016 + NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1017 + AOI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1018 + NOR3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1019 + BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1020 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1021 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1022 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1023 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1024 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1025 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1026 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1027 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1028 + BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1029 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1030 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1031 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1032 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1033 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1034 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1035 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1036 + AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1037 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1038 + NOR2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1039 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1040 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1041 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1042 + ADDH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1043 + AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1044 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1045 + ADDH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1046 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U1047 + OAI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1048 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1049 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1050 + NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1051 + ADDH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1052 + ADDH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1053 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1054 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1055 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1056 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1057 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1058 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1059 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1060 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1061 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1062 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1063 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1064 + ADDH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1065 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1066 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1067 + OAI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_front_end_vx_fetch_warp_scheduler_U1068 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1069 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U1070 + BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1071 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1072 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1073 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1074 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1075 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1076 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U1077 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1078 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1079 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1080 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1081 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1082 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1083 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1084 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1085 + NOR3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1086 + NOR2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1087 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1088 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1089 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1090 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1091 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1092 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1093 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1094 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1095 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1096 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1097 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1098 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1099 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1100 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U1101 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1102 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1103 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1104 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1105 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1106 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1107 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1108 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1109 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U1110 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1111 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1112 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1113 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1114 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1115 + NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1116 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1117 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1118 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1119 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1120 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1121 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1122 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1123 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1124 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1125 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1126 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1127 + AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1128 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1129 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1130 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1131 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1132 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1133 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1134 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1135 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1136 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1137 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1138 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1139 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1140 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1141 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1142 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1143 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1144 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1145 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1146 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1147 + OA21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1148 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1149 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1150 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1151 + NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1152 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1153 + OR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1154 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1155 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1156 + OA21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1157 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1158 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1159 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1160 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1161 + OR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1162 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1163 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1164 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1165 + NAND3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1166 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1167 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1168 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1169 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1170 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1171 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1172 + AO21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1173 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1174 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1175 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1176 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1177 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1178 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1179 + OAI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1180 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1181 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1182 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1183 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1184 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1185 + OA21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1186 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1187 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1188 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1189 + NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1190 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1191 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1192 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1193 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1194 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1195 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1196 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1197 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1198 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1199 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1200 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1201 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1202 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1203 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1204 + OAI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1205 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1206 + NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1207 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1208 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1209 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1210 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1211 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1212 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1213 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1214 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1215 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1216 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1217 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1218 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1219 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1220 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1221 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1222 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1223 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1224 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1225 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1226 + NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1227 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1228 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1229 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1230 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1231 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1232 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1233 + AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 +vx_front_end_vx_fetch_warp_scheduler_U1234 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1235 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1236 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1237 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1238 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1239 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1240 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1241 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1242 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1243 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1244 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1245 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1246 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1247 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1248 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1249 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1250 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1251 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1252 + NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1253 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1254 + NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1255 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1256 + OAI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1257 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1258 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1259 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1260 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1261 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1262 + AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1263 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1264 + AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1265 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1266 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1267 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1268 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1269 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1270 + OAI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1271 + NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1272 + NOR2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1273 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1274 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1275 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1276 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1277 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1278 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1279 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1280 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1281 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1282 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1283 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1284 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1285 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1286 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1287 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1288 + NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1289 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1290 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1291 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1292 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1293 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1294 + NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1295 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1296 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1297 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1298 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1299 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1300 + NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1301 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1302 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1303 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1304 + BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1305 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1306 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1308 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1309 + OAI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1310 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1311 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1312 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1313 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1316 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1317 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1318 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1319 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U1320 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1321 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1322 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1323 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1324 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1325 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1326 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1327 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1328 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1329 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1330 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1331 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1332 + NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1333 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1334 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1335 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1336 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1337 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1338 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1339 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1340 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1341 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1342 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1343 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1344 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1345 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1346 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1347 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1348 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1349 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1350 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1351 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1353 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1354 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1355 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1356 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1357 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1358 + BUF_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1359 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1360 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1361 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1362 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1363 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1364 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1365 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1366 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1367 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1368 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1369 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1370 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1371 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1372 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1373 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1374 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1375 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1376 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1377 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1378 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1379 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1380 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1381 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1382 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1383 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1384 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1385 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1386 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1387 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1388 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1389 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1390 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1391 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1392 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1393 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1394 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1395 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1396 + NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1397 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1398 + INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1399 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1400 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1401 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1402 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1403 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1404 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1405 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1406 + AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1407 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1408 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1409 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1410 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1411 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1412 + AND4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1413 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1414 + NAND3XXB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1415 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1416 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1417 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1418 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1419 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1420 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1421 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1422 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1423 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1424 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1425 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1426 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1427 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1428 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1429 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1430 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1431 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1432 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1433 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1434 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1435 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1436 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1437 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1438 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1439 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1440 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1441 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1442 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1443 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1444 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1445 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1446 + NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1447 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1448 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1449 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1450 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1451 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1452 + AO21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U1453 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1454 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1455 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1456 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1457 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1458 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1459 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U1460 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1461 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1462 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1463 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1464 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1465 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1466 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1467 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1468 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1469 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1470 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1471 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1472 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1473 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1474 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1475 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1476 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1477 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1478 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1479 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1480 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1481 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1482 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1483 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1484 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1485 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1486 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1487 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1488 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1489 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1490 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1491 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1492 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1493 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1494 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1495 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1496 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1497 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1498 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1499 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1500 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1501 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1502 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1503 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1504 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1505 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1506 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1507 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1508 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1509 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1510 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1511 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1512 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1513 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1514 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1515 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1516 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1517 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1518 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1519 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1520 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1521 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1522 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1523 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1524 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1525 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1526 + OAI211_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1527 + NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1528 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1529 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1530 + AND3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1531 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1532 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1533 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1534 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1535 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1536 + NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1537 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1538 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1539 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1540 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1541 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1542 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1543 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1544 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1545 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1546 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1547 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1548 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1549 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1550 + OA21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1551 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1552 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1553 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1554 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1555 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1556 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1557 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1558 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1559 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1560 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1561 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1562 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1563 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1564 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1565 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1566 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1567 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1568 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1569 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1570 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1571 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1572 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1573 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1574 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1575 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1576 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1577 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1578 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1579 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1580 + NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1581 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1582 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1583 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1584 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1585 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1586 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1587 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1588 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1589 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1590 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1591 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1592 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1593 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1594 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1595 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1596 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1597 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1598 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1599 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1600 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1601 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1602 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1603 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1604 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1605 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1606 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1607 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1608 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1609 + NOR2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1610 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1611 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1612 + NOR2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1613 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1614 + NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1615 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1616 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1617 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1618 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1619 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1620 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1621 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1622 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1623 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1624 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U1625 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1626 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1627 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1628 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1629 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1630 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1631 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1632 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1633 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1634 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1635 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1636 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1637 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1638 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1639 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1640 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1641 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1642 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1643 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1644 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1645 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1646 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1647 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1648 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1649 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1650 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1651 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1652 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1653 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1654 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1655 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1656 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1657 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1658 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1659 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U1660 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1661 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1662 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1663 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1664 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1665 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1666 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1667 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1668 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1669 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1670 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1671 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1672 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1673 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1674 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1675 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1676 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1677 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1678 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1679 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1680 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1681 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1682 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1683 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1684 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1685 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1686 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1687 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1688 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1689 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1690 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1691 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1692 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1693 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1694 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1695 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1696 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1697 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1698 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1699 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1700 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1701 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1702 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1703 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1704 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1705 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1706 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1707 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1708 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1709 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1710 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1711 + XOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1712 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1713 + NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1714 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1715 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1716 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1717 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1718 + XNOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U1719 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1720 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1721 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1722 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1723 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1724 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1725 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1726 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1727 + OAI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1728 + NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1729 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1730 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1731 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1732 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1733 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1734 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1735 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1736 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1737 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1738 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1739 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1740 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1741 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1742 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1743 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1744 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1745 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1746 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1747 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1748 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1749 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1750 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1751 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1752 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1753 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1754 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1755 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1756 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1757 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1758 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1759 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1760 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1761 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1762 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1763 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1764 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1765 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1766 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1767 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1768 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1769 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1770 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1771 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1772 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1773 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1774 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1775 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1776 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1777 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1778 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1779 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1780 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1781 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1782 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1783 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1784 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1785 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1786 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1787 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1788 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1789 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1790 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1791 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1792 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1793 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1794 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1795 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1796 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1797 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1798 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1799 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1800 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1801 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1802 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1803 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1804 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1805 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1806 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1807 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1808 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1809 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1810 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1811 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1812 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1813 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1814 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1815 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1816 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1817 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1818 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1819 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1820 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1821 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1822 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1823 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1824 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1825 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1826 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1827 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1828 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1829 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1830 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1831 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1832 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1833 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1834 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1835 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1836 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1837 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1838 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1839 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1840 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1841 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1842 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1843 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1844 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1845 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1846 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1847 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1848 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1849 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1850 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1851 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1852 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1853 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1854 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1855 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1856 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1857 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1858 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1859 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1860 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1861 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1862 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1863 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1864 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1865 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1866 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1867 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1868 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1869 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1870 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1871 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1872 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1873 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1874 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1875 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1876 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1877 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1878 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1879 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1880 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1881 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1882 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1883 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1884 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1885 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1886 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1887 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1888 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1889 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1890 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1891 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1892 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1893 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1894 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1895 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1896 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1897 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1898 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1899 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1900 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1901 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1902 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1903 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1904 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1905 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1906 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1907 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1908 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1909 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1910 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1911 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1912 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1913 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1914 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1915 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1916 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1917 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1918 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1919 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1920 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1921 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1922 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1923 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1924 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1925 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1926 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1927 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1928 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1929 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1930 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1931 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1932 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1933 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1934 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1935 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1936 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1937 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1938 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1939 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1940 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1941 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1942 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1943 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1944 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1945 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1946 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1947 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1948 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U1949 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1950 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1951 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U1952 + NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1953 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1954 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1955 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1956 + NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1957 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U1958 + AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1959 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1960 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1961 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1962 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1963 + NAND3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1964 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1965 + INV_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U1966 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1967 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1968 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1969 + ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 r +vx_front_end_vx_fetch_warp_scheduler_U1970 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1971 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1972 + NOR3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U1973 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1974 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U1975 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1976 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U1977 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1978 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1979 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1980 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1981 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1982 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1983 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U1984 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U1985 + NOR3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1986 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1987 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1988 + BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 +vx_front_end_vx_fetch_warp_scheduler_U1989 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U1990 + AOI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1991 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1992 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U1993 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U1994 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1995 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U1996 + OR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 +vx_front_end_vx_fetch_warp_scheduler_U1997 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U1998 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U1999 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2000 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2001 + NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2002 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2003 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2004 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2005 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2006 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2007 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2008 + NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2009 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2010 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2011 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2012 + NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2013 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2014 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2015 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2016 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2017 + NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2018 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2019 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2020 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2021 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2022 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2023 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2024 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2025 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2026 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2027 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U2028 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2029 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2030 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2031 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2032 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2033 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2034 + OAI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2035 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2036 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2037 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2038 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2039 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2040 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2041 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2042 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2043 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2044 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2045 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2046 + NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2047 + NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2048 + NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2049 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2050 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2051 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2052 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2053 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2054 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2055 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2056 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2057 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2058 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2059 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2060 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2061 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2062 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2063 + AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2064 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2065 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2066 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2067 + AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 +vx_front_end_vx_fetch_warp_scheduler_U2068 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2069 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2070 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2071 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2072 + OR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2073 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2074 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2075 + AOI2XB1_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 +vx_front_end_vx_fetch_warp_scheduler_U2076 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2077 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2078 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2079 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2080 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2081 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2082 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2083 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2084 + OAI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2085 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2086 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2087 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2088 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2089 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2090 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2091 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2092 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2093 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2094 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2095 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2096 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2097 + OAI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2098 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U2099 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2100 + NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2101 + AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2102 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2103 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2104 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2105 + AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2106 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2107 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2108 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2109 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2110 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2111 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2112 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2113 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2114 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2115 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2116 + AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2117 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2118 + AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2119 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2120 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2121 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2122 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2123 + AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2124 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2125 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2126 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2127 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2128 + NAND3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2129 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2130 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2131 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2132 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2133 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2134 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2135 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2136 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2137 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2138 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2139 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2140 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2141 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2142 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2143 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2144 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2145 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2146 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2147 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2148 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2149 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2150 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2151 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2152 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2153 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2154 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2155 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2156 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2157 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2158 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2159 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2160 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2161 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2162 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2163 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2164 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2165 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2166 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2167 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2168 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2169 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2170 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2171 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2172 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2173 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2174 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2175 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2176 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2177 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2178 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2179 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2180 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2181 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2182 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2183 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2184 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2185 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2186 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2187 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2188 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2189 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2190 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2191 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2192 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2193 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2194 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2195 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2196 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2197 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2198 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2199 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2200 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2201 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2202 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2203 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2204 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2205 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2206 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2207 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2208 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2209 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2210 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2211 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2212 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2213 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2214 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2215 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2216 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2217 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2218 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2219 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2220 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2221 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2222 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2223 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2224 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2225 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2226 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2227 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2228 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2229 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2230 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2231 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2232 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2233 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2234 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2235 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2236 + NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2237 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2238 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2239 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2240 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2241 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2242 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2243 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2244 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2245 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2246 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2247 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2248 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2249 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2250 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2251 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2252 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2253 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2254 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2255 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2256 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2257 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2258 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2259 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2260 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2261 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2262 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2263 + AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2264 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2265 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2266 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2267 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2268 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2269 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2270 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2271 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2272 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2273 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2274 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2275 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2276 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2277 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2278 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2279 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2280 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2281 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2282 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2283 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2284 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2285 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2286 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2287 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2288 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2289 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2290 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2291 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2292 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2293 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2294 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2295 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2296 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2297 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2298 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2299 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2300 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2301 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2302 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2303 + AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2304 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2305 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2306 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2307 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2308 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2309 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2310 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2311 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2312 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2313 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2314 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2315 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2316 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2317 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2318 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2319 + AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2320 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2321 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2322 + OAI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2323 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2324 + OAI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2325 + NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2326 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2327 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2328 + OAI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2329 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2330 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2331 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2332 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2333 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2334 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2335 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2336 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2337 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2338 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2339 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2340 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2341 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2342 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2343 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2344 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2345 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2346 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2347 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2348 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2349 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2350 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2351 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2352 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2353 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2354 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2355 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2356 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2357 + OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2358 + AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2359 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2360 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2361 + NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2362 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2363 + OA21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2364 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2365 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2366 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2367 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2368 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2369 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2370 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2371 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2372 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2373 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2374 + AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2375 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2376 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2377 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2378 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2379 + OAI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2380 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2381 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U2382 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2383 + OAI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2384 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2385 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2386 + AOI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2387 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2388 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2389 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2390 + XOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U2391 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2392 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U2393 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2394 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2395 + OR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2396 + INV_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2397 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2398 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2399 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U2400 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U2401 + AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 +vx_front_end_vx_fetch_warp_scheduler_U2402 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2403 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2404 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2405 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2406 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2407 + OAI2XB1_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 +vx_front_end_vx_fetch_warp_scheduler_U2408 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2409 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2410 + BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2411 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2412 + NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2413 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2414 + OAI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2415 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2416 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2417 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2418 + NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2419 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2420 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2421 + OR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2422 + NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2423 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2424 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2425 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2426 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2427 + INV_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2428 + INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2429 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2430 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2431 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2432 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2433 + AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 +vx_front_end_vx_fetch_warp_scheduler_U2434 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2435 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2436 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2437 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2438 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2439 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2440 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2441 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2442 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2443 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2444 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2445 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2446 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2447 + AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2448 + AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 +vx_front_end_vx_fetch_warp_scheduler_U2449 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2450 + MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 +vx_front_end_vx_fetch_warp_scheduler_U2451 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2452 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2453 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2454 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2455 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2456 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2457 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2458 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2459 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2460 + NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2461 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2462 + OR2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2463 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2464 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2465 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2466 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2467 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2468 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2469 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2470 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2471 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2472 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2473 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2474 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2475 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2476 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2477 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2478 + AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_U2479 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2480 + AOI31_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2481 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2482 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2483 + OAI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2484 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2485 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2486 + NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2487 + OAI22BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 +vx_front_end_vx_fetch_warp_scheduler_U2488 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2489 + NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2490 + NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2491 + AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 +vx_front_end_vx_fetch_warp_scheduler_U2492 + INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 +vx_front_end_vx_fetch_warp_scheduler_U2493 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2494 + NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2495 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2496 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2497 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2498 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2499 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2500 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2501 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2502 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2503 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2504 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2505 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2506 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2507 + NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2508 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2509 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2510 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2511 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2512 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2513 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2514 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2515 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2516 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2517 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2518 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2519 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2520 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2521 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2522 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2523 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2524 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2525 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2526 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2527 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2528 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2529 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2530 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2531 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2532 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2533 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2534 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2535 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2536 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2537 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2538 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2539 + TIEHI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2540 + TIELO_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2541 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2542 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2543 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2544 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2545 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2546 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2547 + OR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2548 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2549 + NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2550 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2551 + NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2552 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2553 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2554 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2555 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2556 + NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2557 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2558 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2559 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2560 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2561 + BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 +vx_front_end_vx_fetch_warp_scheduler_U2562 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2563 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2564 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2565 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2566 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2567 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2568 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2569 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2570 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2571 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2572 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2573 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2574 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2575 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2576 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2577 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2578 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2579 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2580 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2581 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2582 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2583 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2584 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2585 + OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2586 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2587 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2588 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2589 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2590 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2591 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2592 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2593 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2594 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2595 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2596 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2597 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2598 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2599 + NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2600 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2601 + AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2602 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2603 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2604 + NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2605 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2606 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2607 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2608 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2609 + ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 r +vx_front_end_vx_fetch_warp_scheduler_U2610 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2611 + OAI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 +vx_front_end_vx_fetch_warp_scheduler_U2612 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2613 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2614 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2615 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2616 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2617 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2618 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2619 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2620 + OAI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2621 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2622 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2623 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2624 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2625 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2626 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2627 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2628 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2629 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2630 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2631 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2632 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2633 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2634 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2635 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2636 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2637 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2638 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2639 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2640 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2641 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2642 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2643 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2644 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2645 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2646 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2647 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2648 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2649 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2650 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2651 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2652 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2653 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2654 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2655 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2656 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2657 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2658 + AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2659 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2660 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2661 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2662 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2663 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2664 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2665 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2666 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2667 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2668 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2669 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2670 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2671 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2672 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2673 + AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2674 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2675 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2676 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2677 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2678 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2679 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2680 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2681 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2682 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2683 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2684 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2685 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2686 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2687 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2688 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2689 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2690 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2691 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2692 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2693 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2694 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2695 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2696 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2697 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2698 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2699 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2700 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2701 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2702 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2703 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2704 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2705 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2706 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2707 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2708 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2709 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2710 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2711 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2712 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2713 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2714 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2715 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2716 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2717 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2718 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2719 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2720 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2721 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2722 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2723 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2724 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2725 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2726 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2727 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2728 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2729 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2730 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2731 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2732 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2733 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2734 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2735 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2736 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2737 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2738 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2739 + MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2740 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2741 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2742 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2743 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2744 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2745 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2746 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2747 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2748 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2749 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2750 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2751 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2752 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2753 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2754 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2755 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2756 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2757 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2758 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2759 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2760 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2761 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2762 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2763 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2764 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2765 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2766 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2767 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2768 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2769 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2770 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2771 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2772 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2773 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2774 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2775 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2776 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2777 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2778 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2779 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2780 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2781 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2782 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2783 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2784 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2785 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2786 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2787 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2788 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2789 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2790 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2791 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2792 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2793 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2794 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2795 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2796 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2797 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2798 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2799 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2800 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2801 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2802 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2803 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2804 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2805 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2806 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2807 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2808 + OR2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2809 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2810 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2811 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2812 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2813 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2814 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2815 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2816 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2817 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2818 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2819 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2820 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2821 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2822 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2823 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2824 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2825 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2826 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2827 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2828 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2829 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2830 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2831 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2832 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2833 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2834 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2835 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2836 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2837 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2838 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2839 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2840 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2841 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2842 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2843 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2844 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2845 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2846 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2847 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2848 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2849 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2850 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2851 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2852 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2853 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2854 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2855 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2856 + NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2857 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2858 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2859 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2860 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2861 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2862 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2863 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2864 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2865 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2866 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2867 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2868 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2869 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2870 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2871 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2872 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2873 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2874 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2875 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2876 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2877 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2878 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2879 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2880 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2881 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2882 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2883 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2884 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2885 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_U2886 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2887 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2888 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2889 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2890 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2891 + NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2892 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2893 + OR4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2894 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2895 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2896 + NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2897 + NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_U2898 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2899 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2900 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2901 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2902 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2903 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2904 + NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2905 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2906 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2907 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2908 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2909 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2910 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2911 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2912 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2913 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2914 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2915 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2916 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2917 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2918 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2919 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2920 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2921 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2922 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2923 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2924 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2925 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2926 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2927 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2928 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2929 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2930 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2931 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2932 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2933 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2934 + OAI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2935 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2936 + OR4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 +vx_front_end_vx_fetch_warp_scheduler_U2937 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2938 + NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2939 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2940 + NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_U2941 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2942 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2943 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2944 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2945 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_U2946 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2947 + MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_U2948 + NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_U2949 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2950 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2951 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2952 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_U2953 + AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U1 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U2 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U3 + AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U4 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U5 + AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U6 + OA21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U7 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U8 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U9 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U10 + ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 r +vx_front_end_vx_fetch_warp_scheduler_barrier_count_U11 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_0__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_1__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_2__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_barrier_stall_mask_reg_3__7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U3 + NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U4 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U5 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U6 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U7 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U8 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U9 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U10 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U11 + AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U12 + OAI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U14 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U15 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U16 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U17 + OR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U18 + OA21A1OI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_choose_schedule_U19 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U3 + INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U4 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U5 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U6 + NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U7 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U8 + OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U9 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U10 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U11 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U12 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U13 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U14 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U15 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U16 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U17 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U18 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U19 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U20 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U22 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U24 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U26 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U27 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U28 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U29 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U30 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U31 + OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U32 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U33 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U34 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U36 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U37 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U38 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U39 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U40 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U42 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U43 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U45 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U46 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U47 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U48 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U49 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U50 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U51 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U52 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U53 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U54 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U55 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U56 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U57 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U58 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U59 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U60 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U61 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U62 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U63 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U64 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U76 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U77 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U79 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U80 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U81 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U82 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U83 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U84 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U85 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U86 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U87 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U88 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U89 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U90 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U91 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U92 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U93 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U94 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U95 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U96 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U97 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U98 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U99 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U100 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U101 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U102 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U103 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U113 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U149 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U150 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U151 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U152 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U153 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U154 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U155 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_0__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U3 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U4 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U5 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U6 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U7 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U8 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U9 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U10 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U11 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U12 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U13 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U14 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U15 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U16 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U17 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U18 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U19 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U20 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U21 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U22 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U23 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U24 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U25 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U26 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U27 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U28 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U29 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U30 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U31 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U32 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U33 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U34 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U35 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U36 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U37 + OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U38 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U39 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U40 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U41 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U42 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U43 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U44 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U45 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U46 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U47 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U48 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U49 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U50 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U51 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U52 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U53 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U54 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U55 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U56 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U57 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U58 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U59 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U60 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U61 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U62 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U63 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U64 + OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U65 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U66 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U67 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U68 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U69 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U70 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U71 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U72 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U73 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U74 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U75 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U76 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U77 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U78 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U79 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U80 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U113 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U114 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U115 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U116 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U117 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U118 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U119 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U120 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U149 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U150 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U151 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U152 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U153 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U154 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U155 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_1__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U3 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U4 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U5 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U6 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U7 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U8 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U9 + OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U10 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U11 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U12 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U13 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U14 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U15 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U16 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U17 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U18 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U19 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U20 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U21 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U22 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U23 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U24 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U25 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U26 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U27 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U28 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U29 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U30 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U31 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U32 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U33 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U34 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U35 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U36 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U37 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U38 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U39 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U40 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U41 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U45 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U46 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U47 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U48 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U49 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U50 + OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U51 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U52 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U53 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U54 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U55 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U56 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U57 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U58 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U59 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U60 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U61 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U62 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U63 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U64 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U76 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U77 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U97 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U98 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U99 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U100 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U101 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U102 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U103 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U104 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U149 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U150 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U151 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U152 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U153 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U154 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U155 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_2__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U4 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U5 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U6 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U7 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U8 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U9 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U10 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U11 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U12 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U13 + OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U14 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U15 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U16 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U17 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U18 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U19 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U20 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U21 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U22 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U24 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U25 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U26 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U27 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U28 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U29 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U30 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U31 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U32 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U34 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U35 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U36 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U37 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U38 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U39 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U40 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U41 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U42 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U43 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U44 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U45 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U46 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U47 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U48 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U49 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U50 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U51 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U52 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U53 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U54 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U55 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U56 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U57 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U58 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U59 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U60 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U61 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U62 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U63 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U64 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U76 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U77 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U87 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U88 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U89 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U90 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U91 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U92 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U93 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U94 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U95 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U96 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U97 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U98 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U99 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U100 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U101 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U102 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U103 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U104 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U105 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U106 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U107 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U108 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U109 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U110 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U111 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U112 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U113 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U114 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U115 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U116 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U117 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U118 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U119 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U120 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U121 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U122 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U123 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U124 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U125 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U126 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U127 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U128 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U129 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U130 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U131 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U132 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U133 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U134 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U135 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U136 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U137 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U138 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U139 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U140 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U141 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U142 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U143 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U144 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U145 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U146 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U147 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U148 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U149 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U150 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U151 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U152 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U153 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U154 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U155 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U156 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U157 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U158 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U159 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U160 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_U161 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_3__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U3 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U4 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U5 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U6 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U7 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U8 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U9 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U10 + OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U11 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U12 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U13 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U14 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U15 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U16 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U17 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U18 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U19 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U20 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U21 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U22 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U23 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U24 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U25 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U26 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U27 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U28 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U29 + OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U30 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U31 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U32 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U34 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U35 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U36 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U37 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U38 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U39 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U40 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U41 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U43 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U44 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U45 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U46 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U47 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U48 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U49 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U50 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U51 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U52 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U53 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U54 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U55 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U56 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U57 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U58 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U59 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U60 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U61 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U62 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U63 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U64 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U76 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U77 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U78 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U79 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U80 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U81 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U82 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U83 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U84 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U85 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U86 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U87 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U88 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U89 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U90 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U91 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U92 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U93 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U94 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U95 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U96 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U97 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U98 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U99 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U100 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U101 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U102 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U103 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U113 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U149 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U150 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U151 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U152 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U153 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U154 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U155 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_4__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U4 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U5 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U6 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U7 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U8 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U9 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U10 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U11 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U12 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U13 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U14 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U15 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U16 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U17 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U18 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U19 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U20 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U21 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U22 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U23 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U24 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U25 + OAI21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U26 + NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U27 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U28 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U29 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U30 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U31 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U32 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U33 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U34 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U35 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U36 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U37 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U38 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U39 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U40 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U41 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U46 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U47 + OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U48 + NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U49 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U50 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U51 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U52 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U53 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U54 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U55 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U56 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U57 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U58 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U59 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U60 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U61 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U62 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U63 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U64 + NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U76 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U77 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U97 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U98 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U99 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U100 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U101 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U102 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U103 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U104 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U105 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U149 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U150 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U151 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U152 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U153 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U154 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U155 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_U157 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_5__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U4 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U5 + INV_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U6 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U7 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U8 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U9 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U10 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U11 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U12 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U13 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U14 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U15 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U16 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U17 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U18 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U19 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U20 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U21 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U22 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U23 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U24 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U25 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U26 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U27 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U28 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U29 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U30 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U31 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U32 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U33 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U34 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U35 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U36 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U37 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U38 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U39 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U40 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U41 + INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U42 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U43 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U44 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U45 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U46 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U47 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U48 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U49 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U50 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U51 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U52 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U53 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U54 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U55 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U56 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U57 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U58 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U59 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U60 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U61 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U62 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U63 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U64 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U65 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U66 + OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U67 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U68 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U69 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U70 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U71 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U72 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U73 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U74 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U75 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U76 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U77 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U78 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U79 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U80 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U81 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U82 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U83 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U89 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U90 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U91 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U92 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U93 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U94 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U95 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U96 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U97 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U110 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U111 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U112 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U113 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U114 + AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U115 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U116 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U124 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U125 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U126 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U127 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U128 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U129 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U130 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U131 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U132 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U133 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U134 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U135 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U136 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U137 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U138 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U139 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U140 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U141 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U142 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U143 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U144 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U145 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U146 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U147 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U148 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U149 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U150 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U151 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U152 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U153 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U154 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U155 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_U156 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_6__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U3 + INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U4 + INV_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U5 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U6 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U7 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U8 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U9 + BUF_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U10 + BUF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U11 + NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U12 + OAI21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U13 + BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U14 + INV_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U15 + NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U16 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U17 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U18 + AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U19 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U20 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U21 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U22 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U23 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U24 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U25 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U26 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U27 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U28 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U29 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U30 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U31 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U32 + AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U33 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U34 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U35 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U36 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U37 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U38 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U39 + AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U40 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U41 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U42 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U43 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U44 + OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U45 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U46 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U47 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U48 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U49 + AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U50 + AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U51 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U52 + NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U53 + NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U54 + AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U55 + OAI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U56 + NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U57 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U58 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U59 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U60 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U61 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U62 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U63 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U64 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U65 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U66 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U67 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U68 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U69 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U70 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U71 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U72 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U73 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U74 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U75 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U76 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U77 + AO22_X0P5M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U84 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U85 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U86 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U87 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U88 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U89 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U90 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U91 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U92 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U93 + NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U94 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U95 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U96 + AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U97 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U98 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U99 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U100 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U101 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U102 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U103 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U104 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U105 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U106 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U107 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U108 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U109 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U110 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U111 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U112 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U113 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U114 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U115 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U116 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U117 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U118 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U119 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U120 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U121 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U122 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U123 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U124 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U125 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U126 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U127 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U128 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U129 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U130 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U131 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U132 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U133 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U134 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U135 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U136 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U137 + AO22_X0P7M_A12TUL_C35 + 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U144 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U145 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U146 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U147 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U148 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U149 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U150 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U151 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U152 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U153 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U154 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U155 + AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U156 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U157 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U158 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_U159 + AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_ptr_reg_0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_ptr_reg_1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_0__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_1__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__0_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__1_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__2_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__3_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__4_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__5_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__6_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__7_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__8_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__9_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__10_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__11_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__12_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__13_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__14_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__15_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__16_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__17_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__18_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__19_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__20_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__21_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__22_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__23_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__24_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__25_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__26_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__27_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__28_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__29_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__30_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__31_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__32_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__33_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__34_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__35_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_genblk1_7__ipdom_stack_stack_reg_2__36_ + DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 n +vx_front_end_vx_fetch_warp_scheduler_num_visible_U1 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U2 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U3 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U4 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U5 + OA21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U6 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U7 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U8 + OAI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U9 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U10 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U11 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U12 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U13 + INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U14 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U15 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U16 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U17 + NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U18 + NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U19 + XOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U20 + XNOR2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U21 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U22 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_num_visible_U23 + CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_0__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_1__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_2__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_3__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_4__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_5__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_6__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_thread_masks_reg_7__3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_0_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_1_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_8_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_9_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_10_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_11_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_12_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_13_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_14_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_15_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_16_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_17_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_18_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_19_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_20_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_21_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_22_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_23_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_24_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_25_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_26_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_27_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_28_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_29_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_30_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_pc_reg_31_ + DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_use_wsapwn_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_0_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_visible_active_reg_7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_0_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_active_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__2_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__3_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__4_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__5_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__6_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__7_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__8_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__9_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__10_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__11_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__12_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__13_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__14_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__15_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__16_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__17_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__18_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__19_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__20_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__21_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__22_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__23_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__24_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__25_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__26_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__27_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__28_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__29_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__30_ + DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_0__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_1__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_2__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_3__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_4__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_5__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_6__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__0_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__1_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__2_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__3_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__4_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__5_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__6_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__7_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__8_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__9_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__10_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__11_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__12_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__13_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__14_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__15_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__16_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__17_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__18_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__19_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__20_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__21_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__22_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__23_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__24_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__25_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__26_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__27_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__28_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__29_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__30_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_pcs_reg_7__31_ + DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_0_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_1_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_2_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_3_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_4_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_5_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_6_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +vx_front_end_vx_fetch_warp_scheduler_warp_stalled_reg_7_ + DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 n +-------------------------------------------------------------------------------- +Total 178940 cells 663659.381451 +1 +report_reference + +**************************************** +Report : reference +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:36:53 2019 +**************************************** + +Attributes: + b - black box (unknown) + bo - allows boundary optimization + d - dont_touch + mo - map_only + h - hierarchical + n - noncombinational + r - removable + s - synthetic operator + u - contains unmapped logic + +Reference Library Unit Area Count Total Area Attributes +----------------------------------------------------------------------------- +ADDF_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 3929 10820.465798 r +ADDF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 83 255.474006 r +ADDF_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 69 212.382005 r +ADDH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 230 409.859987 r +ADDH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 8 16.848000 r +ADDH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 5 10.530000 r +AND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 336 272.160001 +AND2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 355 287.550001 +AND2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 330 267.300001 +AND2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 391 316.710001 +AND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3 2.916000 +AND2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 29 28.188000 +AND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 38 36.936000 +AND2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 118 114.696000 +AND2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 377 549.665979 +AND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 157 254.340001 +AND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 39 75.816000 +AND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 435 1127.520003 +AND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 7 18.144000 +AND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 77 249.480001 +AND2_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 44 192.456003 +AND3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +AND3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 9 8.748000 +AND3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 26 25.272000 +AND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +AND3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 17 19.277999 +AND3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 1 2.106000 +AND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 5 17.010000 +AND4_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 7 7.938000 +AND4_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +AND4_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 2 2.268000 +AND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 4 9.072000 +AO1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 852 828.144002 +AO1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 71 69.012000 +AO1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 56 72.576000 +AO1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 135 174.960001 +AO1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 73 141.912000 +AO1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 274 621.431969 +AO1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 96 311.040001 +AO21A1AI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 195 189.540001 +AO21A1AI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 40 38.880000 +AO21A1AI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3 2.916000 +AO21A1AI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 4 6.480000 +AO21A1AI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 12 19.440000 +AO21A1AI2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 37 83.915996 +AO21A1AI2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 8 23.327999 +AO21A1AI2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 49 206.387995 +AO21B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 156 151.632000 +AO21B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +AO21B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3 2.916000 +AO21B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 2 2.592000 +AO21B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 36 46.656000 +AO21B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 22 42.768000 +AO21B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 20 45.359998 +AO21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 20 64.800000 +AO21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 40 45.359998 +AO21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 86 97.523995 +AO21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 70 79.379996 +AO21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 10 12.960000 +AO21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 11 14.256000 +AO21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 54 104.976000 +AO21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 4 8.424000 +AO21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 39 132.677998 +AO22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1178 1526.688004 +AO22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1193 1546.128005 +AO22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 49 63.504000 +AO22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 4 16.200001 +AOI2XB1_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 28 31.751998 +AOI2XB1_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 37 41.957998 +AOI2XB1_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 69 78.245996 +AOI2XB1_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 12 19.440000 +AOI2XB1_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 44 71.280000 +AOI2XB1_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 37 77.921998 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sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 11 28.512000 +AOI21B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 7 26.082000 +AOI21B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 3 14.094000 +AOI21_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 4552 3687.120011 +AOI21_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 2474 2003.940006 +AOI21_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 954 772.740002 +AOI21_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 853 1105.488003 +AOI21_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1093 1416.528004 +AOI21_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 608 1083.455967 +AOI21_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 455 1031.939949 +AOI21_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 360 1166.400003 +AOI21_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 329 1385.747965 +AOI22BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 4 5.184000 +AOI22BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 7 9.072000 +AOI22BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 14 18.144000 +AOI22BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 21 37.421999 +AOI22BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 21 37.421999 +AOI22BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 10 25.920000 +AOI22BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 14 43.092001 +AOI22BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 6 26.244000 +AOI22BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.670000 4 22.680000 +AOI22_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 2064 2006.208006 +AOI22_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3961 3850.092011 +AOI22_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1739 1690.308005 +AOI22_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 1124 1820.880005 +AOI22_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 1324 2144.880006 +AOI22_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 374 848.231958 +AOI22_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 91 265.355990 +AOI22_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 30 126.359997 +AOI22_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.508000 17 93.635998 +AOI31_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 49 47.628000 +AOI31_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 9 8.748000 +AOI31_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +AOI31_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 4 7.128000 +AOI31_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 11 24.947999 +AOI31_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 9 27.702001 +AOI31_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 22 96.228002 +AOI211_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 521 506.412001 +AOI211_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 20 19.440000 +AOI211_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 3 4.860000 +AOI211_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 30 48.600000 +AOI211_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 12 27.215999 +AOI211_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 12 34.991999 +BUFH_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 223 144.504000 +BUFH_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 1 0.810000 +BUFH_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 5 4.050000 +BUFH_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 194 157.140000 +BUFH_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 8 7.776000 +BUFH_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 131 148.553993 +BUFH_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 99 128.304000 +BUFH_X5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 26 42.120000 +BUFH_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 60 116.640000 +BUFH_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 76 184.680005 +BUFH_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 78 240.084005 +BUFH_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.888000 53 206.064001 +BUF_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 351 227.448001 +BUF_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 26 16.848000 +BUF_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 161 104.328000 +BUF_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 24 19.440000 +BUF_X2B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 15 12.150000 +BUF_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 130 105.300000 +BUF_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 74 71.928000 +BUF_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 43 48.761998 +BUF_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 34 44.064000 +BUF_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 33 48.113998 +BUF_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 85 137.700000 +BUF_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 50 97.200000 +BUF_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 26 58.967997 +BUF_X13M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 38 123.120000 +CGENCON_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 1 3.240000 +CGENI_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 257 291.437986 +CGENI_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 12 23.328000 +CGENI_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 40 77.760000 +CGEN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 146 189.216001 +DFFQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 648 1784.591967 n +DFFRPQL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 121 411.641994 n +DFFRPQNL_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 22 71.280000 n +DFFRPQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 31 100.440000 n +DFFRPQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 1625 5528.249919 n +DFFRPQ_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 17 60.587998 n +DFFRPQ_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 11 40.986001 n +DFFRPQ_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.050000 35 141.750007 n +DFFSQN_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 1 3.240000 n +DFFSQN_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.564000 1 3.564000 n +INV_X0P6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 18919 9194.634027 +INV_X0P6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 3926 1908.036006 +INV_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 423 205.578001 +INV_X0P8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 223 108.378000 +INV_X1M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.486000 2966 1441.476004 +INV_X1P2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 150 97.200000 +INV_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 25 16.200000 +INV_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 129 83.592000 +INV_X1P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 94 60.912000 +INV_X2M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 1001 648.648002 +INV_X2P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 75 60.750000 +INV_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 39 31.590000 +INV_X3M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 397 321.570001 +INV_X3P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 130 126.360000 +INV_X4M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 328 318.816001 +INV_X5M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 188 213.191989 +INV_X6M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 206 266.976001 +INV_X7P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 323 523.260002 +INV_X9M_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 54 96.227997 +INV_X11M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 96 202.175995 +INV_X16M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 235 723.330016 +LATQ_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 129 208.980001 n +MX2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 2 3.240000 +MX2_X1B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 1 1.620000 +MX2_X3B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 2 6.156000 +MX2_X4B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.402000 2 6.804000 +MX2_X6B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.698000 3 14.094000 +MX2_X8B_A12TUL_C35 sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 5.346000 5 26.730001 +MXIT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 789 894.725956 +MXIT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 32 41.472000 +MXIT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 46 67.067997 +MXIT2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 175 311.849990 +MXIT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.106000 65 136.889997 +MXIT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 163 396.090011 +MXIT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 1350 4374.000013 +MXT2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 141 205.577992 +MXT2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 5 7.290000 +MXT2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 2 3.240000 +MXT2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 7 12.474000 +MXT2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 7 18.144000 +MXT2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.754000 2 5.508000 +MXT2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 1 3.726000 +MXT2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 37 137.862003 +NAND2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 609 493.290001 +NAND2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 39 44.225998 +NAND2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 123 139.481993 +NAND2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 100 145.799994 +NAND2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 54 96.227997 +NAND2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 102 264.384001 +NAND2B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 34 110.160000 +NAND2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 56 45.360000 +NAND2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 349 282.690001 +NAND2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 20 22.679999 +NAND2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 153 173.501991 +NAND2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 109 158.921994 +NAND2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 115 204.929994 +NAND2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 99 256.608001 +NAND2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 46 149.040000 +NAND2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 15700 10173.600030 +NAND2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 430 278.640001 +NAND2_X0P7B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 3706 2401.488007 +NAND2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 2439 1580.472005 +NAND2_X1B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 4492 2910.816009 +NAND2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 842 818.424002 +NAND2_X1P4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1750 1701.000005 +NAND2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1293 1256.796004 +NAND2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1449 1408.428004 +NAND2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 599 776.304002 +NAND2_X3B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 507 657.072002 +NAND2_X4B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 291 471.420001 +NAND2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 523 847.260002 +NAND2_X6B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 148 335.663983 +NAND2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 541 1226.987939 +NAND2_X8B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 57 166.211994 +NAND2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 297 866.051967 +NAND3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 55 53.460000 +NAND3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 43 41.796000 +NAND3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 3 3.888000 +NAND3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 15 19.440000 +NAND3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 52 101.088000 +NAND3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 36 81.647996 +NAND3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 39 126.360000 +NAND3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 30 126.359997 +NAND3B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 1 0.972000 +NAND3B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 1 3.726000 +NAND3XXB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3 2.916000 +NAND3XXB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 2 1.944000 +NAND3XXB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 1 1.458000 +NAND3XXB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 1 1.944000 +NAND3XXB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.726000 2 7.452000 +NAND3_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 204 165.240000 +NAND3_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 94 76.140000 +NAND3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 81 65.610000 +NAND3_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 6 7.776000 +NAND3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 48 62.208000 +NAND3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 26 33.696000 +NAND3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 2 2.592000 +NAND3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 183 326.105990 +NAND3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 8 14.256000 +NAND3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 403 914.003955 +NAND3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 18 40.823998 +NAND3_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 389 1260.360004 +NAND3_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 73 236.520001 +NAND4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 12 13.607999 +NAND4BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 9 10.205999 +NAND4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 3 3.402000 +NAND4BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 1 1.782000 +NAND4BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 1 2.430000 +NAND4BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.374000 5 21.870000 +NAND4B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +NAND4B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 1 1.134000 +NAND4_X0P5A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 30 29.160000 +NAND4_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 334 324.648001 +NAND4_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 16 15.552000 +NAND4_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 25 40.500000 +NAND4_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 53 85.860000 +NAND4_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 32 72.575996 +NAND4_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 405 1180.979955 +NOR2B_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 55 44.550000 +NOR2B_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 15 12.150000 +NOR2B_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 135 109.350000 +NOR2B_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 5 5.670000 +NOR2B_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 17 19.277999 +NOR2B_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 20 29.159999 +NOR2B_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 12 21.383999 +NOR2B_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 29 75.168000 +NOR2B_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 20 64.800000 +NOR2XB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 9 7.290000 +NOR2XB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 18 14.580000 +NOR2XB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 42 34.020000 +NOR2XB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 5 5.670000 +NOR2XB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 56 63.503997 +NOR2XB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.458000 15 21.869999 +NOR2XB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 12 21.383999 +NOR2XB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.592000 12 31.104000 +NOR2XB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 5 16.200000 +NOR2_X0P5B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 4321 2800.008008 +NOR2_X0P7A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 125 81.000000 +NOR2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 1424 922.752003 +NOR2_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 3665 2374.920007 +NOR2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.648000 3393 2198.664006 +NOR2_X1P4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 158 153.576000 +NOR2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 929 902.988003 +NOR2_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 2250 2187.000006 +NOR2_X2B_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 251 243.972001 +NOR2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 3777 3671.244011 +NOR2_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 1024 1327.104004 +NOR2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 793 1027.728003 +NOR2_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 564 913.680003 +NOR2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 221 358.020001 +NOR2_X6A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 639 1449.251928 +NOR2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 262 594.215971 +NOR2_X8A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 343 1000.187962 +NOR2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.916000 153 446.147983 +NOR3BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 58 56.376000 +NOR3BB_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 14 13.608000 +NOR3BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 30 29.160000 +NOR3BB_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 11 14.256000 +NOR3BB_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 14 18.144000 +NOR3BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 20 38.880000 +NOR3BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 18 40.823998 +NOR3BB_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 24 77.760000 +NOR3BB_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 17 71.603998 +NOR3_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 82 66.420000 +NOR3_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 3 2.430000 +NOR3_X1A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 53 42.930000 +NOR3_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.810000 21 17.010000 +NOR3_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 3 3.888000 +NOR3_X2A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 7 9.072000 +NOR3_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 9 11.664000 +NOR3_X3A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 6 10.692000 +NOR3_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.782000 2 3.564000 +NOR3_X4A_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 20 45.359998 +NOR3_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 21 47.627998 +NOR4BB_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 43 48.761998 +NOR4BB_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.134000 6 6.804000 +NOR4BB_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.430000 1 2.430000 +NOR4BB_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.078000 1 3.078000 +OA1B2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 23 22.356000 +OA1B2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 39 37.908000 +OA1B2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 12 15.552000 +OA1B2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.296000 60 77.760000 +OA1B2_X3M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.944000 44 85.536000 +OA1B2_X4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 2.268000 33 74.843996 +OA1B2_X6M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 3.240000 31 100.440000 +OA1B2_X8M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 4.212000 16 67.391998 +OA21A1OI2_X0P5M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 198 192.456001 +OA21A1OI2_X0P7M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 97 94.284000 +OA21A1OI2_X1M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 0.972000 5 4.860000 +OA21A1OI2_X1P4M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 4 6.480000 +OA21A1OI2_X2M_A12TUL_C35 + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + 1.620000 11 17.820000 +OA21A1OI2_X3M_A12TUL_C35 + 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+----------------------------------------------------------------------------- +Total 487 references 663659.381451 +1 +report_port + +**************************************** +Report : port +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:36:53 2019 +**************************************** + + + +Attributes: + i - ideal_network + + Pin Wire Max Max Connection +Port Dir Load Load Trans Cap Class Attrs +-------------------------------------------------------------------------------- +clk in 0.0000 0.0000 -- -- -- i +i_m_readdata_0__0__0_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__1_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__2_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__3_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__4_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__5_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__6_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__7_ + in 0.0000 0.0000 -- -- -- +i_m_readdata_0__0__8_ + in 0.0000 0.0000 -- -- -- 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+icache_response_instruction_9_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_10_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_11_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_12_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_13_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_14_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_15_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_16_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_17_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_18_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_19_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_20_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_21_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_22_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_23_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_24_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_25_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_26_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_27_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_28_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_29_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_30_ + in 0.0000 0.0000 -- -- -- +icache_response_instruction_31_ + in 0.0000 0.0000 -- -- -- +reset in 0.0000 0.0000 -- -- -- +icache_request_pc_address_0_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_1_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_2_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_3_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_4_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_5_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_6_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_7_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_8_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_9_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_10_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_11_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_12_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_13_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_14_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_15_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_16_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_17_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_18_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_19_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_20_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_21_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_22_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_23_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_24_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_25_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_26_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_27_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_28_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_29_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_30_ + out 0.0000 0.0000 -- -- -- +icache_request_pc_address_31_ + out 0.0000 0.0000 -- -- -- +io_data_0_ out 0.0000 0.0000 -- -- -- +io_data_1_ out 0.0000 0.0000 -- -- -- +io_data_2_ out 0.0000 0.0000 -- -- -- +io_data_3_ out 0.0000 0.0000 -- -- -- +io_data_4_ out 0.0000 0.0000 -- -- -- +io_data_5_ out 0.0000 0.0000 -- -- -- +io_data_6_ out 0.0000 0.0000 -- -- -- +io_data_7_ out 0.0000 0.0000 -- -- -- +io_data_8_ out 0.0000 0.0000 -- -- -- +io_data_9_ out 0.0000 0.0000 -- -- -- +io_data_10_ out 0.0000 0.0000 -- -- -- +io_data_11_ out 0.0000 0.0000 -- -- -- +io_data_12_ out 0.0000 0.0000 -- -- -- +io_data_13_ out 0.0000 0.0000 -- -- -- +io_data_14_ out 0.0000 0.0000 -- -- -- +io_data_15_ out 0.0000 0.0000 -- -- -- +io_data_16_ out 0.0000 0.0000 -- -- -- +io_data_17_ out 0.0000 0.0000 -- -- -- +io_data_18_ out 0.0000 0.0000 -- -- -- +io_data_19_ out 0.0000 0.0000 -- -- -- +io_data_20_ out 0.0000 0.0000 -- -- -- +io_data_21_ out 0.0000 0.0000 -- -- -- +io_data_22_ out 0.0000 0.0000 -- -- -- +io_data_23_ out 0.0000 0.0000 -- -- -- +io_data_24_ out 0.0000 0.0000 -- -- -- +io_data_25_ out 0.0000 0.0000 -- -- -- +io_data_26_ out 0.0000 0.0000 -- -- -- +io_data_27_ out 0.0000 0.0000 -- -- -- +io_data_28_ out 0.0000 0.0000 -- -- -- +io_data_29_ out 0.0000 0.0000 -- -- -- +io_data_30_ out 0.0000 0.0000 -- -- -- +io_data_31_ out 0.0000 0.0000 -- -- -- +io_valid out 0.0000 0.0000 -- -- -- +o_m_evict_addr_0_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_1_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_2_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_3_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_4_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_5_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_6_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_7_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_8_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_9_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_10_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_11_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_12_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_13_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_14_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_15_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_16_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_17_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_18_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_19_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_20_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_21_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_22_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_23_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_24_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_25_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_26_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_27_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_28_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_29_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_30_ + out 0.0000 0.0000 -- -- -- +o_m_evict_addr_31_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_0_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_1_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_2_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_3_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_4_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_5_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_6_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_7_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_8_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_9_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_10_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_11_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_12_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_13_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_14_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_15_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_16_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_17_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_18_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_19_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_20_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_21_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_22_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_23_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_24_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_25_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_26_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_27_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_28_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_29_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_30_ + out 0.0000 0.0000 -- -- -- +o_m_read_addr_31_ + out 0.0000 0.0000 -- -- -- +o_m_read_or_write + out 0.0000 0.0000 -- -- -- +o_m_valid out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__17_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__0__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__17_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__1__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__17_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__18_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__19_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__20_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__21_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__22_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__23_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__24_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__25_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__26_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__27_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__28_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__29_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__30_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__2__31_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__0_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__1_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__2_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__3_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__4_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__5_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__6_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__7_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__8_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__9_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__10_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__11_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__12_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__13_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__14_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__15_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__16_ + out 0.0000 0.0000 -- -- -- +o_m_writedata_0__3__17_ + out 0.0000 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(PWR-6) +Warning: Design has unannotated primary inputs. (PWR-414) +Warning: Design has unannotated sequential cell outputs. (PWR-415) +Warning: Design has unannotated black box outputs. (PWR-428) + +**************************************** +Report : power + -analysis_effort low +Design : Vortex +Version: O-2018.06-SP3 +Date : Mon Oct 28 20:37:08 2019 +**************************************** + + +Library(s) Used: + + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db) + sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c (File: /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db) + USERLIB_ss_0p81v_0p81v_m40c (File: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpm/2d_hardmacro_db/rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db) + + +Operating Conditions: ssg_typical_max_0p81v_m40c Library: sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c +Wire Load Model Mode: top + +Design Wire Load Model Library +------------------------------------------------ +Vortex Small sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c + + +Global Operating Voltage = 0.81 +Power-specific unit information : + Voltage Units = 1V + Capacitance Units = 1.000000pf + Time Units = 1ns + Dynamic Power Units = 1mW (derived from V,C,T units) + Leakage Power Units = 1uW + + + Cell Internal Power = 170.6666 mW (83%) + Net Switching Power = 34.2001 mW (17%) + --------- +Total Dynamic Power = 204.8668 mW (100%) + +Cell Leakage Power = 67.8704 uW + + + Internal Switching Leakage Total +Power Group Power Power Power Power ( % ) Attrs +-------------------------------------------------------------------------------------------------- +io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) +memory 146.3401 0.3551 34.8456 146.7300 ( 71.60%) +black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) +clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%) +register 8.1184 0.3667 0.8178 8.4859 ( 4.14%) +sequential 4.3550e-03 0.0000 3.0841e-02 4.3858e-03 ( 0.00%) +combinational 16.2039 33.4782 32.1752 49.7134 ( 24.26%) +-------------------------------------------------------------------------------------------------- +Total 170.6667 mW 34.2000 mW 67.8694 uW 204.9336 mW +1 +write -hierarchy -format verilog -output Vortex.netlist.v +Writing verilog file '/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/syn/Vortex.netlist.v'. +Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4) +1 +remove_ideal_network [get_ports clk] +1 +set_propagated_clock [get_ports clk] +Information: set_input_delay values are added to the propagated clock skew. (TIM-113) +1 +write_sdc -version 1.9 Vortex.sdc +1 +write_file -format ddc -output Vortex.ddc +Writing ddc file 'Vortex.ddc'. +1 +exit + +Thank you...