wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis

Browse Source
This commit is contained in:
Blaise Tine
2020-05-28 18:34:25 -04:00
parent b930a822ad b43dd76d0d
commit 33b273b204
4 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
hw/rtl/cache/VX_bank.v vendored
View File

@@ -249,6 +249,8 @@ module VX_bank #(
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
wire is_fill_st2;
wire recover_mrvq_state_st2;
wire mrvq_push_stall;
wire cwbq_push_stall;
wire dwbq_push_stall;
@@ -474,8 +476,7 @@ module VX_bank #(
wire mrvq_init_ready_state_unqual_st2;
wire mrvq_init_ready_state_hazard_st0_st1;
wire mrvq_init_ready_state_hazard_st1e_st1;
wire recover_mrvq_state_st2;
VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
) st_1e_2 (

6
hw/rtl/cache/VX_cache.v vendored
View File

@@ -48,13 +48,13 @@ module VX_cache #(
parameter PRFQ_STRIDE = 0,
// core request tag size
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_WIDTH = 42,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 42,
parameter CORE_TAG_ID_BITS = 8,
// dram request tag size
parameter DRAM_TAG_WIDTH = 8,
parameter DRAM_TAG_WIDTH = 28,
// Number of snoop forwarding requests
parameter NUM_SNP_REQUESTS = 2,