scope refactoring: adding modules definitions to VCD trace
This commit is contained in:
Blaise Tine
@@ -11,12 +11,89 @@ vl_ifdef_re = re.compile(r"^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$")
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vl_endif_re = re.compile(r"^\s*`(endif|else)\s*$")
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vl_expand_re = re.compile(r"`([0-9a-zA-Z_]+)")
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parameters = []
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exclude_files = []
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include_dirs = []
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macros = []
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br_stack = []
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def translate_ternary(text):
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def skip_space(text, i, ln, step):
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while (i >= 0) and (i < ln):
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c = text[i]
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if not c.isspace():
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break
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i += step
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return i
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def skip_expr(text, i, ln, step):
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paren = 0
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checkparen = True
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while (i >= 0) and (i < ln):
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c = text[i]
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if checkparen and (((step < 0) and (c == ')')) or ((step > 0) and (c == '('))):
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paren += 1
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elif checkparen and (((step < 0) and (c == '(')) or ((step > 0) and (c == ')'))):
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if (0 == paren):
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break
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paren -= 1
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if (0 == paren):
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i = skip_space(text, i + step, ln, step)
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checkparen = False
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continue
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elif (0 == paren) and not (c.isalnum() or (c == '_')):
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break
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i += step
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return (i - step)
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def parse_ternary(text):
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ternary = None
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ln = len(text)
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for i in range(1, ln):
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c = text[i]
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if not (c == '?'):
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continue
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# parse condition expression
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i0 = skip_space(text, i - 1, ln, -1)
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if (i < 0):
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raise Exception("invalid condition expression")
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i1 = skip_expr(text, i0, ln, -1)
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if (i1 > i0):
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raise Exception("invalid condition expression")
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# parse true expression
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i2 = skip_space(text, i + 1, ln, 1)
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if (i2 >= ln):
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raise Exception("invalid true expression")
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i3 = skip_expr(text, i2, ln, 1)
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if (i3 < i2):
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raise Exception("invalid true expression")
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# parse colon
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i4 = skip_space(text, i3 + 1, ln, 1)
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if (i4 >= ln):
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raise Exception("invalid colon")
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if not (text[i4] == ':'):
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raise Exception("missing colon")
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# parse false expression
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i5 = skip_space(text, i4 + 1, ln, 1)
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if (i5 >= ln):
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raise Exception("invalid false expression")
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i6 = skip_expr(text, i5, ln, 1)
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if (i6 < i5):
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raise Exception("invalid false expression")
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ternary = (i0, i1, i2, i3, i5, i6)
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break
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return ternary
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while True:
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pos = parse_ternary(text)
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if pos is None:
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break
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# convert to python ternary
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newText = text[:pos[1]] + text[pos[2]:pos[3]+1] + " if " + text[pos[1]:pos[0]+1] + " else " + text[pos[4]:pos[5]+1] + text[pos[5]+1:]
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text = newText
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return text
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def parse_func_args(text):
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args = []
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arg = ''
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@@ -26,7 +103,6 @@ def parse_func_args(text):
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paren = 1
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for i in range(1, l):
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c = text[i]
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if c == '(':
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paren += 1
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elif c == ')':
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@@ -36,17 +112,14 @@ def parse_func_args(text):
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if paren == 0:
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l = i
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break
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if c == ',' and paren == 1:
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if arg.strip():
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args.append(arg)
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arg = ''
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else:
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arg += c
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if paren != 0:
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raise Exception("missing closing parenthesis: " + text)
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if arg.strip():
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args.append(arg)
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@@ -90,9 +163,29 @@ def find_macro(name):
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return macro
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return None
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def expand_text(text):
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def expand_text(text, params):
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class DoRepl(object):
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def re_pattern_args(args):
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p = "(?<![0-9a-zA-Z_])("
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i = 0
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for arg in args:
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if i > 0:
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p += "|"
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p += arg
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i += 1
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p += ")(?![0-9a-zA-Z_])"
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return p
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class DoReplParam(object):
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def __init__(self, params):
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self.params = params
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self.expanded = False
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def __call__(self, match):
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name = match.group(1)
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self.expanded = True
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return self.params[name]
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class DoReplMacro(object):
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def __init__(self):
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self.expanded = False
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self.has_func = False
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@@ -107,17 +200,6 @@ def expand_text(text):
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return macro[2]
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return "`" + name
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class DoRepl2(object):
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def __init__(self, args, f_args):
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map = {}
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for i in range(len(args)):
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map[args[i]] = f_args[i]
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self.map = map
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def __call__(self, match):
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for key in match.groups():
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return self.map[key]
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return group
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def repl_func_macro(text):
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expanded = False
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match = re.search(vl_expand_re, text)
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@@ -137,14 +219,11 @@ def expand_text(text):
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if len(args) != len(f_args[0]):
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raise Exception("mismatch number of argments for macro '" + name + "': actual=" + len(f_args[0]) + ", expected=" + len(args))
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pattern = "(?<![0-9a-zA-Z_])("
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pattern = re_pattern_args(args)
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params = {}
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for i in range(len(args)):
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if i > 0:
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pattern += "|"
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pattern += args[i]
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pattern += ")(?![0-9a-zA-Z_])"
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dorepl = DoRepl2(args, f_args[0])
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params[args[i]] = f_args[0][i]
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dorepl = DoReplParam(params)
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value = re.sub(pattern, dorepl, value)
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str_head = text[0:match.start()]
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@@ -163,10 +242,18 @@ def expand_text(text):
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raise Exception("Macro recursion!")
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has_func = False
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while True:
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do_repl = DoRepl()
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params_updated = False
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if not params is None:
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do_repl = DoReplParam(params)
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pattern = re_pattern_args(params)
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new_text = re.sub(pattern, do_repl, text)
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if do_repl.expanded:
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text = new_text
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params_updated = True
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do_repl = DoReplMacro()
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new_text = re.sub(vl_expand_re, do_repl, text)
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has_func = do_repl.has_func
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if not do_repl.expanded:
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has_func = do_repl.has_func
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if not (params_updated or do_repl.expanded):
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break
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text = new_text
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changed = True
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@@ -291,7 +378,28 @@ def load_config(filename):
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print("condfig=", config)
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return config
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def gen_vl_header(file, taps, triggers):
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def eval_node(text, params):
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def clog2(x):
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l2 = math.log2(x)
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cl = math.ceil(l2)
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return int(cl)
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if not type(text) == str:
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return text
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expanded = expand_text(text, params)
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if expanded:
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text = expanded
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try:
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__text = text.replace('$clog2', '__clog2')
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__text = translate_ternary(__text)
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e = eval(__text, {'__clog2': clog2})
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return e
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except (NameError, SyntaxError):
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return text
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def gen_vl_header(file, modules, taps):
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header = '''
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`ifndef VX_SCOPE_DEFS
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@@ -299,238 +407,274 @@ def gen_vl_header(file, taps, triggers):
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'''
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footer = '`endif'
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def signal_size(size, asize):
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str_asize = ""
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for s in asize:
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if type(s) == int:
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str_asize += "[" + str(s-1) + ":0]"
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else:
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str_asize += "[" + str(s) + "-1:0]"
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def signal_size(size, mn):
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if type(size) == int:
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size1 = (size-1)
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if size1 != 0:
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return str_asize + "[" + str(size1) + ":0]"
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if (size != mn):
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return "[" + str(size-1) + ":0]"
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else:
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return str_asize
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return ""
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else:
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return str_asize + "[(" + size + ")-1:0]"
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return "[" + size + "-1:0]"
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def generate_ports(tclass, tap, ports, new_taps):
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def create_signal(key, ports):
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if not key in ports:
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ports[key] = []
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return ports[key]
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def emit_io(tap, ports, prefix, asize, return_list, new_taps, is_enabled):
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stap = tap + "_IO"
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new_taps.append(stap)
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print("`define " + stap + " \\", file=f)
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if is_enabled:
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for key in ports:
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size = ports[key]
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name = key
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is_trigger = False
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if name[0] == '!':
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name = name[1:]
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is_trigger = True
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if not return_list is None:
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return_list.append((name + prefix, size, asize, is_trigger))
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print("\toutput wire" + signal_size(size, asize) + " " + name + prefix + ", \\", file=f)
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print("", file=f)
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emit_bind(tap, ports, prefix, prefix, new_taps, is_enabled)
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def emit_bind(tap, ports, from_prefix, to_prefix, new_taps, is_enabled):
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stap = tap + "_BIND"
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new_taps.append(stap)
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print("`define " + stap + " \\", file=f)
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for key in ports:
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name = key
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if name[0] == '!':
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name = name[1:]
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if is_enabled:
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print("\t." + name + to_prefix + " (" + name + from_prefix + "), \\", file=f)
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else:
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if (from_prefix != to_prefix):
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print("\t`UNUSED_PIN (" + name + to_prefix + "), \\", file=f)
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print("", file=f)
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def emit_select(tap, ports, from_prefix, to_prefix, new_taps, is_enabled):
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stap = tap + "_SELECT(__i__)"
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new_taps.append(stap)
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print("`define " + stap + " \\", file=f)
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if is_enabled:
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for key in ports:
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name = key
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if name[0] == '!':
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name = name[1:]
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print("\t." + name + to_prefix + " (" + name + from_prefix + "[__i__]), \\", file=f)
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print("", file=f)
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def do_top(tap, ports, new_taps):
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out_ports = []
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for p in ports:
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name = p
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is_trigger = False
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if name[0] == '!':
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name = name[1:]
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is_trigger = True
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out_ports.append((name, ports[p], [], is_trigger))
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return out_ports
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def do_core(tap, ports, new_taps):
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out_ports = []
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nclusters = parameters["NUM_CLUSTERS"]
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ncores = parameters["NUM_CORES"]
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emit_io(tap + "_TOP", ports, "_top", [nclusters, ncores], out_ports, new_taps, True)
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emit_io(tap + "_CLUSTER", ports, "_cluster", [ncores], None, new_taps, True)
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emit_io(tap + "", ports, "", [], None, new_taps, True)
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emit_select(tap + "_CLUSTER", ports, "_top", "_cluster", new_taps, True)
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emit_select(tap + "", ports, "_cluster", "", new_taps, True)
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return out_ports
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def do_bank(tap, ports, new_taps):
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out_ports = []
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nclusters = parameters["NUM_CLUSTERS"]
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ncores = parameters["NUM_CORES"]
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has_l3 = (parameters["L3_ENABLE"] != 0)
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has_l2 = (parameters["L2_ENABLE"] != 0)
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emit_io(tap + "_L3_TOP", ports, "_l3_cache", [parameters["L3NUM_BANKS"]], out_ports, new_taps, has_l3)
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emit_io(tap + "_L2_TOP", ports, "_l2_top", [nclusters, parameters["L2NUM_BANKS"]], out_ports, new_taps, has_l2)
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emit_io(tap + "_L1D_TOP", ports, "_l1d_top", [nclusters, ncores, parameters["DNUM_BANKS"]], out_ports, new_taps, True)
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emit_io(tap + "_L1I_TOP", ports, "_l1i_top", [nclusters, ncores, parameters["INUM_BANKS"]], out_ports, new_taps, True)
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emit_io(tap + "_L1S_TOP", ports, "_l1s_top", [nclusters, ncores, parameters["SNUM_BANKS"]], out_ports, new_taps, True)
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emit_io(tap + "_L2_CLUSTER", ports, "_l2_cache", [parameters["L2NUM_BANKS"]], None, new_taps, has_l2)
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emit_io(tap + "_L1D_CLUSTER", ports, "_l1d_cluster", [ncores, parameters["DNUM_BANKS"]], None, new_taps, True)
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emit_io(tap + "_L1I_CLUSTER", ports, "_l1i_cluster", [ncores, parameters["INUM_BANKS"]], None, new_taps, True)
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emit_io(tap + "_L1S_CLUSTER", ports, "_l1s_cluster", [ncores, parameters["SNUM_BANKS"]], None, new_taps, True)
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emit_io(tap + "_L1D_CORE", ports, "_l1d_cache", [parameters["DNUM_BANKS"]], None, new_taps, True)
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emit_io(tap + "_L1I_CORE", ports, "_l1i_cache", [parameters["INUM_BANKS"]], None, new_taps, True)
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emit_io(tap + "_L1S_CORE", ports, "_l1s_cache", [parameters["SNUM_BANKS"]], None, new_taps, True)
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emit_io(tap + "_CACHE", ports, "_cache", ["NUM_BANKS"], None, new_taps, True)
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emit_io(tap + "", ports, "", [], None, new_taps, True)
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emit_select(tap + "_L2_CLUSTER", ports, "_l2_top", "_l2_cache", new_taps, has_l2)
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emit_select(tap + "_L1D_CLUSTER", ports, "_l1d_top", "_l1d_cluster", new_taps, True)
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emit_select(tap + "_L1I_CLUSTER", ports, "_l1i_top", "_l1i_cluster", new_taps, True)
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emit_select(tap + "_L1S_CLUSTER", ports, "_l1s_top", "_l1s_cluster", new_taps, True)
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emit_select(tap + "_L1D_CORE", ports, "_l1d_cluster", "_l1d_cache", new_taps, True)
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emit_select(tap + "_L1I_CORE", ports, "_l1i_cluster", "_l1i_cache", new_taps, True)
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emit_select(tap + "_L1S_CORE", ports, "_l1s_cluster", "_l1s_cache", new_taps, True)
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emit_bind(tap + "_L3_CACHE", ports, "_l3_cache", "_cache", new_taps, has_l3)
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emit_bind(tap + "_L2_CACHE", ports, "_l2_cache", "_cache", new_taps, has_l2)
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emit_bind(tap + "_L1D_CACHE", ports, "_l1d_cache", "_cache", new_taps, True)
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emit_bind(tap + "_L1I_CACHE", ports, "_l1i_cache", "_cache", new_taps, True)
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emit_bind(tap + "_L1S_CACHE", ports, "_l1s_cache", "_cache", new_taps, True)
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emit_select(tap + "", ports, "_cache", "", new_taps, True)
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return out_ports
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callbacks = {
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"top": do_top,
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"core": do_core,
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"bank": do_bank
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}
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return callbacks[tclass](tap, ports, new_taps)
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def trigger_size(name, ports):
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for port in ports:
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if port[0] == name:
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return (port[1], port[2])
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return None
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def trigger_prefices(asize):
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def Q(arr, ss, asize, idx, N):
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for i in range(asize[idx]):
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tmp = ss + '[' + str(i) + ']'
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if (idx + 1) < N:
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Q(arr, tmp, asize, idx + 1, N)
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else:
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arr.append(tmp)
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l = len(asize)
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if l == 0:
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return [""]
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arr = []
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Q(arr, "", asize, 0, l)
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return arr
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def dic_insert(gdic, ldic, key, value, enabled):
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if enabled:
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ldic[key] = value
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if key in gdic:
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return False
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if enabled:
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gdic[key] = None
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return True
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def trigger_name(name, size):
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if type(size) == int:
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size1 = (size-1)
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if size1 != 0:
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if size != 1:
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return "(| " + name + ")"
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else:
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return name
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else:
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return "(| " + name + ")"
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with open(file, 'w') as f:
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def trigger_subscripts(asize):
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def Q(arr, ss, asize, idx, N):
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a = asize[idx]
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if (a != 0):
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for i in range(a):
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tmp = ss + '[' + str(i) + ']'
|
||||
if (idx + 1) < N:
|
||||
Q(arr, tmp, asize, idx + 1, N)
|
||||
else:
|
||||
arr.append(tmp)
|
||||
else:
|
||||
if (idx + 1) < N:
|
||||
Q(arr, ss, asize, idx + 1, N)
|
||||
else:
|
||||
arr.append(ss)
|
||||
|
||||
if asize is None:
|
||||
return [""]
|
||||
ln = len(asize)
|
||||
if (0 == ln):
|
||||
return [""]
|
||||
arr = []
|
||||
Q(arr, "", asize, 0, ln)
|
||||
return arr
|
||||
|
||||
|
||||
def visit_path(alltaps, ports, path, node, paths, modules, taps):
|
||||
ntype = node["type"]
|
||||
|
||||
enabled = True
|
||||
if "enabled" in node:
|
||||
enabled = eval_node(node["enabled"], None)
|
||||
|
||||
curtaps = {}
|
||||
|
||||
if (len(paths) != 0):
|
||||
spath = paths.pop(0)
|
||||
snodes = modules[ntype]["submodules"]
|
||||
if not spath in snodes:
|
||||
raise Exception("invalid path: " + spath + " in " + path)
|
||||
snode = snodes[spath]
|
||||
|
||||
subtaps = visit_path(alltaps, ports, spath, snode, paths, modules, taps)
|
||||
|
||||
scount = 0
|
||||
if "count" in snode:
|
||||
scount = eval_node(snode["count"], None)
|
||||
|
||||
params = None
|
||||
if "params" in snode:
|
||||
params = snode["params"]
|
||||
|
||||
new_staps = []
|
||||
|
||||
nn = "SCOPE_IO_" + ntype
|
||||
pp = create_signal(nn, ports)
|
||||
for key in subtaps:
|
||||
subtap = subtaps[key]
|
||||
s = subtap[0]
|
||||
a = subtap[1]
|
||||
t = subtap[2]
|
||||
e = subtap[3]
|
||||
|
||||
s = eval_node(s, params)
|
||||
|
||||
e = eval_node(e, params)
|
||||
if type(e) == str or type(enabled) == str:
|
||||
me = str(e) + " and " + str(enabled)
|
||||
else:
|
||||
me = e and enabled
|
||||
|
||||
aa = [scount]
|
||||
sa = signal_size(scount, 0)
|
||||
if a:
|
||||
for i in a:
|
||||
x = eval_node(i, params)
|
||||
aa.append(x)
|
||||
sa += signal_size(x, 0)
|
||||
|
||||
if dic_insert(alltaps, curtaps, spath + '/' + key, (s, aa, t, me), e):
|
||||
skey = key.replace('/', '_')
|
||||
if e:
|
||||
pp.append("\toutput wire" + sa + signal_size(s, 1) + " scope_" + spath + '_' + skey + ',')
|
||||
new_staps.append(skey)
|
||||
|
||||
ports[nn] = pp
|
||||
|
||||
if (0 == scount):
|
||||
nn = "SCOPE_BIND_" + ntype + '_' + spath + "()"
|
||||
pp = create_signal(nn, ports)
|
||||
for st in new_staps:
|
||||
if e:
|
||||
pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "),")
|
||||
else:
|
||||
pp.append("\t`UNUSED_PIN (scope_" + st + "),")
|
||||
ports[nn] = pp
|
||||
else:
|
||||
nn = "SCOPE_BIND_" + ntype + '_' + spath + "(__i__)"
|
||||
pp = create_signal(nn, ports)
|
||||
for st in new_staps:
|
||||
if e:
|
||||
pp.append("\t.scope_" + st + "(scope_" + spath + '_' + st + "[__i__]),")
|
||||
else:
|
||||
pp.append("\t`UNUSED_PIN (scope_" + st + "),")
|
||||
ports[nn] = pp
|
||||
else:
|
||||
nn = "SCOPE_IO_" + ntype
|
||||
pp = create_signal(nn, ports)
|
||||
for tk in taps:
|
||||
trigger = 0
|
||||
name = tk
|
||||
size = eval_node(taps[tk], None)
|
||||
if name[0] == '!':
|
||||
name = name[1:]
|
||||
trigger = 1
|
||||
elif name[0] == '?':
|
||||
name = name[1:]
|
||||
trigger = 2
|
||||
if dic_insert(alltaps, curtaps, name, (size, None, trigger, enabled), True):
|
||||
pp.append("\toutput wire" + signal_size(size, 1) + " scope_" + name + ',')
|
||||
|
||||
ports[nn] = pp
|
||||
|
||||
return curtaps
|
||||
|
||||
toptaps = {}
|
||||
|
||||
with open(file, 'w') as f:
|
||||
|
||||
top = modules['*']
|
||||
snodes = top["submodules"]
|
||||
|
||||
ports = {}
|
||||
alltaps = {}
|
||||
|
||||
for key in taps:
|
||||
skey_list = key.split(',')
|
||||
_taps = taps[key]
|
||||
for skey in skey_list:
|
||||
print('processing node: ' + skey + ' ...')
|
||||
paths = skey.strip().split('/')
|
||||
spath = paths.pop(0)
|
||||
if not spath in snodes:
|
||||
raise Exception("invalid path: " + spath)
|
||||
snode = snodes[spath]
|
||||
curtaps = visit_path(alltaps, ports, spath, snode, paths, modules, _taps)
|
||||
for tk in curtaps:
|
||||
toptaps[tk] = curtaps[tk]
|
||||
|
||||
print(header, file=f)
|
||||
|
||||
all_ports = []
|
||||
new_taps = []
|
||||
for key in ports:
|
||||
print("`define " + key + ' \\', file=f)
|
||||
for port in ports[key]:
|
||||
print(port + ' \\', file=f)
|
||||
print("", file=f)
|
||||
|
||||
for key in taps:
|
||||
[tclass, tap] = key.split('::')
|
||||
ports = generate_ports(tclass, tap, taps[key], new_taps)
|
||||
for port in ports:
|
||||
all_ports.append(port)
|
||||
|
||||
print("`define SCOPE_SIGNALS_DECL \\", file=f)
|
||||
i = 0
|
||||
for port in all_ports:
|
||||
print("`define SCOPE_DECL_SIGNALS \\", file=f)
|
||||
i = 0
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
name = key.replace('/', '_')
|
||||
size = tap[0]
|
||||
asize = tap[1]
|
||||
enabled = tap[3]
|
||||
sa = ""
|
||||
if asize:
|
||||
for a in asize:
|
||||
sa += signal_size(a, 0)
|
||||
if i > 0:
|
||||
print(" \\", file=f)
|
||||
print("\twire" + signal_size(port[1], port[2]) + " " + port[0] + ";", file=f, end='')
|
||||
if not enabled:
|
||||
print("`IGNORE_WARNINGS_BEGIN \\", file=f)
|
||||
print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + '; \\', file=f)
|
||||
print("`IGNORE_WARNINGS_END", file=f, end='')
|
||||
else:
|
||||
print('\t wire' + sa + signal_size(size, 1) + " scope_" + name + ';', file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_SIGNALS_DATA_LIST \\", file=f)
|
||||
print("`define SCOPE_DATA_LIST \\", file=f)
|
||||
i = 0
|
||||
for port in all_ports:
|
||||
if port[3]:
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
if tap[2] != 0:
|
||||
continue
|
||||
name = key.replace('/', '_')
|
||||
if i > 0:
|
||||
print(", \\", file=f)
|
||||
print("\t" + port[0], file=f, end='')
|
||||
print("\t scope_" + name, file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_SIGNALS_UPD_LIST \\", file=f)
|
||||
print("`define SCOPE_UPDATE_LIST \\", file=f)
|
||||
i = 0
|
||||
for port in all_ports:
|
||||
if not port[3]:
|
||||
for key in toptaps:
|
||||
tap = toptaps[key]
|
||||
if tap[2] == 0:
|
||||
continue
|
||||
name = key.replace('/', '_')
|
||||
if i > 0:
|
||||
print(", \\", file=f)
|
||||
print("\t" + port[0], file=f, end='')
|
||||
print("\t scope_" + name, file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("", file=f)
|
||||
|
||||
print("`define SCOPE_TRIGGERS \\", file=f)
|
||||
print("`define SCOPE_TRIGGER \\", file=f)
|
||||
i = 0
|
||||
for trigger in triggers:
|
||||
arr = trigger_size(trigger[0], all_ports)
|
||||
if arr is None:
|
||||
excluded_list = []
|
||||
for key in toptaps:
|
||||
if key in excluded_list:
|
||||
continue
|
||||
[size, asize] = arr
|
||||
for prefix in trigger_prefices(asize):
|
||||
tap = toptaps[key]
|
||||
if tap[2] != 2:
|
||||
continue
|
||||
size = tap[0]
|
||||
asize = tap[1]
|
||||
sus = trigger_subscripts(asize)
|
||||
for su in sus:
|
||||
if i > 0:
|
||||
print(" | \\", file=f)
|
||||
print("\t(", file=f, end='')
|
||||
for j in range(len(trigger)):
|
||||
if j > 0:
|
||||
print(" && ", file=f, end='')
|
||||
print(trigger_name(trigger[j] + prefix, size), file=f, end='')
|
||||
print(" | \\", file=f)
|
||||
print("\t(", file=f, end='')
|
||||
name = trigger_name("scope_" + key.replace('/', '_') + su, size)
|
||||
if key.endswith("_valid"):
|
||||
ready_signal = key[:-6] + "_ready"
|
||||
if ready_signal in toptaps:
|
||||
rname = trigger_name("scope_" + ready_signal.replace('/', '_') + su, size)
|
||||
print(name + " && " + rname, file=f, end='')
|
||||
excluded_list.append(ready_signal)
|
||||
else:
|
||||
print(name, file=f, end='')
|
||||
else:
|
||||
print(name, file=f, end='')
|
||||
print(")", file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
@@ -538,69 +682,110 @@ def gen_vl_header(file, taps, triggers):
|
||||
|
||||
print(footer, file=f)
|
||||
|
||||
return all_ports
|
||||
return toptaps
|
||||
|
||||
def gen_cc_header(file, ports):
|
||||
def gen_cc_header(file, taps):
|
||||
|
||||
header = '''
|
||||
#pragma once\n
|
||||
struct scope_signal_t {
|
||||
#pragma once
|
||||
|
||||
struct scope_module_t {
|
||||
const char* name;
|
||||
int index;
|
||||
int parent;
|
||||
};
|
||||
|
||||
struct scope_tap_t {
|
||||
int width;
|
||||
const char* name;
|
||||
};\n
|
||||
inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
|
||||
static constexpr scope_signal_t scope_signals[] = {'''
|
||||
|
||||
footer = "};"
|
||||
|
||||
def eval_macro(text):
|
||||
expanded = expand_text(text)
|
||||
if expanded:
|
||||
text = expanded
|
||||
text = text.replace('$clog2', '__clog2')
|
||||
return text
|
||||
|
||||
def asize_name(asize):
|
||||
def Q(arr, ss, asize, idx, N):
|
||||
for i in range(asize[idx]):
|
||||
tmp = ss + "_" + str(i)
|
||||
int module;
|
||||
};
|
||||
'''
|
||||
def flatten_path(paths, sizes):
|
||||
def Q(arr, ss, idx, N, paths, sizes):
|
||||
size = sizes[idx]
|
||||
if size != 0:
|
||||
for i in range(sizes[idx]):
|
||||
tmp = ss + ('/' if (ss != '') else '')
|
||||
tmp += paths[idx] + '_' + str(i)
|
||||
if (idx + 1) < N:
|
||||
Q(arr, tmp, idx + 1, N, paths, sizes)
|
||||
else:
|
||||
arr.append(tmp)
|
||||
else:
|
||||
tmp = ss + ('/' if (ss != '') else '')
|
||||
tmp += paths[idx]
|
||||
if (idx + 1) < N:
|
||||
Q(arr, tmp, asize, idx + 1, N)
|
||||
Q(arr, tmp, idx + 1, N, paths, sizes)
|
||||
else:
|
||||
arr.append(tmp)
|
||||
arr.append(tmp)
|
||||
|
||||
l = len(asize)
|
||||
if l == 0:
|
||||
return [""]
|
||||
arr = []
|
||||
Q(arr, "", asize, 0, l)
|
||||
return arr
|
||||
Q(arr, "", 0, len(asize), paths, asize)
|
||||
return arr
|
||||
|
||||
# flatten the taps
|
||||
fdic = {}
|
||||
for key in taps:
|
||||
tap = taps[key]
|
||||
size = str(tap[0])
|
||||
paths = key.split('/')
|
||||
if (len(paths) > 1):
|
||||
name = paths.pop(-1)
|
||||
asize = tap[1]
|
||||
for ss in flatten_path(paths, asize):
|
||||
fdic[ss + '/' + name ] = [size, -1]
|
||||
else:
|
||||
fdic[key] = [size, -1]
|
||||
|
||||
# generate module dic
|
||||
mdic = {}
|
||||
for key in fdic:
|
||||
paths = key.split('/')
|
||||
if len(paths) == 1:
|
||||
continue
|
||||
paths.pop(-1)
|
||||
parent = -1
|
||||
for path in paths:
|
||||
if not path in mdic:
|
||||
index = len(mdic)
|
||||
mdic[path] = (index, parent)
|
||||
parent = index
|
||||
else:
|
||||
parent = mdic[path][0]
|
||||
fdic[key][1] = parent
|
||||
|
||||
with open(file, 'w') as f:
|
||||
print(header, file=f)
|
||||
|
||||
print("static constexpr scope_module_t scope_modules[] = {", file=f)
|
||||
i = 0
|
||||
for port in ports:
|
||||
if port[3]:
|
||||
continue
|
||||
name = port[0]
|
||||
size = eval_macro(str(port[1]))
|
||||
for ss in asize_name(port[2]):
|
||||
if i > 0:
|
||||
print(",", file=f)
|
||||
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
|
||||
i += 1
|
||||
for port in ports:
|
||||
if not port[3]:
|
||||
continue
|
||||
name = port[0]
|
||||
size = eval_macro(str(port[1]))
|
||||
for ss in asize_name(port[2]):
|
||||
if i > 0:
|
||||
print(",", file=f)
|
||||
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
|
||||
i += 1
|
||||
for key in mdic:
|
||||
m = mdic[key]
|
||||
if i > 0:
|
||||
print(',', file=f)
|
||||
print("\t{\"" + key + "\", " + str(m[0]) + ", " + str(m[1]) + "}", file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print(footer, file=f)
|
||||
print("};", file=f)
|
||||
|
||||
print("", file=f)
|
||||
print("static constexpr scope_tap_t scope_taps[] = {", file=f)
|
||||
i = 0
|
||||
for key in fdic:
|
||||
size = fdic[key][0]
|
||||
parent = fdic[key][1]
|
||||
paths = key.split('/')
|
||||
if len(paths) > 1:
|
||||
name = paths.pop(-1)
|
||||
else:
|
||||
name = key
|
||||
if i > 0:
|
||||
print(',', file=f)
|
||||
print("\t{" + size + ", \"" + name + "\", " + str(parent) + "}", file=f, end='')
|
||||
i += 1
|
||||
print("", file=f)
|
||||
print("};", file=f)
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description='Scope headers generator.')
|
||||
@@ -612,7 +797,6 @@ def main():
|
||||
args = parser.parse_args()
|
||||
print("args=", args)
|
||||
|
||||
global parameters
|
||||
global exclude_files
|
||||
global include_dirs
|
||||
global macros
|
||||
@@ -630,13 +814,9 @@ def main():
|
||||
|
||||
if "includes" in config:
|
||||
parse_includes(config["includes"])
|
||||
|
||||
parameters = config["parameters"]
|
||||
for key in parameters:
|
||||
parameters[key] = int(eval(expand_text(str(parameters[key]))))
|
||||
|
||||
ports = gen_vl_header(args.vl, config["taps"], config["triggers"])
|
||||
gen_cc_header(args.cc, ports)
|
||||
taps = gen_vl_header(args.vl, config["modules"], config["taps"])
|
||||
gen_cc_header(args.cc, taps)
|
||||
|
||||
if __name__ == "__main__":
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
Reference in New Issue
Block a user