fixed all build warnings
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6
hw/rtl/cache/VX_d_cache_tb.v
vendored
6
hw/rtl/cache/VX_d_cache_tb.v
vendored
@@ -3,7 +3,7 @@
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module VX_d_cache_tb;
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parameter NUMBER_BANKS = 8;
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parameter NUM_BANKS = 8;
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reg clk, reset, im_ready;
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reg [`NUM_THREADS-1:0] i_p_valid;
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@@ -16,9 +16,9 @@ module VX_d_cache_tb;
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reg o_p_waitrequest;
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reg [13:0] o_m_addr; // Only one address is sent out at a time to memory
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reg o_m_valid;
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reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
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reg [(NUM_BANKS * 32) - 1:0] o_m_writedata;
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reg o_m_read_or_write; //, o_m_write;
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reg [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
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reg [(NUM_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
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VX_d_cache d_cache(.clk(clk),
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