wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fixed all build warnings

Browse Source
This commit is contained in:
Blaise Tine
2020-04-16 10:22:46 -04:00
parent 81745f08c9
commit 31f906f9fd
42 changed files with 497 additions and 509 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
hw/rtl/cache/VX_cache_bank_valid.v vendored
View File

@@ -2,14 +2,14 @@
module VX_cache_bank_valid
#(
parameter NUMBER_BANKS = 8,
parameter NUM_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 1
)
(
input wire [NUM_REQ-1:0] i_p_valid,
input wire [NUM_REQ-1:0][31:0] i_p_addr,
output reg [NUMBER_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks
output reg [NUM_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks
);
generate
@@ -18,7 +18,7 @@ module VX_cache_bank_valid
thread_track_banks = 0;
for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
begin
if (NUMBER_BANKS != 1) begin
if (NUM_BANKS != 1) begin
thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
end else begin
thread_track_banks[0][t_id] = i_p_valid[t_id];