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merged fpu_port branch

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This commit is contained in:
Blaise Tine
2020-07-31 17:13:22 -04:00
parent 4bdab8903e 836a735555
commit 31ee824862
508 changed files with 45407 additions and 41832 deletions
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74
hw/rtl/libs/VX_cam_buffer.v Normal file
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@@ -0,0 +1,74 @@
`include "VX_platform.vh"
module VX_cam_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter RPORTS = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
input wire [DATAW-1:0] write_data,
output wire [ADDRW-1:0] write_addr,
input wire acquire_slot,
input wire [RPORTS-1:0][ADDRW-1:0] read_addr,
output reg [RPORTS-1:0][DATAW-1:0] read_data,
input wire [RPORTS-1:0] release_slot,
output wire full
);
reg [DATAW-1:0] entries [SIZE-1:0];
reg [SIZE-1:0] free_slots, free_slots_n;
reg [ADDRW-1:0] write_addr_r;
reg full_r;
wire free_valid;
wire [ADDRW-1:0] free_index;
VX_priority_encoder #(
.N(SIZE)
) free_slots_encoder (
.data_in (free_slots_n),
.data_out (free_index),
.valid_out (free_valid)
);
integer i;
always @(*) begin
free_slots_n = free_slots;
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
end
for (i = 0; i < RPORTS; i++) begin
if (release_slot[i]) begin
free_slots_n[read_addr[i]] = 1;
end
read_data[i] = entries[read_addr[i]];
end
end
always @(posedge clk) begin
if (reset) begin
free_slots <= {SIZE{1'b1}};
full_r <= 1'b0;
write_addr_r <= ADDRW'(1'b0);
end else begin
if (acquire_slot) begin
assert(1 == free_slots[write_addr]);
entries[write_addr] <= write_data;
end
for (i = 0; i < RPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[read_addr[i]]);
end
end
free_slots <= free_slots_n;
write_addr_r <= free_index;
full_r <= ~free_valid;
end
end
assign write_addr = write_addr_r;
assign full = full_r;
endmodule

3
hw/rtl/libs/VX_countones.v
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@@ -1,3 +1,6 @@
`include "VX_platform.vh"
module VX_countones #(
parameter N = 10
) (

23
hw/rtl/libs/VX_divide.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_divide #(
parameter WIDTHN = 1,
@@ -12,6 +12,7 @@ module VX_divide #(
input wire clk,
input wire reset,
input wire clk_en,
input wire [WIDTHN-1:0] numer,
input wire [WIDTHD-1:0] denom,
@@ -31,7 +32,7 @@ module VX_divide #(
.quotient (quotient_unqual),
.remain (remainder_unqual),
.aclr (1'b0),
.clken (1'b1)
.clken (clk_en)
);
defparam
@@ -43,8 +44,8 @@ module VX_divide #(
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE;
assign quotient = quotient_unqual[WIDTHQ-1:0];
assign remainder = remainder_unqual[WIDTHR-1:0];
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
`else
@@ -82,8 +83,8 @@ module VX_divide #(
end
if (PIPELINE == 0) begin
assign quotient = quotient_unqual[WIDTHQ-1:0];
assign remainder = remainder_unqual[WIDTHR-1:0];
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
end else begin
reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1];
@@ -95,14 +96,14 @@ module VX_divide #(
quotient_pipe[i] <= 0;
remainder_pipe[i] <= 0;
end
else begin
else if (clk_en) begin
if (i == 0) begin
quotient_pipe[0] <= quotient_unqual;
remainder_pipe[0] <= remainder_unqual;
quotient_pipe[i] <= quotient_unqual;
remainder_pipe[i] <= remainder_unqual;
end else begin
quotient_pipe[i] <= quotient_pipe[i-1];
remainder_pipe[i] <= remainder_pipe[i-1];
end
remainder_pipe[i] <= remainder_pipe[i-1];
end
end
end
end

2
hw/rtl/libs/VX_fair_arbiter.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_fair_arbiter #(
parameter N = 1

2
hw/rtl/libs/VX_fixed_arbiter.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_fixed_arbiter #(
parameter N = 1

16
hw/rtl/libs/VX_generic_queue.v
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@@ -1,9 +1,9 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_generic_queue #(
parameter DATAW = 0,
parameter SIZE = 1,
parameter BUFFERED_OUTPUT = 1
parameter DATAW = 1,
parameter SIZE = 16,
parameter BUFFERED = 1
) (
input wire clk,
input wire reset,
@@ -52,13 +52,9 @@ module VX_generic_queue #(
end else begin // (SIZE > 1)
`ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
`else
reg [DATAW-1:0] data [SIZE-1:0];
`endif
`USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0];
if (0 == BUFFERED_OUTPUT) begin
if (0 == BUFFERED) begin
reg [`LOG2UP(SIZE):0] rd_ptr_r;
reg [`LOG2UP(SIZE):0] wr_ptr_r;

2
hw/rtl/libs/VX_generic_register.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_generic_register #(
parameter N = 1,

32
hw/rtl/libs/VX_generic_stack.v
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@@ -1,32 +0,0 @@
module VX_generic_stack #(
parameter WIDTH = 1,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire push,
input wire pop,
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
);
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
always @(posedge clk) begin
if (reset) begin
ptr <= 0;
end else if (push) begin
stack[ptr] <= q1;
stack[ptr+1] <= q2;
ptr <= ptr + 2;
end else if (pop) begin
ptr <= ptr - 1;
end
end
assign d = stack[ptr - 1];
endmodule

4
hw/rtl/libs/VX_index_queue.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_index_queue #(
parameter DATAW = 1,
@@ -15,7 +15,7 @@ module VX_index_queue #(
input wire [`LOG2UP(SIZE)-1:0] read_addr,
output wire [DATAW-1:0] read_data
);
reg [DATAW-1:0] data [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] data [SIZE-1:0];
reg [SIZE-1:0] valid;
reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;

2
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_matrix_arbiter #(
parameter N = 1

15
hw/rtl/libs/VX_mult.v → hw/rtl/libs/VX_multiplier.v
View File

@@ -1,6 +1,6 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_mult #(
module VX_multiplier #(
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
@@ -10,6 +10,7 @@ module VX_mult #(
input wire clk,
input wire reset,
input wire clk_en,
input wire [WIDTHA-1:0] dataa,
input wire [WIDTHB-1:0] datab,
output wire [WIDTHP-1:0] result
@@ -24,7 +25,7 @@ module VX_mult #(
.result (result),
.sclr (reset),
.aclr (1'b0),
.clken (1'b1),
.clken (clk_en),
.sum (1'b0)
);
@@ -49,7 +50,7 @@ module VX_mult #(
assign result = result_unqual;
end else begin
reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE; i++) begin
@@ -57,12 +58,12 @@ module VX_mult #(
if (reset) begin
result_pipe[i] <= 0;
end
else begin
else if (clk_en) begin
if (i == 0) begin
result_pipe[0] <= result_unqual;
result_pipe[i] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end
end
end
end

2
hw/rtl/libs/VX_onehot_encooder.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_onehot_encoder #(
parameter N = 6

3
hw/rtl/libs/VX_priority_encoder.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_priority_encoder #(
parameter N = 1
@@ -8,6 +8,7 @@ module VX_priority_encoder #(
output reg valid_out
);
integer i;
always @(*) begin
data_out = 0;
valid_out = 0;

2
hw/rtl/libs/VX_rr_arbiter.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_rr_arbiter #(
parameter N = 1

2
hw/rtl/libs/VX_scope.v
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@@ -1,4 +1,4 @@
`include "VX_define.vh"
`include "VX_platform.vh"
module VX_scope #(
parameter DATAW = 64,

50
hw/rtl/libs/VX_shift_register.v Normal file
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@@ -0,0 +1,50 @@
`include "VX_platform.vh"
module VX_shift_register #(
parameter DATAW = 1,
parameter DEPTH = 0
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] in,
output wire [DATAW-1:0] out
);
if (0 == DEPTH) begin
assign out = in;
end if (1 == DEPTH) begin
reg [DATAW-1:0] ram;
always @(posedge clk) begin
if (reset) begin
ram <= '0;
end else begin
if (enable) begin
ram <= in;
end
end
end
assign out = ram;
end else begin
reg [DEPTH-1:0][DATAW-1:0] ram;
always @(posedge clk) begin
if (reset) begin
ram <= '0;
end else begin
if (enable) begin
ram <= {ram[DEPTH-2:0], in};
end
end
end
assign out = ram [DEPTH-1];
end
endmodule