Changed tb

2019-11-10 15:06:06 -05:00
parent b3c7ac435a
commit 31de18c328
2 changed files with 2 additions and 2 deletions
--- a/rtl/cache/VX_cache_data.v
+++ b/rtl/cache/VX_cache_data.v
@@ -116,7 +116,7 @@ module VX_cache_data

        // Using ASIC MEM
        /* verilator lint_off PINCONNECTEMPTY */
-       rf2_256x128_wm1 data (
+       rf2_32x128_wm1 data (
             .CENYA(),
             .AYA(),
             .CENYB(),