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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 08:45:46 -04:00
parent 164eb5454c
commit 3139d37610
62 changed files with 261 additions and 256 deletions
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6
hw/rtl/compat/VX_divide.v
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@@ -25,9 +25,9 @@ module VX_divide #(
generate
if (NREP != DREP) begin
/* verilator lint_off DECLFILENAME */
`IGNORE_WARNINGS_BEGIN
different_nrep_drep_not_yet_supported non_existing_module();
/* verilator lint_on DECLFILENAME */
`IGNORE_WARNINGS_END
end
if (IMPL == "quartus") begin
@@ -98,7 +98,7 @@ module VX_divide #(
if (NREP == "SIGNED") begin
/*VX_divide_internal_signed #(
/*VX_divide_ifnal_signed #(
.WIDTHN,
.WIDTHD
)div(

4
hw/rtl/compat/VX_mult.v
View File

@@ -30,7 +30,7 @@ module VX_mult #(
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
/* verilator lint_off DECLFILENAME */
`IGNORE_WARNINGS_BEGIN
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
@@ -47,7 +47,7 @@ module VX_mult #(
.datab(datab),
.result(result)
);
/* verilator lint_on DECLFILENAME */
`IGNORE_WARNINGS_END
end
else begin
lpm_mult#(