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scope bug fixes

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This commit is contained in:
Blaise Tine
2020-10-06 03:59:27 -04:00
parent 4e1007e5b2
commit 309dd48fc6
8 changed files with 191 additions and 167 deletions
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37
hw/scripts/scope.json
View File

@@ -27,7 +27,7 @@
"scope_dram_req_tag": "`VX_DRAM_TAG_WIDTH",
"!scope_dram_req_ready": 1,
"!scope_dram_rsp_valid": 1,
"scope_dram_rsp_data": 128,
"scope_dram_rsp_data": "`VX_DRAM_LINE_WIDTH",
"scope_dram_rsp_tag": "`VX_DRAM_TAG_WIDTH",
"!scope_dram_rsp_ready": 1,
"!scope_snp_req_valid": 1,
@@ -83,7 +83,6 @@
"scope_issue_rs1_is_pc": 1,
"scope_issue_rs2_is_imm": 1,
"!scope_issue_ready": 1,
"!scope_gpr_rsp_valid": 1,
"scope_gpr_rsp_wid": "`NW_BITS",
"scope_gpr_rsp_pc": 32,
"scope_gpr_rsp_a": "`NUM_THREADS * 32",
@@ -121,41 +120,11 @@
["scope_icache_req_valid_top", "scope_icache_req_ready_top"],
["scope_icache_rsp_valid_top", "scope_icache_rsp_ready_top"],
["scope_dcache_req_valid_top", "scope_dcache_req_ready_top"],
["scope_dcache_rsp_valid_top", "scope_dcache_rsp_ready_top"],
["scope_bank_valid_st0_l3_top"],
["scope_bank_valid_st1_l3_top"],
["scope_bank_valid_st2_l3_top"],
["scope_bank_stall_pipe_l3_top"],
["scope_bank_valid_st0_l2_top"],
["scope_bank_valid_st1_l2_top"],
["scope_bank_valid_st2_l2_top"],
["scope_bank_stall_pipe_l2_top"],
["scope_bank_valid_st0_l1d_top"],
["scope_bank_valid_st1_l1d_top"],
["scope_bank_valid_st2_l1d_top"],
["scope_bank_stall_pipe_l1d_top"],
["scope_bank_valid_st0_l1i_top"],
["scope_bank_valid_st1_l1i_top"],
["scope_bank_valid_st2_l1i_top"],
["scope_bank_stall_pipe_l1i_top"],
["scope_bank_valid_st0_l1s_top"],
["scope_bank_valid_st1_l1s_top"],
["scope_bank_valid_st2_l1s_top"],
["scope_bank_stall_pipe_l1s_top"],
["scope_issue_valid_top", "scope_issue_ready_top"],
["scope_gpr_rsp_valid_top"],
["scope_scoreboard_delay_top"],
["scope_gpr_delay_top"],
["scope_execute_delay_top"],
["scope_busy"]
["scope_issue_valid_top", "scope_issue_ready_top"]
]
}

112
hw/scripts/scope.py
View File

@@ -291,56 +291,6 @@ def load_config(filename):
print("condfig=", config)
return config
def gen_cc_header(file, ports):
header = '''
#pragma once\n
struct scope_signal_t {
int width;
const char* name;
};\n
inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
static constexpr scope_signal_t scope_signals[] = {'''
footer = "};"
def eval_macro(text):
expanded = expand_text(text)
if expanded:
text = expanded
text = text.replace('$clog2', '__clog2')
return text
def asize_name(asize):
def Q(arr, ss, asize, idx, N):
for i in range(asize[idx]):
tmp = ss + "_" + str(i)
if (idx + 1) < N:
Q(arr, tmp, asize, idx + 1, N)
else:
arr.append(tmp)
l = len(asize)
if l == 0:
return [""]
arr = []
Q(arr, "", asize, 0, l)
return arr
with open(file, 'w') as f:
print(header, file=f)
i = 0
for port in ports:
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
print("", file=f)
print(footer, file=f)
def gen_vl_header(file, taps, triggers):
header = '''
@@ -590,6 +540,68 @@ def gen_vl_header(file, taps, triggers):
return all_ports
def gen_cc_header(file, ports):
header = '''
#pragma once\n
struct scope_signal_t {
int width;
const char* name;
};\n
inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
static constexpr scope_signal_t scope_signals[] = {'''
footer = "};"
def eval_macro(text):
expanded = expand_text(text)
if expanded:
text = expanded
text = text.replace('$clog2', '__clog2')
return text
def asize_name(asize):
def Q(arr, ss, asize, idx, N):
for i in range(asize[idx]):
tmp = ss + "_" + str(i)
if (idx + 1) < N:
Q(arr, tmp, asize, idx + 1, N)
else:
arr.append(tmp)
l = len(asize)
if l == 0:
return [""]
arr = []
Q(arr, "", asize, 0, l)
return arr
with open(file, 'w') as f:
print(header, file=f)
i = 0
for port in ports:
if port[3]:
continue
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
for port in ports:
if not port[3]:
continue
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
print("", file=f)
print(footer, file=f)
def main():
parser = argparse.ArgumentParser(description='Scope headers generator.')
parser.add_argument('-vl', nargs='?', default='scope-defs.vh', metavar='file', help='Output Verilog header')